Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	449	1			T10	11		T21	7		T57	4
all_values[1]	449	1			T10	11		T21	7		T57	4
all_values[2]	449	1			T10	11		T21	7		T57	4
all_values[3]	449	1			T10	11		T21	7		T57	4
all_values[4]	449	1			T10	11		T21	7		T57	4
all_values[5]	449	1			T10	11		T21	7		T57	4
all_values[6]	449	1			T10	11		T21	7		T57	4
all_values[7]	449	1			T10	11		T21	7		T57	4
all_values[8]	449	1			T10	11		T21	7		T57	4
all_values[9]	449	1			T10	11		T21	7		T57	4
all_values[10]	449	1			T10	11		T21	7		T57	4
all_values[11]	449	1			T10	11		T21	7		T57	4
all_values[12]	449	1			T10	11		T21	7		T57	4
all_values[13]	449	1			T10	11		T21	7		T57	4
all_values[14]	449	1			T10	11		T21	7		T57	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3559

1

T10

87

T21

57

T57

33

auto[1]

3176

1

T10

78

T21

48

T57

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T10

16

T21

25

T57

13

auto[1]

5729

1

T10

149

T21

80

T57

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3864

1

T10

97

T21

70

T57

38

auto[1]

2871

1

T10

68

T21

35

T57

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T21	2		T176	4		T201	1
all_values[0]	auto[0]	auto[0]	auto[1]	97	1			T10	2		T21	1		T57	1
all_values[0]	auto[0]	auto[1]	auto[0]	41	1			T21	2		T176	1		T207	2
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T10	4		T57	1		T22	2
all_values[0]	auto[1]	auto[0]	auto[1]	89	1			T10	2		T21	2		T57	1
all_values[0]	auto[1]	auto[1]	auto[1]	99	1			T10	3		T57	1		T22	2
all_values[1]	auto[0]	auto[0]	auto[0]	46	1			T21	2		T57	1		T176	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T10	2		T57	1		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	13	1			T57	1		T176	1		T198	1
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T10	4		T21	3		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	121	1			T10	3		T22	2		T176	3
all_values[1]	auto[1]	auto[1]	auto[1]	82	1			T10	2		T21	2		T57	1
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T10	2		T57	3		T198	1
all_values[2]	auto[0]	auto[0]	auto[1]	96	1			T10	2		T21	2		T22	4
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T10	2		T57	1		T36	1
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T10	1		T21	1		T22	2
all_values[2]	auto[1]	auto[0]	auto[1]	106	1			T10	4		T21	3		T22	1
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T21	1		T176	3		T36	6
all_values[3]	auto[0]	auto[0]	auto[0]	43	1			T22	1		T36	2		T137	1
all_values[3]	auto[0]	auto[0]	auto[1]	102	1			T10	2		T21	3		T57	2
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T21	2		T198	3		T207	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T10	5		T57	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	103	1			T10	1		T21	2		T22	2
all_values[3]	auto[1]	auto[1]	auto[1]	77	1			T10	3		T57	1		T176	2
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T10	2		T57	2		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T21	1		T22	1		T176	3
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T21	3		T57	2		T176	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T10	3		T22	3		T176	5
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T10	4		T21	2		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	85	1			T10	2		T21	1		T22	1
all_values[5]	auto[0]	auto[0]	auto[0]	29	1			T176	1		T208	1		T209	1
all_values[5]	auto[0]	auto[0]	auto[1]	107	1			T10	4		T176	3		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	16	1			T10	1		T176	3		T210	2
all_values[5]	auto[0]	auto[1]	auto[1]	97	1			T10	3		T21	5		T57	3
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T10	1		T21	2		T57	1
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T10	2		T22	2		T176	1
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T10	2		T21	1		T211	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T10	1		T57	1		T22	2
all_values[6]	auto[0]	auto[1]	auto[0]	31	1			T21	2		T198	5		T211	1
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T10	2		T21	1		T57	1
all_values[6]	auto[1]	auto[0]	auto[1]	99	1			T10	3		T21	2		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	94	1			T10	3		T21	1		T57	2
all_values[7]	auto[0]	auto[0]	auto[0]	31	1			T176	2		T36	1		T198	1
all_values[7]	auto[0]	auto[0]	auto[1]	93	1			T10	4		T57	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T21	1		T22	1		T176	3
all_values[7]	auto[0]	auto[1]	auto[1]	104	1			T10	2		T21	3		T22	2
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T10	4		T57	2		T22	1
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T10	1		T21	3		T57	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1			T137	2		T201	1		T202	1
all_values[8]	auto[0]	auto[0]	auto[1]	91	1			T10	4		T21	4		T22	3
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T10	1		T198	2		T212	2
all_values[8]	auto[0]	auto[1]	auto[1]	95	1			T10	3		T57	2		T36	4
all_values[8]	auto[1]	auto[0]	auto[1]	103	1			T10	2		T21	2		T57	1
all_values[8]	auto[1]	auto[1]	auto[1]	106	1			T10	1		T21	1		T57	1
all_values[9]	auto[0]	auto[0]	auto[0]	54	1			T10	1		T57	1		T198	1
all_values[9]	auto[0]	auto[0]	auto[1]	81	1			T10	1		T21	4		T57	2
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T198	1		T212	1		T207	3
all_values[9]	auto[0]	auto[1]	auto[1]	102	1			T10	3		T21	1		T22	1
all_values[9]	auto[1]	auto[0]	auto[1]	87	1			T10	5		T21	2		T57	1
all_values[9]	auto[1]	auto[1]	auto[1]	100	1			T10	1		T22	2		T176	4
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T10	2		T212	1		T213	2
all_values[10]	auto[0]	auto[0]	auto[1]	94	1			T10	3		T21	2		T57	1
all_values[10]	auto[0]	auto[1]	auto[0]	26	1			T57	1		T176	1		T198	2
all_values[10]	auto[0]	auto[1]	auto[1]	102	1			T21	3		T57	1		T22	2
all_values[10]	auto[1]	auto[0]	auto[1]	121	1			T10	3		T21	2		T57	1
all_values[10]	auto[1]	auto[1]	auto[1]	76	1			T10	3		T22	4		T36	3
all_values[11]	auto[0]	auto[0]	auto[0]	44	1			T212	4		T207	1		T214	1
all_values[11]	auto[0]	auto[0]	auto[1]	106	1			T10	2		T21	2		T57	1
all_values[11]	auto[0]	auto[1]	auto[0]	26	1			T212	1		T210	1		T202	1
all_values[11]	auto[0]	auto[1]	auto[1]	98	1			T10	4		T21	3		T22	3
all_values[11]	auto[1]	auto[0]	auto[1]	93	1			T10	4		T22	1		T176	1
all_values[11]	auto[1]	auto[1]	auto[1]	82	1			T10	1		T21	2		T57	3
all_values[12]	auto[0]	auto[0]	auto[0]	29	1			T57	1		T36	4		T210	3
all_values[12]	auto[0]	auto[0]	auto[1]	98	1			T10	4		T21	2		T57	1
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T21	2		T198	1		T210	1
all_values[12]	auto[0]	auto[1]	auto[1]	97	1			T10	6		T57	1		T22	2
all_values[12]	auto[1]	auto[0]	auto[1]	112	1			T21	2		T57	1		T22	3
all_values[12]	auto[1]	auto[1]	auto[1]	90	1			T10	1		T21	1		T22	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T10	1		T21	2		T22	1
all_values[13]	auto[0]	auto[0]	auto[1]	100	1			T10	4		T21	1		T57	3
all_values[13]	auto[0]	auto[1]	auto[0]	34	1			T21	3		T198	2		T207	1
all_values[13]	auto[0]	auto[1]	auto[1]	97	1			T10	1		T22	1		T176	4
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T10	3		T21	1		T22	2
all_values[13]	auto[1]	auto[1]	auto[1]	87	1			T10	2		T57	1		T22	1
all_values[14]	auto[0]	auto[0]	auto[0]	44	1			T21	3		T210	1		T207	1
all_values[14]	auto[0]	auto[0]	auto[1]	105	1			T10	1		T21	2		T57	1
all_values[14]	auto[0]	auto[1]	auto[0]	29	1			T10	2		T176	1		T210	2
all_values[14]	auto[0]	auto[1]	auto[1]	91	1			T10	4		T21	1		T36	8
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T10	2		T21	1		T57	2
all_values[14]	auto[1]	auto[1]	auto[1]	89	1			T10	2		T57	1		T22	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal