Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

128671

1

T11

1

T15

2

T20

366

ack

15387

1

T14

13

T11

35

T15

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	537	1			T25	1		T206	1		T52	7
high	29173	1			T14	3		T11	1		T20	70
med	52382	1			T14	2		T11	2		T15	3
sml	61409	1			T14	8		T11	33		T15	3
all_zero	557	1			T20	1		T23	1		T25	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71908

1

T14

7

T11

17

T15

3

auto[1]

72150

1

T14

6

T11

19

T15

3

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98840

1

T14

13

T11

25

T15

4

auto[1]

45218

1

T11

11

T15

2

T20

111

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134695

1

T14

7

T11

14

T15

4

auto[1]

9363

1

T14

6

T11

22

T15

2

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133041

1

T14

6

T11

23

T15

4

auto[1]

11017

1

T14

7

T11

13

T15

2

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134631

1

T14

7

T11

24

T15

4

auto[1]

9427

1

T14

6

T11

12

T15

2

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71908

1

T14

7

T11

17

T15

3

auto[1]

72150

1

T14

6

T11

19

T15

3

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98840

1

T14

13

T11

25

T15

4

auto[1]

45218

1

T11

11

T15

2

T20

111

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134695

1

T14

7

T11

14

T15

4

auto[1]

9363

1

T14

6

T11

22

T15

2

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133041

1

T14

6

T11

23

T15

4

auto[1]

11017

1

T14

7

T11

13

T15

2

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134631

1

T14

7

T11

24

T15

4

auto[1]

9427

1

T14

6

T11

12

T15

2

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T207

1

T208

1

T166

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T209

1

T210

1

T211

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T212

1

T213

1

T162

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

426

1

T25

3

T61

1

T52

4

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

183

1

T25

2

T52

2

T86

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

206

1

T25

3

T61

1

T52

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

778

1

T20

1

T25

6

T61

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

360

1

T20

1

T25

2

T61

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

390

1

T20

1

T25

4

T61

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

800

1

T25

5

T61

1

T52

11

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

389

1

T20

1

T61

1

T52

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

341

1

T20

2

T25

1

T61

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T214

1

T215

1

T162

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T207

1

T216

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T217

1

T218

1

T219

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	39685	1			T15	1		T20	118		T25	179
write_address_byte	11017	1			T14	7		T11	13		T15	2
read_with_ack	3571	1			T11	11		T15	1		T20	6
read_with_nack	5792	1			T14	6		T11	11		T15	1
stop_byte	9427	1			T14	6		T11	12		T15	2
write_address_byte_nak	6526	1			T15	1		T20	11		T25	63
data_byte_nack	128671	1			T11	1		T15	2		T20	366
stop_byte_nack	6249	1			T11	1		T15	1		T20	10
nakok_byte_nack	64466	1			T15	2		T20	189		T23	1
nakok_addr_byte_nack	3230	1			T15	1		T20	6		T25	35