Group : i2c_env_pkg::i2c_timing_param_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_timing_param_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
75.00 52.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

10 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.t_f_cg 50.00 1 100 1 64 64
i2c_env_pkg.t_r_cg 50.00 1 100 1 64 64
i2c_env_pkg.thd_dat_cg 50.00 1 100 1 64 64
i2c_env_pkg.thd_sta_cg 50.00 1 100 1 64 64
i2c_env_pkg.thigh_cg 50.00 1 100 1 64 64
i2c_env_pkg.tlow_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_dat_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_sta_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_sto_cg 50.00 1 100 1 64 64
i2c_env_pkg.t_buf_cg 75.00 1 100 1 64 64




Group Instance : i2c_env_pkg.t_f_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_f_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.t_f_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.t_r_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_r_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.t_r_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thd_dat_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thd_dat_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thd_dat_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thd_sta_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thd_sta_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thd_sta_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thigh_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thigh_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thigh_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tlow_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tlow_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tlow_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_dat_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_dat_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_dat_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_sta_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_sta_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_sta_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_sto_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_sto_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_sto_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.t_buf_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_buf_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 1 3 75.00


Variables for Group Instance i2c_env_pkg.t_buf_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 1 3 75.00 100 1 1 0


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 10393 1 T1 8 T2 1 T3 1
zero 13 1 T167 1 T159 1 T168 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 10402 1 T1 8 T2 1 T3 1
zero 4 1 T34 1 T36 1 T169 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 14 1 T15 1 T24 1 T170 1
low 11043 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 12 1 T15 1 T24 1 T170 1
low 12157 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 13 1 T15 1 T24 1 T170 1
low 14186 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 13 1 T15 1 T24 1 T170 1
low 14186 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 11051 1 T1 8 T2 1 T3 1
zero 6 1 T167 1 T34 1 T171 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 14 1 T15 1 T24 1 T170 1
low 12155 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 12 1 T15 1 T24 1 T170 1
low 14516 1 T1 8 T2 1 T3 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 14 1 T15 1 T24 1 T170 1
low 13847 1 T1 7 T2 1 T3 1
zero 667 1 T1 1 T14 1 T11 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%