Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36822102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10982904

1

T1

206

T2

292

T3

364

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43478774	1			T1	721		T2	930		T3	885
values[0x0]	2163399	1			T1	72		T2	197		T3	201
values[0x1]	2162833	1			T1	71		T2	224		T3	202

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26840332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20964674

1

T1

398

T2

605

T3

610

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	156027	1			T1	1		T2	2		T7	3
valid_sources[0x01]	227513	1			T1	2		T2	6		T7	2
valid_sources[0x02]	169296	1			T1	6		T2	1		T3	104
valid_sources[0x03]	179901	1			T1	2		T2	10		T7	3
valid_sources[0x04]	243712	1			T1	6		T2	10		T7	1
valid_sources[0x05]	157388	1			T1	5		T2	6		T14	1
valid_sources[0x06]	159495	1			T1	1		T2	3		T14	1
valid_sources[0x07]	158111	1			T1	3		T2	3		T7	3
valid_sources[0x08]	169245	1			T1	3		T2	12		T7	1
valid_sources[0x09]	198204	1			T1	2		T2	2		T7	2
valid_sources[0x0a]	154854	1			T1	3		T2	8		T7	4
valid_sources[0x0b]	190448	1			T1	4		T2	4		T7	3
valid_sources[0x0c]	251326	1			T1	3		T2	2		T7	7
valid_sources[0x0d]	165803	1			T1	6		T2	7		T7	2
valid_sources[0x0e]	189294	1			T1	6		T2	10		T7	7
valid_sources[0x0f]	163535	1			T1	1		T2	3		T7	2
valid_sources[0x10]	236173	1			T1	5		T2	6		T7	1
valid_sources[0x11]	154430	1			T1	3		T2	6		T7	3
valid_sources[0x12]	156063	1			T1	2		T2	8		T3	76
valid_sources[0x13]	159722	1			T1	5		T2	3		T7	2
valid_sources[0x14]	159036	1			T1	2		T2	8		T7	3
valid_sources[0x15]	190573	1			T1	4		T2	1		T7	4
valid_sources[0x16]	171529	1			T2	3		T7	7		T19	19
valid_sources[0x17]	163594	1			T1	2		T2	5		T7	9
valid_sources[0x18]	167662	1			T1	1		T2	6		T14	1
valid_sources[0x19]	167074	1			T1	1		T2	6		T14	1
valid_sources[0x1a]	162351	1			T1	1		T2	4		T7	2
valid_sources[0x1b]	159972	1			T1	4		T2	4		T7	2
valid_sources[0x1c]	243868	1			T1	5		T2	2		T7	2
valid_sources[0x1d]	169447	1			T2	6		T7	3		T19	13
valid_sources[0x1e]	168192	1			T1	1		T7	7		T19	26
valid_sources[0x1f]	194506	1			T1	2		T7	1		T19	38
valid_sources[0x20]	507705	1			T1	3		T2	4		T7	4
valid_sources[0x21]	168119	1			T1	3		T2	5		T7	2
valid_sources[0x22]	479834	1			T1	3		T2	2		T7	6
valid_sources[0x23]	161512	1			T1	4		T2	1		T7	1
valid_sources[0x24]	155544	1			T1	4		T2	10		T3	43
valid_sources[0x25]	159074	1			T1	4		T2	7		T7	6
valid_sources[0x26]	160166	1			T1	5		T2	6		T7	2
valid_sources[0x27]	170529	1			T1	2		T2	13		T7	7
valid_sources[0x28]	177571	1			T1	3		T2	6		T7	7
valid_sources[0x29]	177497	1			T1	4		T2	6		T7	4
valid_sources[0x2a]	166361	1			T1	3		T2	6		T7	2
valid_sources[0x2b]	161690	1			T1	6		T2	6		T7	1
valid_sources[0x2c]	172915	1			T1	3		T2	4		T7	3
valid_sources[0x2d]	166482	1			T1	5		T2	7		T7	2
valid_sources[0x2e]	271577	1			T1	4		T2	16		T7	6
valid_sources[0x2f]	187964	1			T1	2		T2	1		T7	1
valid_sources[0x30]	166798	1			T1	6		T2	5		T7	4
valid_sources[0x31]	172496	1			T1	2		T2	4		T7	5
valid_sources[0x32]	323215	1			T1	8		T2	6		T7	3
valid_sources[0x33]	170216	1			T1	8		T2	4		T3	39
valid_sources[0x34]	156649	1			T1	4		T2	5		T7	5
valid_sources[0x35]	175034	1			T1	4		T2	6		T3	72
valid_sources[0x36]	177827	1			T1	2		T2	4		T7	2
valid_sources[0x37]	183745	1			T1	3		T2	4		T7	3
valid_sources[0x38]	178538	1			T1	5		T2	4		T14	4754
valid_sources[0x39]	156503	1			T1	2		T2	2		T7	1
valid_sources[0x3a]	160249	1			T1	7		T2	7		T3	200
valid_sources[0x3b]	167433	1			T1	4		T7	2		T19	22
valid_sources[0x3c]	156541	1			T1	3		T2	7		T7	4
valid_sources[0x3d]	172523	1			T1	1		T2	4		T7	5
valid_sources[0x3e]	169189	1			T1	4		T2	13		T14	1
valid_sources[0x3f]	165610	1			T1	4		T2	4		T7	4
valid_sources[0x40]	171315	1			T1	1		T2	5		T7	2
valid_sources[0x41]	181328	1			T1	3		T7	5		T19	20
valid_sources[0x42]	159919	1			T1	4		T2	6		T7	4
valid_sources[0x43]	165353	1			T1	2		T2	1		T7	4
valid_sources[0x44]	159195	1			T1	1		T2	4		T14	1
valid_sources[0x45]	160441	1			T1	5		T2	1		T7	1
valid_sources[0x46]	158004	1			T1	4		T2	4		T7	4
valid_sources[0x47]	223596	1			T1	6		T2	9		T7	4
valid_sources[0x48]	157239	1			T1	2		T2	7		T14	1
valid_sources[0x49]	190808	1			T1	6		T2	5		T7	1
valid_sources[0x4a]	179506	1			T1	2		T2	6		T7	4
valid_sources[0x4b]	199668	1			T1	3		T7	4		T19	14
valid_sources[0x4c]	158280	1			T1	2		T2	7		T3	82
valid_sources[0x4d]	163204	1			T1	3		T2	7		T7	4
valid_sources[0x4e]	163645	1			T1	4		T2	9		T7	3
valid_sources[0x4f]	176377	1			T1	1		T2	3		T7	4
valid_sources[0x50]	186164	1			T1	5		T2	11		T7	2
valid_sources[0x51]	157912	1			T1	2		T2	3		T19	21
valid_sources[0x52]	158064	1			T1	3		T2	9		T7	3
valid_sources[0x53]	158872	1			T1	5		T2	4		T7	3
valid_sources[0x54]	177179	1			T1	7		T2	8		T7	5
valid_sources[0x55]	252975	1			T1	2		T2	6		T7	3
valid_sources[0x56]	186606	1			T1	3		T2	13		T7	3
valid_sources[0x57]	248853	1			T1	3		T2	4		T7	1
valid_sources[0x58]	336744	1			T1	2		T14	129		T7	5
valid_sources[0x59]	163246	1			T1	9		T2	5		T7	1
valid_sources[0x5a]	185020	1			T1	2		T2	5		T19	28
valid_sources[0x5b]	224280	1			T1	3		T2	1		T3	112
valid_sources[0x5c]	183505	1			T1	3		T2	7		T7	3
valid_sources[0x5d]	165147	1			T1	4		T2	5		T7	4
valid_sources[0x5e]	176962	1			T1	2		T2	7		T14	3754
valid_sources[0x5f]	165204	1			T1	2		T3	8		T7	8
valid_sources[0x60]	165206	1			T1	9		T2	4		T7	2
valid_sources[0x61]	484590	1			T1	5		T2	10		T7	4
valid_sources[0x62]	170808	1			T1	2		T2	8		T7	4
valid_sources[0x63]	157148	1			T1	3		T2	2		T3	1
valid_sources[0x64]	157724	1			T1	4		T2	7		T7	5
valid_sources[0x65]	174041	1			T1	6		T2	2		T7	4
valid_sources[0x66]	159008	1			T1	1		T2	2		T7	3
valid_sources[0x67]	161512	1			T1	6		T2	9		T7	4
valid_sources[0x68]	160821	1			T1	7		T2	2		T7	2
valid_sources[0x69]	228009	1			T1	2		T2	7		T7	2
valid_sources[0x6a]	156645	1			T1	2		T2	3		T7	4
valid_sources[0x6b]	156498	1			T1	3		T2	1		T7	4
valid_sources[0x6c]	160776	1			T1	5		T2	7		T7	6
valid_sources[0x6d]	168963	1			T1	3		T2	3		T7	4
valid_sources[0x6e]	163432	1			T2	15		T14	1		T7	2
valid_sources[0x6f]	160722	1			T1	6		T2	3		T7	4
valid_sources[0x70]	183480	1			T1	3		T2	3		T7	4
valid_sources[0x71]	173860	1			T1	2		T2	7		T7	8
valid_sources[0x72]	158207	1			T1	3		T7	6		T19	25
valid_sources[0x73]	164936	1			T1	1		T2	9		T7	3
valid_sources[0x74]	166051	1			T1	8		T2	9		T7	4
valid_sources[0x75]	179362	1			T1	5		T2	4		T14	2
valid_sources[0x76]	163922	1			T1	1		T2	8		T7	3
valid_sources[0x77]	154533	1			T1	4		T2	2		T7	3
valid_sources[0x78]	162031	1			T1	2		T2	3		T7	4
valid_sources[0x79]	159639	1			T1	3		T2	5		T7	6
valid_sources[0x7a]	160555	1			T1	7		T2	8		T7	4
valid_sources[0x7b]	217808	1			T1	2		T2	4		T7	3
valid_sources[0x7c]	162644	1			T1	3		T2	10		T7	1
valid_sources[0x7d]	160065	1			T1	1		T2	2		T7	2
valid_sources[0x7e]	157134	1			T1	3		T2	4		T7	2
valid_sources[0x7f]	177371	1			T1	1		T2	8		T7	2
valid_sources[0x80]	158393	1			T1	2		T2	10		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9255896

1

T1

115

T2

151

T3

215

values[0x0]

all_enables

biggest_size

1096569

1

T1

51

T2

79

T3

93

values[0x1]

all_enables

biggest_size

630439

1

T1

40

T2

62

T3

56