Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	4	56	93.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	4	56	93.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6457093	1			T1	3		T2	1		T3	7509
all_values[1]	6457093	1			T1	3		T2	1		T3	7509
all_values[2]	6457093	1			T1	3		T2	1		T3	7509
all_values[3]	6457093	1			T1	3		T2	1		T3	7509
all_values[4]	6457093	1			T1	3		T2	1		T3	7509
all_values[5]	6457093	1			T1	3		T2	1		T3	7509
all_values[6]	6457093	1			T1	3		T2	1		T3	7509
all_values[7]	6457093	1			T1	3		T2	1		T3	7509
all_values[8]	6457093	1			T1	3		T2	1		T3	7509
all_values[9]	6457093	1			T1	3		T2	1		T3	7509
all_values[10]	6457093	1			T1	3		T2	1		T3	7509
all_values[11]	6457093	1			T1	3		T2	1		T3	7509
all_values[12]	6457093	1			T1	3		T2	1		T3	7509
all_values[13]	6457093	1			T1	3		T2	1		T3	7509
all_values[14]	6457093	1			T1	3		T2	1		T3	7509

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82635395

1

T1

44

T2

15

T3

95182

auto[1]

14221000

1

T1

1

T3

17453

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85952643

1

T1

45

T2

15

T3

112635

auto[1]

10903752

1

T14

619664

T15

86811

T27

346619

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1195840	1			T1	3		T2	1		T3	6
all_values[0]	auto[0]	auto[1]	113404	1			T14	863		T15	574		T27	1514
all_values[0]	auto[1]	auto[0]	4531386	1			T3	7503		T6	2		T7	2
all_values[0]	auto[1]	auto[1]	616463	1			T14	43398		T15	5211		T27	21590
all_values[1]	auto[0]	auto[0]	5725121	1			T1	3		T2	1		T3	7509
all_values[1]	auto[0]	auto[1]	729644	1			T14	44235		T15	5785		T27	23084
all_values[1]	auto[1]	auto[0]	2121	1			T11	3		T28	93		T62	3
all_values[1]	auto[1]	auto[1]	207	1			T14	26		T15	3		T27	23
all_values[2]	auto[0]	auto[0]	5727231	1			T1	3		T2	1		T3	7509
all_values[2]	auto[0]	auto[1]	729696	1			T14	44257		T15	5783		T27	23106
all_values[2]	auto[1]	auto[0]	1	1			T181	1		-	-		-	-
all_values[2]	auto[1]	auto[1]	165	1			T14	4		T15	5		T27	3
all_values[3]	auto[0]	auto[0]	5727229	1			T1	3		T2	1		T3	7509
all_values[3]	auto[0]	auto[1]	729694	1			T14	44254		T15	5786		T27	23103
all_values[3]	auto[1]	auto[1]	170	1			T14	6		T27	6		T177	4
all_values[4]	auto[0]	auto[0]	5727193	1			T1	3		T2	1		T3	7509
all_values[4]	auto[0]	auto[1]	729691	1			T14	44254		T15	5785		T27	23102
all_values[4]	auto[1]	auto[0]	51	1			T38	48		T35	3		-	-
all_values[4]	auto[1]	auto[1]	158	1			T14	8		T15	1		T27	7
all_values[5]	auto[0]	auto[0]	5725476	1			T1	3		T2	1		T3	7509
all_values[5]	auto[0]	auto[1]	729702	1			T14	44256		T15	5786		T27	23104
all_values[5]	auto[1]	auto[0]	1754	1			T34	1662		T35	92		-	-
all_values[5]	auto[1]	auto[1]	161	1			T14	6		T27	5		T177	4
all_values[6]	auto[0]	auto[0]	5053662	1			T1	2		T2	1		T3	7485
all_values[6]	auto[0]	auto[1]	679712	1			T14	36693		T15	5754		T27	17680
all_values[6]	auto[1]	auto[0]	673547	1			T1	1		T3	24		T16	1
all_values[6]	auto[1]	auto[1]	50172	1			T14	7567		T15	33		T27	5429
all_values[7]	auto[0]	auto[0]	5444621	1			T1	3		T2	1		T3	5552
all_values[7]	auto[0]	auto[1]	710443	1			T14	41027		T15	5195		T27	17794
all_values[7]	auto[1]	auto[0]	282586	1			T3	1957		T16	1		T11	2291
all_values[7]	auto[1]	auto[1]	19443	1			T14	3235		T15	593		T27	5313
all_values[8]	auto[0]	auto[0]	4929584	1			T1	3		T2	1		T3	7064
all_values[8]	auto[0]	auto[1]	636809	1			T14	2		T15	5512		T27	16606
all_values[8]	auto[1]	auto[0]	841892	1			T3	445		T16	1		T11	3427
all_values[8]	auto[1]	auto[1]	48808	1			T14	4		T15	276		T27	6499
all_values[9]	auto[0]	auto[0]	5081530	1			T1	3		T2	1		T3	7488
all_values[9]	auto[0]	auto[1]	678089	1			T14	36765		T15	5766		T27	17759
all_values[9]	auto[1]	auto[0]	645689	1			T3	21		T8	1		T21	1
all_values[9]	auto[1]	auto[1]	51785	1			T14	7496		T15	23		T27	5350
all_values[10]	auto[0]	auto[0]	5727255	1			T1	3		T2	1		T3	7509
all_values[10]	auto[0]	auto[1]	729696	1			T14	44258		T15	5782		T27	23106
all_values[10]	auto[1]	auto[1]	142	1			T14	3		T15	5		T27	3
all_values[11]	auto[0]	auto[0]	2947	1			T1	3		T2	1		T3	6
all_values[11]	auto[0]	auto[1]	357	1			T14	25		T15	15		T27	25
all_values[11]	auto[1]	auto[0]	5724281	1			T3	7503		T6	2		T7	2
all_values[11]	auto[1]	auto[1]	729508	1			T14	44236		T15	5774		T27	23083
all_values[12]	auto[0]	auto[0]	5727212	1			T1	3		T2	1		T3	7509
all_values[12]	auto[0]	auto[1]	729722	1			T14	44259		T15	5784		T27	23105
all_values[12]	auto[1]	auto[1]	159	1			T14	3		T15	5		T27	3
all_values[13]	auto[0]	auto[0]	5727206	1			T1	3		T2	1		T3	7509
all_values[13]	auto[0]	auto[1]	729698	1			T14	44256		T15	5780		T27	23106
all_values[13]	auto[1]	auto[0]	10	1			T193	1		T194	1		T205	1
all_values[13]	auto[1]	auto[1]	179	1			T14	6		T15	7		T27	2
all_values[14]	auto[0]	auto[0]	5727218	1			T1	3		T2	1		T3	7509
all_values[14]	auto[0]	auto[1]	729713	1			T14	44254		T15	5783		T27	23107
all_values[14]	auto[1]	auto[1]	162	1			T14	8		T15	5		T27	2