Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6457093	1			T1	3		T2	1		T3	7509
all_pins[1]	6457093	1			T1	3		T2	1		T3	7509
all_pins[2]	6457093	1			T1	3		T2	1		T3	7509
all_pins[3]	6457093	1			T1	3		T2	1		T3	7509
all_pins[4]	6457093	1			T1	3		T2	1		T3	7509
all_pins[5]	6457093	1			T1	3		T2	1		T3	7509
all_pins[6]	6457093	1			T1	3		T2	1		T3	7509
all_pins[7]	6457093	1			T1	3		T2	1		T3	7509
all_pins[8]	6457093	1			T1	3		T2	1		T3	7509
all_pins[9]	6457093	1			T1	3		T2	1		T3	7509
all_pins[10]	6457093	1			T1	3		T2	1		T3	7509
all_pins[11]	6457093	1			T1	3		T2	1		T3	7509
all_pins[12]	6457093	1			T1	3		T2	1		T3	7509
all_pins[13]	6457093	1			T1	3		T2	1		T3	7509
all_pins[14]	6457093	1			T1	3		T2	1		T3	7509

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	82578084	1			T1	44		T2	15		T3	95055
values[0x1]	14278311	1			T1	1		T3	17580		T6	4
transitions[0x0=>0x1]	13504114	1			T1	1		T3	17547		T6	4
transitions[0x1=>0x0]	13502985	1			T1	1		T3	17546		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1309387	1			T1	3		T2	1		T3	6
all_pins[0]	values[0x1]	5147706	1			T3	7503		T6	2		T7	2
all_pins[0]	transitions[0x0=>0x1]	5145151	1			T3	7503		T6	2		T7	2
all_pins[0]	transitions[0x1=>0x0]	67	1			T15	1		T177	2		T219	2
all_pins[1]	values[0x0]	6454471	1			T1	3		T2	1		T3	7509
all_pins[1]	values[0x1]	2622	1			T11	3		T14	25		T28	101
all_pins[1]	transitions[0x0=>0x1]	2596	1			T11	3		T14	24		T28	101
all_pins[1]	transitions[0x1=>0x0]	70	1			T27	1		T177	3		T219	1
all_pins[2]	values[0x0]	6456997	1			T1	3		T2	1		T3	7509
all_pins[2]	values[0x1]	96	1			T14	1		T27	1		T177	3
all_pins[2]	transitions[0x0=>0x1]	71	1			T14	1		T177	1		T219	1
all_pins[2]	transitions[0x1=>0x0]	64	1			T14	3		T27	2		T177	2
all_pins[3]	values[0x0]	6457004	1			T1	3		T2	1		T3	7509
all_pins[3]	values[0x1]	89	1			T14	3		T27	3		T177	4
all_pins[3]	transitions[0x0=>0x1]	78	1			T14	3		T27	2		T177	4
all_pins[3]	transitions[0x1=>0x0]	115	1			T14	3		T27	2		T177	2
all_pins[4]	values[0x0]	6456967	1			T1	3		T2	1		T3	7509
all_pins[4]	values[0x1]	126	1			T14	3		T27	3		T177	2
all_pins[4]	transitions[0x0=>0x1]	109	1			T14	2		T27	3		T177	2
all_pins[4]	transitions[0x1=>0x0]	1920	1			T14	2		T177	1		T219	2
all_pins[5]	values[0x0]	6455156	1			T1	3		T2	1		T3	7509
all_pins[5]	values[0x1]	1937	1			T14	3		T177	1		T219	2
all_pins[5]	transitions[0x0=>0x1]	1666	1			T14	3		T219	2		T34	1545
all_pins[5]	transitions[0x1=>0x0]	726372	1			T1	1		T3	28		T16	1
all_pins[6]	values[0x0]	5730450	1			T1	2		T2	1		T3	7481
all_pins[6]	values[0x1]	726643	1			T1	1		T3	28		T16	1
all_pins[6]	transitions[0x0=>0x1]	708234	1			T1	1		T3	23		T11	605
all_pins[6]	transitions[0x1=>0x0]	315974	1			T3	2044		T11	2605		T12	35
all_pins[7]	values[0x0]	6122710	1			T1	3		T2	1		T3	5460
all_pins[7]	values[0x1]	334383	1			T3	2049		T16	1		T11	2630
all_pins[7]	transitions[0x0=>0x1]	271542	1			T3	2021		T11	2057		T14	3129
all_pins[7]	transitions[0x1=>0x0]	849610	1			T3	447		T11	3404		T12	4923
all_pins[8]	values[0x0]	5544642	1			T1	3		T2	1		T3	7034
all_pins[8]	values[0x1]	912451	1			T3	475		T16	1		T11	3977
all_pins[8]	transitions[0x0=>0x1]	222521	1			T3	475		T11	3977		T12	682
all_pins[8]	transitions[0x1=>0x0]	8302	1			T3	22		T8	1		T21	1
all_pins[9]	values[0x0]	5758861	1			T1	3		T2	1		T3	7487
all_pins[9]	values[0x1]	698232	1			T3	22		T8	1		T21	1
all_pins[9]	transitions[0x0=>0x1]	698215	1			T3	22		T8	1		T21	1
all_pins[9]	transitions[0x1=>0x0]	49	1			T15	2		T177	1		T219	1
all_pins[10]	values[0x0]	6457027	1			T1	3		T2	1		T3	7509
all_pins[10]	values[0x1]	66	1			T14	1		T15	2		T177	1
all_pins[10]	transitions[0x0=>0x1]	52	1			T15	2		T177	1		T144	1
all_pins[10]	transitions[0x1=>0x0]	6453694	1			T3	7503		T6	2		T7	2
all_pins[11]	values[0x0]	3385	1			T1	3		T2	1		T3	6
all_pins[11]	values[0x1]	6453708	1			T3	7503		T6	2		T7	2
all_pins[11]	transitions[0x0=>0x1]	6453688	1			T3	7503		T6	2		T7	2
all_pins[11]	transitions[0x1=>0x0]	63	1			T15	1		T177	1		T219	1
all_pins[12]	values[0x0]	6457010	1			T1	3		T2	1		T3	7509
all_pins[12]	values[0x1]	83	1			T14	1		T15	1		T27	1
all_pins[12]	transitions[0x0=>0x1]	59	1			T27	1		T177	1		T219	2
all_pins[12]	transitions[0x1=>0x0]	72	1			T14	3		T15	1		T193	1
all_pins[13]	values[0x0]	6456997	1			T1	3		T2	1		T3	7509
all_pins[13]	values[0x1]	96	1			T14	4		T15	2		T193	1
all_pins[13]	transitions[0x0=>0x1]	79	1			T15	2		T193	1		T27	1
all_pins[13]	transitions[0x1=>0x0]	56	1			T14	4		T177	1		T144	2
all_pins[14]	values[0x0]	6457020	1			T1	3		T2	1		T3	7509
all_pins[14]	values[0x1]	73	1			T14	8		T177	1		T144	3
all_pins[14]	transitions[0x0=>0x1]	53	1			T14	6		T177	1		T144	3
all_pins[14]	transitions[0x1=>0x0]	5146557	1			T3	7502		T6	1		T7	1