Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368	1			T14	8		T15	11		T27	7
all_values[1]	368	1			T14	8		T15	11		T27	7
all_values[2]	368	1			T14	8		T15	11		T27	7
all_values[3]	368	1			T14	8		T15	11		T27	7
all_values[4]	368	1			T14	8		T15	11		T27	7
all_values[5]	368	1			T14	8		T15	11		T27	7
all_values[6]	368	1			T14	8		T15	11		T27	7
all_values[7]	368	1			T14	8		T15	11		T27	7
all_values[8]	368	1			T14	8		T15	11		T27	7
all_values[9]	368	1			T14	8		T15	11		T27	7
all_values[10]	368	1			T14	8		T15	11		T27	7
all_values[11]	368	1			T14	8		T15	11		T27	7
all_values[12]	368	1			T14	8		T15	11		T27	7
all_values[13]	368	1			T14	8		T15	11		T27	7
all_values[14]	368	1			T14	8		T15	11		T27	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3002

1

T14

55

T15

110

T27

71

auto[1]

2518

1

T14

65

T15

55

T27

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

942

1

T14

14

T15

24

T27

16

auto[1]

4578

1

T14

106

T15

141

T27

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3229

1

T14

62

T15

107

T27

57

auto[1]

2291

1

T14

58

T15

58

T27

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1			T15	3		T27	2		T219	2
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T15	3		T177	1		T219	1
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T14	1		T15	1		T27	3
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T14	4		T15	1		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	87	1			T14	1		T15	2		T177	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1			T14	2		T15	1		T27	1
all_values[1]	auto[0]	auto[0]	auto[0]	48	1			T15	1		T27	1		T37	1
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T14	3		T15	5		T27	2
all_values[1]	auto[0]	auto[1]	auto[0]	29	1			T14	1		T27	1		T144	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T14	1		T15	2		T177	1
all_values[1]	auto[1]	auto[0]	auto[1]	84	1			T14	3		T15	2		T27	2
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T15	1		T27	1		T177	3
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T15	1		T37	1		T145	1
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T14	1		T15	4		T27	3
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T14	1		T144	1		T37	1
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T14	2		T15	1		T27	1
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T14	3		T15	2		T27	3
all_values[2]	auto[1]	auto[1]	auto[1]	82	1			T14	1		T15	3		T177	3
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T14	1		T15	2		T177	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T14	1		T15	4		T27	1
all_values[3]	auto[0]	auto[1]	auto[0]	28	1			T14	1		T15	1		T144	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T14	1		T15	3		T27	2
all_values[3]	auto[1]	auto[0]	auto[1]	74	1			T14	4		T15	1		T27	3
all_values[3]	auto[1]	auto[1]	auto[1]	67	1			T27	1		T177	4		T219	1
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T15	3		T177	1		T189	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T14	1		T15	4		T27	3
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T177	1		T144	1		T37	1
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T14	1		T15	1		T177	2
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T14	5		T15	2		T27	4
all_values[4]	auto[1]	auto[1]	auto[1]	50	1			T14	1		T15	1		T177	1
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T15	1		T220	1		T146	1
all_values[5]	auto[0]	auto[0]	auto[1]	81	1			T14	2		T15	3		T27	2
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T15	2		T177	1		T144	3
all_values[5]	auto[0]	auto[1]	auto[1]	65	1			T14	1		T15	3		T27	1
all_values[5]	auto[1]	auto[0]	auto[1]	86	1			T14	3		T15	1		T27	3
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T14	2		T15	1		T27	1
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T14	1		T15	1		T145	3
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T14	2		T15	3		T27	1
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T14	1		T15	1		T144	1
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T14	1		T15	3		T177	3
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T14	3		T15	2		T27	5
all_values[6]	auto[1]	auto[1]	auto[1]	65	1			T15	1		T27	1		T177	2
all_values[7]	auto[0]	auto[0]	auto[0]	27	1			T15	1		T27	2		T177	2
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T14	2		T15	2		T144	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T219	1		T221	1		T222	2
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T14	2		T15	2		T27	2
all_values[7]	auto[1]	auto[0]	auto[1]	99	1			T14	2		T15	4		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	71	1			T14	2		T15	2		T27	2
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T14	2		T15	1		T27	2
all_values[8]	auto[0]	auto[0]	auto[1]	89	1			T14	2		T15	3		T177	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T14	2		T27	2		T144	2
all_values[8]	auto[0]	auto[1]	auto[1]	67	1			T14	1		T15	2		T27	2
all_values[8]	auto[1]	auto[0]	auto[1]	86	1			T14	1		T15	3		T27	1
all_values[8]	auto[1]	auto[1]	auto[1]	63	1			T15	2		T144	1		T189	1
all_values[9]	auto[0]	auto[0]	auto[0]	38	1			T189	1		T145	1		T220	1
all_values[9]	auto[0]	auto[0]	auto[1]	87	1			T14	2		T15	6		T27	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T14	1		T144	1		T189	3
all_values[9]	auto[0]	auto[1]	auto[1]	72	1			T14	2		T15	2		T177	1
all_values[9]	auto[1]	auto[0]	auto[1]	87	1			T15	3		T27	4		T219	1
all_values[9]	auto[1]	auto[1]	auto[1]	65	1			T14	3		T27	2		T177	4
all_values[10]	auto[0]	auto[0]	auto[0]	44	1			T15	1		T189	1		T146	3
all_values[10]	auto[0]	auto[0]	auto[1]	77	1			T14	1		T15	1		T27	4
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T14	1		T15	1		T177	2
all_values[10]	auto[0]	auto[1]	auto[1]	74	1			T14	3		T15	3		T177	2
all_values[10]	auto[1]	auto[0]	auto[1]	77	1			T14	2		T15	4		T27	3
all_values[10]	auto[1]	auto[1]	auto[1]	65	1			T14	1		T15	1		T177	1
all_values[11]	auto[0]	auto[0]	auto[0]	31	1			T27	1		T221	1		T223	1
all_values[11]	auto[0]	auto[0]	auto[1]	74	1			T15	3		T27	2		T177	1
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T14	1		T219	1		T145	1
all_values[11]	auto[0]	auto[1]	auto[1]	78	1			T14	2		T15	3		T27	3
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T14	1		T15	3		T177	1
all_values[11]	auto[1]	auto[1]	auto[1]	75	1			T14	4		T15	2		T27	1
all_values[12]	auto[0]	auto[0]	auto[0]	29	1			T27	1		T145	1		T221	1
all_values[12]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T15	3		T27	2
all_values[12]	auto[0]	auto[1]	auto[0]	21	1			T221	1		T220	1		T224	1
all_values[12]	auto[0]	auto[1]	auto[1]	83	1			T14	4		T15	3		T27	1
all_values[12]	auto[1]	auto[0]	auto[1]	81	1			T14	2		T15	5		T27	2
all_values[12]	auto[1]	auto[1]	auto[1]	78	1			T14	1		T27	1		T219	2
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T15	2		T27	1		T189	1
all_values[13]	auto[0]	auto[0]	auto[1]	78	1			T14	2		T15	3		T27	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1			T177	1		T221	1		T225	2
all_values[13]	auto[0]	auto[1]	auto[1]	83	1			T14	1		T15	1		T27	2
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T15	3		T27	3		T219	2
all_values[13]	auto[1]	auto[1]	auto[1]	63	1			T14	5		T15	2		T177	1
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T15	1		T177	1		T189	1
all_values[14]	auto[0]	auto[0]	auto[1]	83	1			T15	6		T27	2		T177	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T177	2		T144	2		T37	3
all_values[14]	auto[0]	auto[1]	auto[1]	74	1			T14	2		T27	2		T177	2
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T14	1		T15	2		T27	3
all_values[14]	auto[1]	auto[1]	auto[1]	62	1			T14	5		T15	2		T177	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal