| T1305 |
/workspace/coverage/default/41.i2c_target_stress_wr.3821103941 |
|
|
Mar 03 02:58:47 PM PST 24 |
Mar 03 03:12:34 PM PST 24 |
28706603607 ps |
| T1306 |
/workspace/coverage/default/0.i2c_alert_test.2372635490 |
|
|
Mar 03 02:51:15 PM PST 24 |
Mar 03 02:51:16 PM PST 24 |
122497354 ps |
| T1307 |
/workspace/coverage/default/10.i2c_target_fifo_reset_acq.1809013161 |
|
|
Mar 03 02:52:18 PM PST 24 |
Mar 03 02:53:14 PM PST 24 |
10142218983 ps |
| T1308 |
/workspace/coverage/default/34.i2c_host_fifo_full.1933397852 |
|
|
Mar 03 02:57:05 PM PST 24 |
Mar 03 02:58:24 PM PST 24 |
8940441235 ps |
| T1309 |
/workspace/coverage/default/14.i2c_host_fifo_reset_rx.3674970843 |
|
|
Mar 03 02:52:45 PM PST 24 |
Mar 03 02:52:51 PM PST 24 |
2041065302 ps |
| T1310 |
/workspace/coverage/default/17.i2c_host_fifo_watermark.3886626398 |
|
|
Mar 03 02:53:24 PM PST 24 |
Mar 03 02:57:55 PM PST 24 |
21071931139 ps |
| T1311 |
/workspace/coverage/default/1.i2c_host_rx_oversample.1212585581 |
|
|
Mar 03 02:51:09 PM PST 24 |
Mar 03 02:53:44 PM PST 24 |
1900041068 ps |
| T1312 |
/workspace/coverage/default/25.i2c_host_fifo_overflow.3309350051 |
|
|
Mar 03 02:54:58 PM PST 24 |
Mar 03 02:58:19 PM PST 24 |
2425071661 ps |
| T1313 |
/workspace/coverage/default/34.i2c_alert_test.2992078188 |
|
|
Mar 03 02:57:20 PM PST 24 |
Mar 03 02:57:21 PM PST 24 |
47305147 ps |
| T1314 |
/workspace/coverage/default/1.i2c_host_fifo_overflow.339683414 |
|
|
Mar 03 02:51:13 PM PST 24 |
Mar 03 02:52:50 PM PST 24 |
11610190737 ps |
| T1315 |
/workspace/coverage/default/27.i2c_target_bad_addr.3825132458 |
|
|
Mar 03 02:55:37 PM PST 24 |
Mar 03 02:55:42 PM PST 24 |
1189669789 ps |
| T1316 |
/workspace/coverage/default/40.i2c_target_timeout.1260583418 |
|
|
Mar 03 02:58:37 PM PST 24 |
Mar 03 02:58:45 PM PST 24 |
8077262097 ps |
| T1317 |
/workspace/coverage/default/35.i2c_target_fifo_reset_acq.2043600703 |
|
|
Mar 03 02:57:26 PM PST 24 |
Mar 03 02:57:39 PM PST 24 |
10460524144 ps |
| T1318 |
/workspace/coverage/default/41.i2c_host_fifo_full.1546051436 |
|
|
Mar 03 02:58:46 PM PST 24 |
Mar 03 03:00:17 PM PST 24 |
16129556438 ps |
| T1319 |
/workspace/coverage/default/46.i2c_target_hrst.2976434058 |
|
|
Mar 03 03:00:12 PM PST 24 |
Mar 03 03:00:15 PM PST 24 |
471601178 ps |
| T1320 |
/workspace/coverage/default/13.i2c_target_stress_wr.1252960518 |
|
|
Mar 03 02:52:40 PM PST 24 |
Mar 03 03:00:07 PM PST 24 |
38162799288 ps |
| T1321 |
/workspace/coverage/default/3.i2c_target_hrst.789713840 |
|
|
Mar 03 02:51:31 PM PST 24 |
Mar 03 02:51:34 PM PST 24 |
2177370168 ps |
| T1322 |
/workspace/coverage/default/29.i2c_target_bad_addr.910742361 |
|
|
Mar 03 02:55:59 PM PST 24 |
Mar 03 02:56:04 PM PST 24 |
1020705654 ps |
| T1323 |
/workspace/coverage/default/15.i2c_host_fifo_watermark.220263857 |
|
|
Mar 03 02:53:00 PM PST 24 |
Mar 03 03:00:27 PM PST 24 |
19622935701 ps |
| T1324 |
/workspace/coverage/default/31.i2c_host_smoke.10612582 |
|
|
Mar 03 02:56:17 PM PST 24 |
Mar 03 02:57:50 PM PST 24 |
1589353739 ps |
| T1325 |
/workspace/coverage/default/35.i2c_host_error_intr.2816775649 |
|
|
Mar 03 02:57:31 PM PST 24 |
Mar 03 02:57:33 PM PST 24 |
568653639 ps |
| T1326 |
/workspace/coverage/default/23.i2c_alert_test.1130245240 |
|
|
Mar 03 02:54:48 PM PST 24 |
Mar 03 02:54:49 PM PST 24 |
23386160 ps |
| T1327 |
/workspace/coverage/default/23.i2c_target_hrst.3332732630 |
|
|
Mar 03 02:54:42 PM PST 24 |
Mar 03 02:54:44 PM PST 24 |
2832425714 ps |
| T1328 |
/workspace/coverage/default/45.i2c_target_intr_smoke.1498067759 |
|
|
Mar 03 02:59:49 PM PST 24 |
Mar 03 02:59:57 PM PST 24 |
3487740146 ps |
| T1329 |
/workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3631746313 |
|
|
Mar 03 02:53:23 PM PST 24 |
Mar 03 02:53:24 PM PST 24 |
281707529 ps |
| T1330 |
/workspace/coverage/default/5.i2c_host_override.3686002732 |
|
|
Mar 03 02:51:34 PM PST 24 |
Mar 03 02:51:34 PM PST 24 |
20345164 ps |
| T1331 |
/workspace/coverage/default/14.i2c_host_override.3252439577 |
|
|
Mar 03 02:52:43 PM PST 24 |
Mar 03 02:52:44 PM PST 24 |
43643183 ps |
| T1332 |
/workspace/coverage/default/40.i2c_target_fifo_reset_tx.2499621025 |
|
|
Mar 03 02:58:37 PM PST 24 |
Mar 03 02:58:46 PM PST 24 |
10933872071 ps |
| T1333 |
/workspace/coverage/default/12.i2c_target_intr_smoke.3628029739 |
|
|
Mar 03 02:52:31 PM PST 24 |
Mar 03 02:52:36 PM PST 24 |
3072984483 ps |
| T1334 |
/workspace/coverage/default/38.i2c_target_unexp_stop.2980771711 |
|
|
Mar 03 02:58:10 PM PST 24 |
Mar 03 02:58:17 PM PST 24 |
1189890890 ps |
| T1335 |
/workspace/coverage/default/42.i2c_host_stretch_timeout.3042962632 |
|
|
Mar 03 02:59:06 PM PST 24 |
Mar 03 02:59:16 PM PST 24 |
1023504489 ps |
| T1336 |
/workspace/coverage/default/27.i2c_host_error_intr.2704683458 |
|
|
Mar 03 02:55:35 PM PST 24 |
Mar 03 02:55:38 PM PST 24 |
334185512 ps |
| T1337 |
/workspace/coverage/default/46.i2c_target_stretch.476761561 |
|
|
Mar 03 03:00:06 PM PST 24 |
Mar 03 03:11:30 PM PST 24 |
37056419298 ps |
| T1338 |
/workspace/coverage/default/20.i2c_host_fifo_full.522573889 |
|
|
Mar 03 02:53:57 PM PST 24 |
Mar 03 02:55:23 PM PST 24 |
3113753570 ps |
| T1339 |
/workspace/coverage/default/42.i2c_target_intr_smoke.1878881102 |
|
|
Mar 03 02:59:05 PM PST 24 |
Mar 03 02:59:09 PM PST 24 |
3479123708 ps |
| T1340 |
/workspace/coverage/default/7.i2c_host_perf.982311901 |
|
|
Mar 03 02:51:49 PM PST 24 |
Mar 03 03:03:47 PM PST 24 |
52320771520 ps |
| T1341 |
/workspace/coverage/default/39.i2c_host_rx_oversample.3146917468 |
|
|
Mar 03 02:58:18 PM PST 24 |
Mar 03 03:00:06 PM PST 24 |
4571546220 ps |
| T1342 |
/workspace/coverage/default/48.i2c_target_fifo_reset_tx.122675246 |
|
|
Mar 03 03:00:38 PM PST 24 |
Mar 03 03:00:51 PM PST 24 |
10195479185 ps |
| T1343 |
/workspace/coverage/default/42.i2c_target_perf.785826485 |
|
|
Mar 03 02:59:10 PM PST 24 |
Mar 03 02:59:13 PM PST 24 |
909980779 ps |
| T1344 |
/workspace/coverage/default/41.i2c_host_perf.460339579 |
|
|
Mar 03 02:58:48 PM PST 24 |
Mar 03 03:00:18 PM PST 24 |
8136693920 ps |
| T1345 |
/workspace/coverage/default/1.i2c_host_fifo_reset_rx.34913922 |
|
|
Mar 03 02:51:14 PM PST 24 |
Mar 03 02:51:25 PM PST 24 |
856377681 ps |
| T1346 |
/workspace/coverage/default/22.i2c_target_fifo_reset_tx.3202551665 |
|
|
Mar 03 02:54:31 PM PST 24 |
Mar 03 02:55:01 PM PST 24 |
10233014359 ps |
| T1347 |
/workspace/coverage/default/38.i2c_host_stretch_timeout.1591220883 |
|
|
Mar 03 02:58:06 PM PST 24 |
Mar 03 02:58:15 PM PST 24 |
634722163 ps |
| T1348 |
/workspace/coverage/default/46.i2c_target_bad_addr.762855661 |
|
|
Mar 03 03:00:13 PM PST 24 |
Mar 03 03:00:18 PM PST 24 |
1485666781 ps |
| T1349 |
/workspace/coverage/default/30.i2c_target_intr_smoke.4154487793 |
|
|
Mar 03 02:56:13 PM PST 24 |
Mar 03 02:56:17 PM PST 24 |
1691385868 ps |
| T220 |
/workspace/coverage/default/27.i2c_host_stress_all.2945529174 |
|
|
Mar 03 02:55:35 PM PST 24 |
Mar 03 03:24:14 PM PST 24 |
28557252518 ps |
| T1350 |
/workspace/coverage/default/10.i2c_host_perf.1012843508 |
|
|
Mar 03 02:52:11 PM PST 24 |
Mar 03 03:03:47 PM PST 24 |
49047557386 ps |
| T1351 |
/workspace/coverage/default/43.i2c_alert_test.3549678630 |
|
|
Mar 03 02:59:28 PM PST 24 |
Mar 03 02:59:28 PM PST 24 |
17328364 ps |
| T1352 |
/workspace/coverage/default/7.i2c_host_fifo_full.769907193 |
|
|
Mar 03 02:51:50 PM PST 24 |
Mar 03 02:55:53 PM PST 24 |
12217972119 ps |
| T1353 |
/workspace/coverage/default/7.i2c_target_fifo_reset_acq.3618958414 |
|
|
Mar 03 02:51:51 PM PST 24 |
Mar 03 02:53:13 PM PST 24 |
10146816127 ps |
| T1354 |
/workspace/coverage/default/25.i2c_target_fifo_reset_tx.418472448 |
|
|
Mar 03 02:55:11 PM PST 24 |
Mar 03 02:55:24 PM PST 24 |
10196461900 ps |
| T1355 |
/workspace/coverage/default/2.i2c_target_stress_wr.3930974580 |
|
|
Mar 03 02:51:20 PM PST 24 |
Mar 03 03:03:31 PM PST 24 |
75874056642 ps |
| T1356 |
/workspace/coverage/default/27.i2c_target_fifo_reset_tx.9649067 |
|
|
Mar 03 02:55:35 PM PST 24 |
Mar 03 02:55:50 PM PST 24 |
10305118715 ps |
| T1357 |
/workspace/coverage/default/31.i2c_target_fifo_reset_tx.3636404788 |
|
|
Mar 03 02:56:29 PM PST 24 |
Mar 03 02:56:40 PM PST 24 |
10295043717 ps |
| T1358 |
/workspace/coverage/default/18.i2c_target_stress_wr.1212509149 |
|
|
Mar 03 02:53:41 PM PST 24 |
Mar 03 03:01:05 PM PST 24 |
38465143658 ps |
| T1359 |
/workspace/coverage/default/42.i2c_target_fifo_reset_tx.149581946 |
|
|
Mar 03 02:59:12 PM PST 24 |
Mar 03 02:59:29 PM PST 24 |
10117455428 ps |
| T1360 |
/workspace/coverage/default/2.i2c_target_unexp_stop.2054772588 |
|
|
Mar 03 02:51:22 PM PST 24 |
Mar 03 02:51:30 PM PST 24 |
2256619512 ps |
| T1361 |
/workspace/coverage/default/6.i2c_host_override.180355222 |
|
|
Mar 03 02:51:42 PM PST 24 |
Mar 03 02:51:43 PM PST 24 |
55603802 ps |
| T1362 |
/workspace/coverage/default/7.i2c_target_hrst.3829781047 |
|
|
Mar 03 02:51:51 PM PST 24 |
Mar 03 02:51:54 PM PST 24 |
598076689 ps |
| T1363 |
/workspace/coverage/default/30.i2c_host_mode_toggle.476841783 |
|
|
Mar 03 02:56:18 PM PST 24 |
Mar 03 02:58:06 PM PST 24 |
2031971392 ps |
| T1364 |
/workspace/coverage/default/26.i2c_target_perf.4067772623 |
|
|
Mar 03 02:55:21 PM PST 24 |
Mar 03 02:55:26 PM PST 24 |
2560019717 ps |
| T1365 |
/workspace/coverage/default/0.i2c_host_fifo_full.1505511916 |
|
|
Mar 03 02:51:04 PM PST 24 |
Mar 03 02:51:53 PM PST 24 |
5054543572 ps |
| T1366 |
/workspace/coverage/default/21.i2c_target_stress_all.494564283 |
|
|
Mar 03 02:54:16 PM PST 24 |
Mar 03 02:56:15 PM PST 24 |
23830317920 ps |
| T1367 |
/workspace/coverage/default/40.i2c_host_rx_oversample.4010239628 |
|
|
Mar 03 02:58:32 PM PST 24 |
Mar 03 02:59:26 PM PST 24 |
17810542250 ps |
| T1368 |
/workspace/coverage/default/22.i2c_host_override.2678815502 |
|
|
Mar 03 02:54:18 PM PST 24 |
Mar 03 02:54:20 PM PST 24 |
19309622 ps |
| T1369 |
/workspace/coverage/default/25.i2c_host_rx_oversample.1433711184 |
|
|
Mar 03 02:54:58 PM PST 24 |
Mar 03 02:56:29 PM PST 24 |
8328193704 ps |
| T1370 |
/workspace/coverage/default/0.i2c_host_fifo_watermark.3757500164 |
|
|
Mar 03 02:51:08 PM PST 24 |
Mar 03 02:54:18 PM PST 24 |
11193033314 ps |
| T1371 |
/workspace/coverage/default/16.i2c_target_fifo_reset_tx.3286769372 |
|
|
Mar 03 02:53:21 PM PST 24 |
Mar 03 02:53:38 PM PST 24 |
10325608942 ps |
| T1372 |
/workspace/coverage/default/25.i2c_target_hrst.389021851 |
|
|
Mar 03 02:55:14 PM PST 24 |
Mar 03 02:55:17 PM PST 24 |
1076621367 ps |
| T1373 |
/workspace/coverage/default/36.i2c_host_fifo_full.3652578126 |
|
|
Mar 03 02:57:33 PM PST 24 |
Mar 03 03:00:58 PM PST 24 |
3170278114 ps |
| T1374 |
/workspace/coverage/default/19.i2c_target_fifo_reset_tx.655646780 |
|
|
Mar 03 02:53:52 PM PST 24 |
Mar 03 02:54:54 PM PST 24 |
10144154687 ps |
| T1375 |
/workspace/coverage/default/44.i2c_target_stretch.2067951642 |
|
|
Mar 03 02:59:32 PM PST 24 |
Mar 03 03:02:30 PM PST 24 |
13822141924 ps |
| T1376 |
/workspace/coverage/default/49.i2c_target_smoke.1124246133 |
|
|
Mar 03 03:00:42 PM PST 24 |
Mar 03 03:01:04 PM PST 24 |
4666020894 ps |
| T1377 |
/workspace/coverage/default/49.i2c_host_stretch_timeout.1863032004 |
|
|
Mar 03 03:00:45 PM PST 24 |
Mar 03 03:01:21 PM PST 24 |
3433280089 ps |
| T1378 |
/workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2200253215 |
|
|
Mar 03 02:51:42 PM PST 24 |
Mar 03 02:52:04 PM PST 24 |
400164224 ps |
| T1379 |
/workspace/coverage/default/16.i2c_host_rx_oversample.235626600 |
|
|
Mar 03 02:53:12 PM PST 24 |
Mar 03 02:54:42 PM PST 24 |
3818352113 ps |
| T1380 |
/workspace/coverage/default/0.i2c_host_stretch_timeout.2302597822 |
|
|
Mar 03 02:51:12 PM PST 24 |
Mar 03 02:51:26 PM PST 24 |
1300609587 ps |
| T1381 |
/workspace/coverage/default/43.i2c_target_unexp_stop.2492812324 |
|
|
Mar 03 02:59:17 PM PST 24 |
Mar 03 02:59:25 PM PST 24 |
9053757739 ps |
| T1382 |
/workspace/coverage/default/39.i2c_host_smoke.379580553 |
|
|
Mar 03 02:58:17 PM PST 24 |
Mar 03 03:00:07 PM PST 24 |
11061861899 ps |
| T1383 |
/workspace/coverage/default/49.i2c_host_fifo_reset_fmt.4052704740 |
|
|
Mar 03 03:00:42 PM PST 24 |
Mar 03 03:00:43 PM PST 24 |
406028783 ps |
| T1384 |
/workspace/coverage/default/30.i2c_target_stress_all.2034027676 |
|
|
Mar 03 02:56:11 PM PST 24 |
Mar 03 03:11:22 PM PST 24 |
33527520224 ps |
| T1385 |
/workspace/coverage/default/9.i2c_host_fifo_full.3415027895 |
|
|
Mar 03 02:52:04 PM PST 24 |
Mar 03 02:55:33 PM PST 24 |
29999884843 ps |
| T1386 |
/workspace/coverage/default/22.i2c_host_fifo_full.1200612570 |
|
|
Mar 03 02:54:21 PM PST 24 |
Mar 03 02:55:22 PM PST 24 |
3991899739 ps |
| T1387 |
/workspace/coverage/default/20.i2c_host_override.2697028129 |
|
|
Mar 03 02:53:54 PM PST 24 |
Mar 03 02:53:55 PM PST 24 |
17096031 ps |
| T1388 |
/workspace/coverage/default/42.i2c_alert_test.2021346332 |
|
|
Mar 03 02:59:10 PM PST 24 |
Mar 03 02:59:10 PM PST 24 |
17370457 ps |
| T1389 |
/workspace/coverage/default/32.i2c_target_stress_wr.712449053 |
|
|
Mar 03 02:56:38 PM PST 24 |
Mar 03 02:57:44 PM PST 24 |
23338427019 ps |
| T1390 |
/workspace/coverage/default/46.i2c_host_fifo_watermark.3603424379 |
|
|
Mar 03 02:59:55 PM PST 24 |
Mar 03 03:01:05 PM PST 24 |
31754672402 ps |
| T1391 |
/workspace/coverage/default/29.i2c_host_override.1711145514 |
|
|
Mar 03 02:55:56 PM PST 24 |
Mar 03 02:55:56 PM PST 24 |
51171480 ps |
| T1392 |
/workspace/coverage/default/29.i2c_target_timeout.419585652 |
|
|
Mar 03 02:55:59 PM PST 24 |
Mar 03 02:56:06 PM PST 24 |
1842043274 ps |
| T1393 |
/workspace/coverage/default/27.i2c_host_stretch_timeout.3714945343 |
|
|
Mar 03 02:55:34 PM PST 24 |
Mar 03 02:55:55 PM PST 24 |
2252861325 ps |
| T1394 |
/workspace/coverage/default/36.i2c_target_timeout.3796816925 |
|
|
Mar 03 02:57:38 PM PST 24 |
Mar 03 02:57:46 PM PST 24 |
7368098978 ps |
| T1395 |
/workspace/coverage/default/27.i2c_host_fifo_reset_rx.528193949 |
|
|
Mar 03 02:55:29 PM PST 24 |
Mar 03 02:55:35 PM PST 24 |
244284314 ps |
| T1396 |
/workspace/coverage/default/31.i2c_target_intr_smoke.689608323 |
|
|
Mar 03 02:56:25 PM PST 24 |
Mar 03 02:56:32 PM PST 24 |
3308827585 ps |
| T1397 |
/workspace/coverage/default/8.i2c_host_perf.2190839354 |
|
|
Mar 03 02:51:56 PM PST 24 |
Mar 03 03:20:58 PM PST 24 |
52697963804 ps |
| T1398 |
/workspace/coverage/default/1.i2c_host_fifo_full.3135293132 |
|
|
Mar 03 02:51:16 PM PST 24 |
Mar 03 02:52:23 PM PST 24 |
2533859871 ps |
| T1399 |
/workspace/coverage/default/35.i2c_host_fifo_full.2376041901 |
|
|
Mar 03 02:57:20 PM PST 24 |
Mar 03 02:58:43 PM PST 24 |
8889085877 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.730942929 |
|
|
Mar 03 01:38:09 PM PST 24 |
Mar 03 01:38:10 PM PST 24 |
254559902 ps |
| T223 |
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2496523141 |
|
|
Mar 03 01:38:24 PM PST 24 |
Mar 03 01:38:25 PM PST 24 |
41456158 ps |
| T146 |
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2127752387 |
|
|
Mar 03 01:37:41 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
33925459 ps |
| T104 |
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.3200061196 |
|
|
Mar 03 01:38:19 PM PST 24 |
Mar 03 01:38:20 PM PST 24 |
56988181 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2933498240 |
|
|
Mar 03 01:38:11 PM PST 24 |
Mar 03 01:38:12 PM PST 24 |
40279120 ps |
| T66 |
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3501328387 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:38:01 PM PST 24 |
166502669 ps |
| T119 |
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.150000836 |
|
|
Mar 03 01:38:03 PM PST 24 |
Mar 03 01:38:04 PM PST 24 |
43523049 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1014404968 |
|
|
Mar 03 01:37:51 PM PST 24 |
Mar 03 01:37:53 PM PST 24 |
114980085 ps |
| T67 |
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.660840238 |
|
|
Mar 03 01:38:09 PM PST 24 |
Mar 03 01:38:10 PM PST 24 |
86599400 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3618808557 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
150614122 ps |
| T100 |
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.311319770 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:13 PM PST 24 |
68367904 ps |
| T1400 |
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2744549089 |
|
|
Mar 03 01:38:28 PM PST 24 |
Mar 03 01:38:29 PM PST 24 |
19985517 ps |
| T1401 |
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1234046987 |
|
|
Mar 03 01:37:48 PM PST 24 |
Mar 03 01:37:49 PM PST 24 |
28825768 ps |
| T69 |
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1297983129 |
|
|
Mar 03 01:37:55 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
250873118 ps |
| T147 |
/workspace/coverage/cover_reg_top/43.i2c_intr_test.2368497134 |
|
|
Mar 03 01:38:27 PM PST 24 |
Mar 03 01:38:28 PM PST 24 |
21656836 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.311561770 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:13 PM PST 24 |
75398376 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3798876891 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:45 PM PST 24 |
118557620 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1558748737 |
|
|
Mar 03 01:38:01 PM PST 24 |
Mar 03 01:38:04 PM PST 24 |
110724009 ps |
| T225 |
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3253899650 |
|
|
Mar 03 01:38:23 PM PST 24 |
Mar 03 01:38:24 PM PST 24 |
50669170 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3179534692 |
|
|
Mar 03 01:37:41 PM PST 24 |
Mar 03 01:37:45 PM PST 24 |
110274717 ps |
| T222 |
/workspace/coverage/cover_reg_top/34.i2c_intr_test.1566935953 |
|
|
Mar 03 01:38:27 PM PST 24 |
Mar 03 01:38:28 PM PST 24 |
20410772 ps |
| T224 |
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3608081124 |
|
|
Mar 03 01:38:29 PM PST 24 |
Mar 03 01:38:30 PM PST 24 |
45976720 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.3927240257 |
|
|
Mar 03 01:38:13 PM PST 24 |
Mar 03 01:38:14 PM PST 24 |
18573703 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4119626581 |
|
|
Mar 03 01:37:40 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
243783619 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1135952198 |
|
|
Mar 03 01:37:39 PM PST 24 |
Mar 03 01:37:43 PM PST 24 |
41536830 ps |
| T1402 |
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3017836283 |
|
|
Mar 03 01:38:26 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
98145938 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3566012721 |
|
|
Mar 03 01:37:37 PM PST 24 |
Mar 03 01:37:40 PM PST 24 |
252373035 ps |
| T1403 |
/workspace/coverage/cover_reg_top/11.i2c_intr_test.102280924 |
|
|
Mar 03 01:38:03 PM PST 24 |
Mar 03 01:38:04 PM PST 24 |
19355462 ps |
| T1404 |
/workspace/coverage/cover_reg_top/27.i2c_intr_test.1390124916 |
|
|
Mar 03 01:38:25 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
86806474 ps |
| T1405 |
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1097058009 |
|
|
Mar 03 01:38:06 PM PST 24 |
Mar 03 01:38:07 PM PST 24 |
117559419 ps |
| T1406 |
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3087348196 |
|
|
Mar 03 01:37:33 PM PST 24 |
Mar 03 01:37:34 PM PST 24 |
21672746 ps |
| T1407 |
/workspace/coverage/cover_reg_top/23.i2c_intr_test.1131194193 |
|
|
Mar 03 01:38:25 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
39522981 ps |
| T1408 |
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1075496036 |
|
|
Mar 03 01:38:27 PM PST 24 |
Mar 03 01:38:28 PM PST 24 |
27074799 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.4037046057 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:14 PM PST 24 |
486925319 ps |
| T120 |
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.253595631 |
|
|
Mar 03 01:37:49 PM PST 24 |
Mar 03 01:37:50 PM PST 24 |
125982378 ps |
| T121 |
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3350543813 |
|
|
Mar 03 01:38:19 PM PST 24 |
Mar 03 01:38:20 PM PST 24 |
22741740 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2292497464 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
52440662 ps |
| T1409 |
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2267379955 |
|
|
Mar 03 01:38:06 PM PST 24 |
Mar 03 01:38:07 PM PST 24 |
99166444 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3575703080 |
|
|
Mar 03 01:38:18 PM PST 24 |
Mar 03 01:38:19 PM PST 24 |
52592420 ps |
| T110 |
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3090437469 |
|
|
Mar 03 01:38:11 PM PST 24 |
Mar 03 01:38:12 PM PST 24 |
42896208 ps |
| T1410 |
/workspace/coverage/cover_reg_top/48.i2c_intr_test.1607927603 |
|
|
Mar 03 01:38:30 PM PST 24 |
Mar 03 01:38:31 PM PST 24 |
36729266 ps |
| T1411 |
/workspace/coverage/cover_reg_top/22.i2c_intr_test.3082689530 |
|
|
Mar 03 01:38:29 PM PST 24 |
Mar 03 01:38:30 PM PST 24 |
51517475 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1654662511 |
|
|
Mar 03 01:38:05 PM PST 24 |
Mar 03 01:38:07 PM PST 24 |
85616217 ps |
| T1412 |
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3443861911 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
55382773 ps |
| T1413 |
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3315231203 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:53 PM PST 24 |
61197053 ps |
| T123 |
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3369175919 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
89150522 ps |
| T84 |
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.937278770 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
242658789 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1878893876 |
|
|
Mar 03 01:38:18 PM PST 24 |
Mar 03 01:38:20 PM PST 24 |
114690629 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1755319999 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:39 PM PST 24 |
42194483 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1267658399 |
|
|
Mar 03 01:37:41 PM PST 24 |
Mar 03 01:37:45 PM PST 24 |
411790110 ps |
| T125 |
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.151253708 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
303680200 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3400657964 |
|
|
Mar 03 01:38:08 PM PST 24 |
Mar 03 01:38:09 PM PST 24 |
46625605 ps |
| T173 |
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3520060399 |
|
|
Mar 03 01:37:40 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
252740248 ps |
| T1414 |
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2959469736 |
|
|
Mar 03 01:38:24 PM PST 24 |
Mar 03 01:38:25 PM PST 24 |
16670384 ps |
| T1415 |
/workspace/coverage/cover_reg_top/42.i2c_intr_test.451459217 |
|
|
Mar 03 01:38:24 PM PST 24 |
Mar 03 01:38:25 PM PST 24 |
15646934 ps |
| T1416 |
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4248295653 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
199549882 ps |
| T80 |
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4035204744 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:14 PM PST 24 |
245933649 ps |
| T1417 |
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1792802266 |
|
|
Mar 03 01:38:26 PM PST 24 |
Mar 03 01:38:28 PM PST 24 |
36768106 ps |
| T1418 |
/workspace/coverage/cover_reg_top/12.i2c_intr_test.3199668363 |
|
|
Mar 03 01:38:03 PM PST 24 |
Mar 03 01:38:04 PM PST 24 |
19581229 ps |
| T1419 |
/workspace/coverage/cover_reg_top/14.i2c_intr_test.2567521017 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:12 PM PST 24 |
18673605 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2321842828 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
71960425 ps |
| T1420 |
/workspace/coverage/cover_reg_top/8.i2c_intr_test.957370030 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
15200060 ps |
| T76 |
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.1811629278 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
32457836 ps |
| T1421 |
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2105094364 |
|
|
Mar 03 01:38:15 PM PST 24 |
Mar 03 01:38:17 PM PST 24 |
99242462 ps |
| T1422 |
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4141655310 |
|
|
Mar 03 01:38:06 PM PST 24 |
Mar 03 01:38:08 PM PST 24 |
527791304 ps |
| T1423 |
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.837670871 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
99203573 ps |
| T1424 |
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2442956198 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
25539530 ps |
| T1425 |
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3227210 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
50296363 ps |
| T1426 |
/workspace/coverage/cover_reg_top/33.i2c_intr_test.1371832838 |
|
|
Mar 03 01:38:27 PM PST 24 |
Mar 03 01:38:29 PM PST 24 |
26407268 ps |
| T1427 |
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3057988730 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
111615029 ps |
| T1428 |
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1025096290 |
|
|
Mar 03 01:38:01 PM PST 24 |
Mar 03 01:38:02 PM PST 24 |
29339638 ps |
| T1429 |
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3979422767 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
100955300 ps |
| T1430 |
/workspace/coverage/cover_reg_top/45.i2c_intr_test.1936893189 |
|
|
Mar 03 01:38:26 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
23812161 ps |
| T1431 |
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.786693630 |
|
|
Mar 03 01:38:02 PM PST 24 |
Mar 03 01:38:03 PM PST 24 |
293377780 ps |
| T1432 |
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2799430903 |
|
|
Mar 03 01:37:51 PM PST 24 |
Mar 03 01:37:56 PM PST 24 |
668089941 ps |
| T1433 |
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2026167986 |
|
|
Mar 03 01:38:18 PM PST 24 |
Mar 03 01:38:19 PM PST 24 |
25543082 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3831491268 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
83808290 ps |
| T1434 |
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3923155360 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:53 PM PST 24 |
627556297 ps |
| T1435 |
/workspace/coverage/cover_reg_top/1.i2c_intr_test.845377726 |
|
|
Mar 03 01:37:43 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
47500169 ps |
| T1436 |
/workspace/coverage/cover_reg_top/4.i2c_intr_test.1563270484 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:50 PM PST 24 |
21327781 ps |
| T1437 |
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1929296886 |
|
|
Mar 03 01:38:04 PM PST 24 |
Mar 03 01:38:05 PM PST 24 |
192015360 ps |
| T1438 |
/workspace/coverage/cover_reg_top/38.i2c_intr_test.813046354 |
|
|
Mar 03 01:38:29 PM PST 24 |
Mar 03 01:38:30 PM PST 24 |
21761278 ps |
| T1439 |
/workspace/coverage/cover_reg_top/24.i2c_intr_test.941250370 |
|
|
Mar 03 01:38:24 PM PST 24 |
Mar 03 01:38:25 PM PST 24 |
45853569 ps |
| T1440 |
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2309053334 |
|
|
Mar 03 01:38:03 PM PST 24 |
Mar 03 01:38:06 PM PST 24 |
979472385 ps |
| T1441 |
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.590288463 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
36747818 ps |
| T1442 |
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2904844061 |
|
|
Mar 03 01:38:11 PM PST 24 |
Mar 03 01:38:12 PM PST 24 |
96437139 ps |
| T1443 |
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.479368877 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
49314566 ps |
| T1444 |
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3601607212 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
77618363 ps |
| T1445 |
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.239539371 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
81975801 ps |
| T1446 |
/workspace/coverage/cover_reg_top/17.i2c_intr_test.348069718 |
|
|
Mar 03 01:38:23 PM PST 24 |
Mar 03 01:38:24 PM PST 24 |
21003437 ps |
| T1447 |
/workspace/coverage/cover_reg_top/3.i2c_intr_test.3193354362 |
|
|
Mar 03 01:37:43 PM PST 24 |
Mar 03 01:37:45 PM PST 24 |
19399932 ps |
| T1448 |
/workspace/coverage/cover_reg_top/25.i2c_intr_test.1256690689 |
|
|
Mar 03 01:38:25 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
51308341 ps |
| T1449 |
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1035132323 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:40 PM PST 24 |
178552057 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2512922002 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
774033639 ps |
| T1450 |
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3362748147 |
|
|
Mar 03 01:37:49 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
72561954 ps |
| T1451 |
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1469978800 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
67613028 ps |
| T1452 |
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1013206996 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
40763999 ps |
| T1453 |
/workspace/coverage/cover_reg_top/26.i2c_intr_test.1011949814 |
|
|
Mar 03 01:38:28 PM PST 24 |
Mar 03 01:38:29 PM PST 24 |
16055495 ps |
| T1454 |
/workspace/coverage/cover_reg_top/30.i2c_intr_test.586314433 |
|
|
Mar 03 01:38:23 PM PST 24 |
Mar 03 01:38:24 PM PST 24 |
43887823 ps |
| T1455 |
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.486756389 |
|
|
Mar 03 01:37:45 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
41376648 ps |
| T1456 |
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1841248741 |
|
|
Mar 03 01:38:12 PM PST 24 |
Mar 03 01:38:13 PM PST 24 |
138170367 ps |
| T1457 |
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2202644170 |
|
|
Mar 03 01:38:13 PM PST 24 |
Mar 03 01:38:15 PM PST 24 |
34766097 ps |
| T1458 |
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.302169699 |
|
|
Mar 03 01:37:47 PM PST 24 |
Mar 03 01:37:48 PM PST 24 |
62572998 ps |
| T1459 |
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.844410190 |
|
|
Mar 03 01:37:47 PM PST 24 |
Mar 03 01:37:48 PM PST 24 |
23379438 ps |
| T1460 |
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.395831658 |
|
|
Mar 03 01:37:44 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
256781134 ps |
| T1461 |
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2441040122 |
|
|
Mar 03 01:37:56 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
61627735 ps |
| T1462 |
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2368231164 |
|
|
Mar 03 01:38:17 PM PST 24 |
Mar 03 01:38:18 PM PST 24 |
24690497 ps |
| T1463 |
/workspace/coverage/cover_reg_top/31.i2c_intr_test.2693366046 |
|
|
Mar 03 01:38:36 PM PST 24 |
Mar 03 01:38:38 PM PST 24 |
18564669 ps |
| T1464 |
/workspace/coverage/cover_reg_top/36.i2c_intr_test.3006685951 |
|
|
Mar 03 01:38:26 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
48321289 ps |
| T1465 |
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.2060717543 |
|
|
Mar 03 01:37:40 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
180986038 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.3198786411 |
|
|
Mar 03 01:38:04 PM PST 24 |
Mar 03 01:38:05 PM PST 24 |
19010327 ps |
| T86 |
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1046195698 |
|
|
Mar 03 01:38:11 PM PST 24 |
Mar 03 01:38:13 PM PST 24 |
72819215 ps |
| T1466 |
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.544360529 |
|
|
Mar 03 01:38:11 PM PST 24 |
Mar 03 01:38:12 PM PST 24 |
86203524 ps |
| T1467 |
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2185745109 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
20797996 ps |
| T1468 |
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3022819758 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
108633561 ps |
| T1469 |
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2569446069 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:38 PM PST 24 |
36403738 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1442115813 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
24976570 ps |
| T1470 |
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.160369828 |
|
|
Mar 03 01:37:51 PM PST 24 |
Mar 03 01:37:52 PM PST 24 |
34778535 ps |
| T1471 |
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3699370386 |
|
|
Mar 03 01:38:27 PM PST 24 |
Mar 03 01:38:28 PM PST 24 |
140181068 ps |
| T1472 |
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3749483254 |
|
|
Mar 03 01:38:20 PM PST 24 |
Mar 03 01:38:21 PM PST 24 |
45902622 ps |
| T1473 |
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1837383856 |
|
|
Mar 03 01:37:56 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
84650276 ps |
| T1474 |
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1530560918 |
|
|
Mar 03 01:38:05 PM PST 24 |
Mar 03 01:38:06 PM PST 24 |
297587332 ps |
| T1475 |
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1683265154 |
|
|
Mar 03 01:38:10 PM PST 24 |
Mar 03 01:38:11 PM PST 24 |
130122356 ps |
| T1476 |
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1937276884 |
|
|
Mar 03 01:38:20 PM PST 24 |
Mar 03 01:38:21 PM PST 24 |
90484204 ps |
| T1477 |
/workspace/coverage/cover_reg_top/10.i2c_intr_test.4041036475 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
16979874 ps |
| T1478 |
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2455887327 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:39 PM PST 24 |
344304681 ps |
| T1479 |
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3415763519 |
|
|
Mar 03 01:37:43 PM PST 24 |
Mar 03 01:37:48 PM PST 24 |
377543034 ps |
| T1480 |
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.4100237626 |
|
|
Mar 03 01:37:56 PM PST 24 |
Mar 03 01:37:56 PM PST 24 |
29190647 ps |
| T1481 |
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.257262377 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
104849780 ps |
| T1482 |
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.28175401 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:45 PM PST 24 |
43500359 ps |
| T1483 |
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1207273097 |
|
|
Mar 03 01:38:04 PM PST 24 |
Mar 03 01:38:05 PM PST 24 |
21479920 ps |
| T116 |
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4232818587 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:50 PM PST 24 |
41328006 ps |
| T1484 |
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1039538903 |
|
|
Mar 03 01:37:42 PM PST 24 |
Mar 03 01:37:44 PM PST 24 |
22643793 ps |
| T1485 |
/workspace/coverage/cover_reg_top/29.i2c_intr_test.199411439 |
|
|
Mar 03 01:38:29 PM PST 24 |
Mar 03 01:38:30 PM PST 24 |
23287849 ps |
| T1486 |
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1722477684 |
|
|
Mar 03 01:37:49 PM PST 24 |
Mar 03 01:37:50 PM PST 24 |
111189098 ps |
| T1487 |
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.1152181765 |
|
|
Mar 03 01:38:18 PM PST 24 |
Mar 03 01:38:20 PM PST 24 |
230232813 ps |
| T1488 |
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.771466746 |
|
|
Mar 03 01:37:50 PM PST 24 |
Mar 03 01:37:51 PM PST 24 |
43012898 ps |
| T115 |
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1861620690 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:58 PM PST 24 |
35313652 ps |
| T1489 |
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2434344247 |
|
|
Mar 03 01:38:19 PM PST 24 |
Mar 03 01:38:20 PM PST 24 |
18192101 ps |
| T1490 |
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1033726390 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
24911413 ps |
| T1491 |
/workspace/coverage/cover_reg_top/39.i2c_intr_test.2999567734 |
|
|
Mar 03 01:38:25 PM PST 24 |
Mar 03 01:38:26 PM PST 24 |
25249868 ps |
| T1492 |
/workspace/coverage/cover_reg_top/16.i2c_intr_test.1407304946 |
|
|
Mar 03 01:38:13 PM PST 24 |
Mar 03 01:38:14 PM PST 24 |
22105383 ps |
| T1493 |
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2382528291 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:38 PM PST 24 |
26450145 ps |
| T1494 |
/workspace/coverage/cover_reg_top/6.i2c_intr_test.1202525349 |
|
|
Mar 03 01:37:58 PM PST 24 |
Mar 03 01:37:59 PM PST 24 |
18736853 ps |
| T1495 |
/workspace/coverage/cover_reg_top/21.i2c_intr_test.416462789 |
|
|
Mar 03 01:38:29 PM PST 24 |
Mar 03 01:38:30 PM PST 24 |
16708382 ps |
| T117 |
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1415022669 |
|
|
Mar 03 01:37:49 PM PST 24 |
Mar 03 01:37:50 PM PST 24 |
42698682 ps |
| T1496 |
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4055849700 |
|
|
Mar 03 01:38:03 PM PST 24 |
Mar 03 01:38:05 PM PST 24 |
138653510 ps |
| T1497 |
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1065872905 |
|
|
Mar 03 01:38:06 PM PST 24 |
Mar 03 01:38:07 PM PST 24 |
20404250 ps |
| T1498 |
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1958560874 |
|
|
Mar 03 01:37:57 PM PST 24 |
Mar 03 01:37:57 PM PST 24 |
55872998 ps |
| T204 |
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.746621548 |
|
|
Mar 03 01:38:04 PM PST 24 |
Mar 03 01:38:06 PM PST 24 |
329713792 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3099256884 |
|
|
Mar 03 01:37:35 PM PST 24 |
Mar 03 01:37:37 PM PST 24 |
38132224 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3731969221 |
|
|
Mar 03 01:37:45 PM PST 24 |
Mar 03 01:37:46 PM PST 24 |
38549466 ps |
| T1499 |
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2353474933 |
|
|
Mar 03 01:37:59 PM PST 24 |
Mar 03 01:38:00 PM PST 24 |
30388796 ps |
| T1500 |
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.59454584 |
|
|
Mar 03 01:38:16 PM PST 24 |
Mar 03 01:38:18 PM PST 24 |
93067973 ps |