Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6138005	1			T1	12		T2	56288		T3	3
all_values[1]	6138005	1			T1	12		T2	56288		T3	3
all_values[2]	6138005	1			T1	12		T2	56288		T3	3
all_values[3]	6138005	1			T1	12		T2	56288		T3	3
all_values[4]	6138005	1			T1	12		T2	56288		T3	3
all_values[5]	6138005	1			T1	12		T2	56288		T3	3
all_values[6]	6138005	1			T1	12		T2	56288		T3	3
all_values[7]	6138005	1			T1	12		T2	56288		T3	3
all_values[8]	6138005	1			T1	12		T2	56288		T3	3
all_values[9]	6138005	1			T1	12		T2	56288		T3	3
all_values[10]	6138005	1			T1	12		T2	56288		T3	3
all_values[11]	6138005	1			T1	12		T2	56288		T3	3
all_values[12]	6138005	1			T1	12		T2	56288		T3	3
all_values[13]	6138005	1			T1	12		T2	56288		T3	3
all_values[14]	6138005	1			T1	12		T2	56288		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76906915

1

T1

156

T2

728865

T3

37

auto[1]

15163160

1

T1

24

T2

115455

T3

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80509565

1

T1

180

T2

566143

T3

45

auto[1]

11560510

1

T2

278177

T58

131927

T59

124294

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3] , all_values[4] , all_values[5]]	[auto[1]]	[auto[0]]	--	--	4
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	868821	1			T2	1547		T3	1		T16	1
all_values[0]	auto[0]	auto[1]	104850	1			T2	8		T58	402		T59	4
all_values[0]	auto[1]	auto[0]	4526882	1			T1	12		T2	33342		T3	2
all_values[0]	auto[1]	auto[1]	637452	1			T2	21391		T58	9747		T59	8
all_values[1]	auto[0]	auto[0]	5377434	1			T1	12		T2	34874		T3	3
all_values[1]	auto[0]	auto[1]	757387	1			T2	21393		T59	9556		T60	50360
all_values[1]	auto[1]	auto[0]	2805	1			T2	15		T12	5		T64	14
all_values[1]	auto[1]	auto[1]	379	1			T2	6		T59	3		T60	7
all_values[2]	auto[0]	auto[0]	5354987	1			T1	12		T2	34891		T3	3
all_values[2]	auto[0]	auto[1]	782793	1			T2	21396		T58	10147		T59	9555
all_values[2]	auto[1]	auto[1]	225	1			T2	1		T58	2		T59	4
all_values[3]	auto[0]	auto[0]	5370085	1			T1	12		T2	34891		T3	3
all_values[3]	auto[0]	auto[1]	767676	1			T2	21395		T58	10145		T59	9557
all_values[3]	auto[1]	auto[1]	244	1			T2	2		T58	2		T59	3
all_values[4]	auto[0]	auto[0]	5346217	1			T1	12		T2	56288		T3	3
all_values[4]	auto[0]	auto[1]	791522	1			T58	10145		T59	9552		T60	50353
all_values[4]	auto[1]	auto[1]	266	1			T58	3		T59	6		T60	14
all_values[5]	auto[0]	auto[0]	5396321	1			T1	12		T2	34891		T3	3
all_values[5]	auto[0]	auto[1]	741427	1			T2	21395		T59	9555		T60	50355
all_values[5]	auto[1]	auto[1]	257	1			T2	2		T59	5		T60	12
all_values[6]	auto[0]	auto[0]	4465490	1			T1	12		T2	56161		T3	2
all_values[6]	auto[0]	auto[1]	554163	1			T58	5451		T59	9515		T60	1927
all_values[6]	auto[1]	auto[0]	880724	1			T2	127		T3	1		T16	1
all_values[6]	auto[1]	auto[1]	237628	1			T58	4696		T59	43		T60	48442
all_values[7]	auto[0]	auto[0]	5127290	1			T1	12		T2	33383		T3	2
all_values[7]	auto[0]	auto[1]	675464	1			T2	19517		T58	9384		T59	7550
all_values[7]	auto[1]	auto[0]	313100	1			T2	1506		T3	1		T16	1
all_values[7]	auto[1]	auto[1]	22151	1			T2	1882		T58	765		T59	2010
all_values[8]	auto[0]	auto[0]	4265267	1			T1	12		T2	34344		T3	2
all_values[8]	auto[0]	auto[1]	557048	1			T2	21134		T58	5178		T59	9143
all_values[8]	auto[1]	auto[0]	1061889	1			T2	545		T3	1		T16	1
all_values[8]	auto[1]	auto[1]	253801	1			T2	265		T58	4970		T59	417
all_values[9]	auto[0]	auto[0]	4473762	1			T1	12		T2	34836		T3	2
all_values[9]	auto[0]	auto[1]	573911	1			T2	21360		T58	5480		T59	9520
all_values[9]	auto[1]	auto[0]	851097	1			T2	53		T3	1		T16	1
all_values[9]	auto[1]	auto[1]	239235	1			T2	39		T58	4669		T59	39
all_values[10]	auto[0]	auto[0]	5324823	1			T1	12		T2	34890		T3	3
all_values[10]	auto[0]	auto[1]	812972	1			T2	21396		T58	10147		T59	9556
all_values[10]	auto[1]	auto[1]	210	1			T2	2		T58	1		T59	3
all_values[11]	auto[0]	auto[0]	3282	1			T2	10		T3	1		T16	1
all_values[11]	auto[0]	auto[1]	645	1			T2	7		T58	15		T59	22
all_values[11]	auto[1]	auto[0]	5321541	1			T1	12		T2	34879		T3	2
all_values[11]	auto[1]	auto[1]	812537	1			T2	21392		T58	10132		T59	9538
all_values[12]	auto[0]	auto[0]	5518583	1			T1	12		T2	34889		T3	3
all_values[12]	auto[0]	auto[1]	619198	1			T2	21397		T58	10146		T59	9556
all_values[12]	auto[1]	auto[1]	224	1			T2	2		T58	2		T59	4
all_values[13]	auto[0]	auto[0]	5324788	1			T1	12		T2	34890		T3	3
all_values[13]	auto[0]	auto[1]	812951	1			T2	21396		T58	10147		T59	9555
all_values[13]	auto[1]	auto[0]	11	1			T191	1		T192	1		T193	1
all_values[13]	auto[1]	auto[1]	255	1			T2	2		T58	2		T59	5
all_values[14]	auto[0]	auto[0]	5334366	1			T1	12		T2	34891		T3	3
all_values[14]	auto[0]	auto[1]	803392	1			T2	21395		T58	10145		T59	8
all_values[14]	auto[1]	auto[1]	247	1			T2	2		T58	4		T59	2