Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6138005	1			T1	12		T2	56288		T3	3
all_pins[1]	6138005	1			T1	12		T2	56288		T3	3
all_pins[2]	6138005	1			T1	12		T2	56288		T3	3
all_pins[3]	6138005	1			T1	12		T2	56288		T3	3
all_pins[4]	6138005	1			T1	12		T2	56288		T3	3
all_pins[5]	6138005	1			T1	12		T2	56288		T3	3
all_pins[6]	6138005	1			T1	12		T2	56288		T3	3
all_pins[7]	6138005	1			T1	12		T2	56288		T3	3
all_pins[8]	6138005	1			T1	12		T2	56288		T3	3
all_pins[9]	6138005	1			T1	12		T2	56288		T3	3
all_pins[10]	6138005	1			T1	12		T2	56288		T3	3
all_pins[11]	6138005	1			T1	12		T2	56288		T3	3
all_pins[12]	6138005	1			T1	12		T2	56288		T3	3
all_pins[13]	6138005	1			T1	12		T2	56288		T3	3
all_pins[14]	6138005	1			T1	12		T2	56288		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	76833211	1			T1	156		T2	728174		T3	37
values[0x1]	15236864	1			T1	24		T2	116146		T3	8
transitions[0x0=>0x1]	14056814	1			T1	24		T2	115971		T3	5
transitions[0x1=>0x0]	14055675	1			T1	23		T2	115970		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	974017	1			T2	1557		T3	1		T16	1
all_pins[0]	values[0x1]	5163988	1			T1	12		T2	54731		T3	2
all_pins[0]	transitions[0x0=>0x1]	5160474	1			T1	12		T2	54709		T3	2
all_pins[0]	transitions[0x1=>0x0]	128	1			T2	2		T59	2		T60	2
all_pins[1]	values[0x0]	6134363	1			T1	12		T2	56264		T3	3
all_pins[1]	values[0x1]	3642	1			T2	24		T12	8		T64	17
all_pins[1]	transitions[0x0=>0x1]	3617	1			T2	24		T12	8		T64	17
all_pins[1]	transitions[0x1=>0x0]	79	1			T58	1		T59	1		T60	2
all_pins[2]	values[0x0]	6137901	1			T1	12		T2	56288		T3	3
all_pins[2]	values[0x1]	104	1			T58	1		T59	1		T60	3
all_pins[2]	transitions[0x0=>0x1]	78	1			T58	1		T59	1		T60	2
all_pins[2]	transitions[0x1=>0x0]	99	1			T2	2		T59	3		T60	5
all_pins[3]	values[0x0]	6137880	1			T1	12		T2	56286		T3	3
all_pins[3]	values[0x1]	125	1			T2	2		T59	3		T60	6
all_pins[3]	transitions[0x0=>0x1]	97	1			T2	2		T59	1		T60	3
all_pins[3]	transitions[0x1=>0x0]	100	1			T58	2		T60	1		T97	1
all_pins[4]	values[0x0]	6137877	1			T1	12		T2	56288		T3	3
all_pins[4]	values[0x1]	128	1			T58	2		T59	2		T60	4
all_pins[4]	transitions[0x0=>0x1]	99	1			T58	2		T59	2		T60	2
all_pins[4]	transitions[0x1=>0x0]	101	1			T59	3		T60	8		T97	2
all_pins[5]	values[0x0]	6137875	1			T1	12		T2	56288		T3	3
all_pins[5]	values[0x1]	130	1			T59	3		T60	10		T97	2
all_pins[5]	transitions[0x0=>0x1]	100	1			T59	3		T60	10		T97	2
all_pins[5]	transitions[0x1=>0x0]	1122500	1			T2	140		T3	1		T16	1
all_pins[6]	values[0x0]	5015475	1			T1	12		T2	56148		T3	2
all_pins[6]	values[0x1]	1122530	1			T2	140		T3	1		T16	1
all_pins[6]	transitions[0x0=>0x1]	1098686	1			T2	134		T12	406		T64	14366
all_pins[6]	transitions[0x1=>0x0]	352931	1			T2	3912		T12	2487		T24	40
all_pins[7]	values[0x0]	5761230	1			T1	12		T2	52370		T3	2
all_pins[7]	values[0x1]	376775	1			T2	3918		T3	1		T16	1
all_pins[7]	transitions[0x0=>0x1]	306865	1			T2	3774		T12	2098		T24	17
all_pins[7]	transitions[0x1=>0x0]	1273896	1			T2	810		T12	3070		T64	14313
all_pins[8]	values[0x0]	4794199	1			T1	12		T2	55334		T3	2
all_pins[8]	values[0x1]	1343806	1			T2	954		T3	1		T16	1
all_pins[8]	transitions[0x0=>0x1]	261361	1			T2	952		T12	3502		T64	70
all_pins[8]	transitions[0x1=>0x0]	8799	1			T2	103		T12	80		T7	1
all_pins[9]	values[0x0]	5046761	1			T1	12		T2	56183		T3	2
all_pins[9]	values[0x1]	1091244	1			T2	105		T3	1		T16	1
all_pins[9]	transitions[0x0=>0x1]	1091216	1			T2	105		T3	1		T16	1
all_pins[9]	transitions[0x1=>0x0]	72	1			T2	1		T59	1		T60	2
all_pins[10]	values[0x0]	6137905	1			T1	12		T2	56287		T3	3
all_pins[10]	values[0x1]	100	1			T2	1		T59	1		T60	3
all_pins[10]	transitions[0x0=>0x1]	73	1			T59	1		T60	2		T178	3
all_pins[10]	transitions[0x1=>0x0]	6133898	1			T1	12		T2	56270		T3	2
all_pins[11]	values[0x0]	4080	1			T2	17		T3	1		T16	1
all_pins[11]	values[0x1]	6133925	1			T1	12		T2	56271		T3	2
all_pins[11]	transitions[0x0=>0x1]	6133900	1			T1	12		T2	56271		T3	2
all_pins[11]	transitions[0x1=>0x0]	72	1			T58	1		T60	1		T178	1
all_pins[12]	values[0x0]	6137908	1			T1	12		T2	56288		T3	3
all_pins[12]	values[0x1]	97	1			T58	2		T60	3		T178	1
all_pins[12]	transitions[0x0=>0x1]	75	1			T58	2		T60	3		T178	1
all_pins[12]	transitions[0x1=>0x0]	120	1			T59	2		T60	5		T97	2
all_pins[13]	values[0x0]	6137863	1			T1	12		T2	56288		T3	3
all_pins[13]	values[0x1]	142	1			T59	2		T60	5		T97	2
all_pins[13]	transitions[0x0=>0x1]	103	1			T59	2		T60	4		T97	2
all_pins[13]	transitions[0x1=>0x0]	89	1			T58	3		T59	2		T60	5
all_pins[14]	values[0x0]	6137877	1			T1	12		T2	56288		T3	3
all_pins[14]	values[0x1]	128	1			T58	3		T59	2		T60	6
all_pins[14]	transitions[0x0=>0x1]	70	1			T58	3		T59	2		T60	4
all_pins[14]	transitions[0x1=>0x0]	5162791	1			T1	11		T2	54730		T3	1