Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	529	1			T2	4		T58	4		T59	8
all_values[1]	529	1			T2	4		T58	4		T59	8
all_values[2]	529	1			T2	4		T58	4		T59	8
all_values[3]	529	1			T2	4		T58	4		T59	8
all_values[4]	529	1			T2	4		T58	4		T59	8
all_values[5]	529	1			T2	4		T58	4		T59	8
all_values[6]	529	1			T2	4		T58	4		T59	8
all_values[7]	529	1			T2	4		T58	4		T59	8
all_values[8]	529	1			T2	4		T58	4		T59	8
all_values[9]	529	1			T2	4		T58	4		T59	8
all_values[10]	529	1			T2	4		T58	4		T59	8
all_values[11]	529	1			T2	4		T58	4		T59	8
all_values[12]	529	1			T2	4		T58	4		T59	8
all_values[13]	529	1			T2	4		T58	4		T59	8
all_values[14]	529	1			T2	4		T58	4		T59	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4214

1

T2

26

T58

27

T59

70

auto[1]

3721

1

T2

34

T58

33

T59

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T2

18

T58

18

T59

18

auto[1]

6795

1

T2

42

T58

42

T59

102

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701

1

T2

38

T58

39

T59

80

auto[1]

3234

1

T2

22

T58

21

T59

40

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T59	2		T60	1		T178	3
all_values[0]	auto[0]	auto[0]	auto[1]	133	1			T2	2		T58	2		T59	2
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T59	2		T222	1		T223	1
all_values[0]	auto[0]	auto[1]	auto[1]	106	1			T60	3		T97	1		T178	1
all_values[0]	auto[1]	auto[0]	auto[1]	113	1			T2	1		T58	1		T59	2
all_values[0]	auto[1]	auto[1]	auto[1]	112	1			T2	1		T58	1		T60	4
all_values[1]	auto[0]	auto[0]	auto[0]	42	1			T60	1		T105	2		T224	2
all_values[1]	auto[0]	auto[0]	auto[1]	112	1			T59	2		T60	4		T97	2
all_values[1]	auto[0]	auto[1]	auto[0]	45	1			T58	4		T59	1		T60	1
all_values[1]	auto[0]	auto[1]	auto[1]	135	1			T2	2		T59	2		T60	6
all_values[1]	auto[1]	auto[0]	auto[1]	91	1			T2	1		T59	1		T60	3
all_values[1]	auto[1]	auto[1]	auto[1]	104	1			T2	1		T59	2		T60	4
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T2	2		T183	1		T222	2
all_values[2]	auto[0]	auto[0]	auto[1]	144	1			T2	1		T58	2		T59	2
all_values[2]	auto[0]	auto[1]	auto[0]	20	1			T59	1		T183	1		T222	3
all_values[2]	auto[0]	auto[1]	auto[1]	110	1			T59	1		T60	5		T97	1
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T58	1		T59	2		T60	4
all_values[2]	auto[1]	auto[1]	auto[1]	102	1			T2	1		T58	1		T59	2
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T58	1		T60	1		T178	1
all_values[3]	auto[0]	auto[0]	auto[1]	125	1			T58	1		T59	1		T60	5
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T2	2		T58	1		T60	1
all_values[3]	auto[0]	auto[1]	auto[1]	118	1			T2	1		T59	5		T60	6
all_values[3]	auto[1]	auto[0]	auto[1]	114	1			T2	1		T58	1		T60	5
all_values[3]	auto[1]	auto[1]	auto[1]	102	1			T59	2		T60	1		T183	4
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T2	4		T60	2		T178	1
all_values[4]	auto[0]	auto[0]	auto[1]	115	1			T59	2		T60	3		T97	2
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T58	1		T59	2		T178	1
all_values[4]	auto[0]	auto[1]	auto[1]	107	1			T58	1		T59	1		T60	3
all_values[4]	auto[1]	auto[0]	auto[1]	131	1			T58	2		T59	2		T60	7
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T59	1		T60	4		T97	1
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T58	1		T60	1		T178	2
all_values[5]	auto[0]	auto[0]	auto[1]	130	1			T2	1		T59	4		T97	1
all_values[5]	auto[0]	auto[1]	auto[0]	34	1			T2	2		T58	3		T60	1
all_values[5]	auto[0]	auto[1]	auto[1]	113	1			T59	1		T60	8		T97	1
all_values[5]	auto[1]	auto[0]	auto[1]	113	1			T2	1		T59	1		T60	4
all_values[5]	auto[1]	auto[1]	auto[1]	93	1			T59	2		T60	5		T97	1
all_values[6]	auto[0]	auto[0]	auto[0]	31	1			T58	1		T36	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[1]	130	1			T59	4		T60	8		T97	1
all_values[6]	auto[0]	auto[1]	auto[0]	39	1			T2	4		T58	1		T59	2
all_values[6]	auto[0]	auto[1]	auto[1]	106	1			T58	1		T59	1		T60	4
all_values[6]	auto[1]	auto[0]	auto[1]	117	1			T58	1		T59	1		T60	5
all_values[6]	auto[1]	auto[1]	auto[1]	106	1			T60	2		T178	1		T183	2
all_values[7]	auto[0]	auto[0]	auto[0]	64	1			T178	1		T183	3		T225	1
all_values[7]	auto[0]	auto[0]	auto[1]	103	1			T2	1		T59	3		T60	3
all_values[7]	auto[0]	auto[1]	auto[0]	49	1			T60	1		T225	1		T226	1
all_values[7]	auto[0]	auto[1]	auto[1]	132	1			T2	1		T58	2		T59	2
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T2	1		T59	2		T60	3
all_values[7]	auto[1]	auto[1]	auto[1]	87	1			T2	1		T58	2		T59	1
all_values[8]	auto[0]	auto[0]	auto[0]	52	1			T105	1		T140	5		T224	2
all_values[8]	auto[0]	auto[0]	auto[1]	113	1			T2	1		T58	2		T60	3
all_values[8]	auto[0]	auto[1]	auto[0]	34	1			T58	1		T60	1		T97	1
all_values[8]	auto[0]	auto[1]	auto[1]	109	1			T2	1		T59	5		T60	6
all_values[8]	auto[1]	auto[0]	auto[1]	134	1			T58	1		T59	1		T60	4
all_values[8]	auto[1]	auto[1]	auto[1]	87	1			T2	2		T59	2		T60	5
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T59	1		T183	1		T105	1
all_values[9]	auto[0]	auto[0]	auto[1]	110	1			T2	1		T58	3		T59	4
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T105	1		T222	1		T37	1
all_values[9]	auto[0]	auto[1]	auto[1]	127	1			T2	2		T60	5		T97	1
all_values[9]	auto[1]	auto[0]	auto[1]	124	1			T59	3		T60	7		T178	3
all_values[9]	auto[1]	auto[1]	auto[1]	85	1			T2	1		T58	1		T60	2
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T97	1		T105	2		T214	1
all_values[10]	auto[0]	auto[0]	auto[1]	116	1			T2	1		T58	1		T59	4
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T2	1		T58	1		T59	1
all_values[10]	auto[0]	auto[1]	auto[1]	127	1			T58	1		T60	6		T97	1
all_values[10]	auto[1]	auto[0]	auto[1]	115	1			T58	1		T59	1		T60	6
all_values[10]	auto[1]	auto[1]	auto[1]	95	1			T2	2		T59	2		T60	1
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T58	1		T178	1		T183	1
all_values[11]	auto[0]	auto[0]	auto[1]	135	1			T59	5		T60	6		T97	1
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T58	1		T60	1		T223	1
all_values[11]	auto[0]	auto[1]	auto[1]	104	1			T2	1		T58	1		T59	2
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T58	1		T59	1		T60	5
all_values[11]	auto[1]	auto[1]	auto[1]	116	1			T2	3		T60	4		T97	2
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T60	1		T183	4		T214	1
all_values[12]	auto[0]	auto[0]	auto[1]	117	1			T2	1		T59	2		T60	4
all_values[12]	auto[0]	auto[1]	auto[0]	41	1			T58	1		T97	2		T183	3
all_values[12]	auto[0]	auto[1]	auto[1]	112	1			T2	1		T58	1		T59	2
all_values[12]	auto[1]	auto[0]	auto[1]	141	1			T2	2		T59	4		T60	2
all_values[12]	auto[1]	auto[1]	auto[1]	83	1			T58	2		T60	5		T105	4
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T60	1		T140	1		T214	1
all_values[13]	auto[0]	auto[0]	auto[1]	128	1			T2	1		T58	1		T59	4
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T2	1		T36	1		T225	1
all_values[13]	auto[0]	auto[1]	auto[1]	113	1			T60	5		T97	1		T178	1
all_values[13]	auto[1]	auto[0]	auto[1]	124	1			T58	2		T59	4		T60	1
all_values[13]	auto[1]	auto[1]	auto[1]	109	1			T2	2		T58	1		T60	7
all_values[14]	auto[0]	auto[0]	auto[0]	53	1			T2	2		T59	3		T97	1
all_values[14]	auto[0]	auto[0]	auto[1]	121	1			T2	1		T60	6		T97	1
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T59	3		T178	1		T225	1
all_values[14]	auto[0]	auto[1]	auto[1]	110	1			T58	2		T59	1		T60	4
all_values[14]	auto[1]	auto[0]	auto[1]	104	1			T60	2		T97	2		T183	1
all_values[14]	auto[1]	auto[1]	auto[1]	117	1			T2	1		T58	2		T59	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal