| T1306 |
/workspace/coverage/default/43.i2c_target_intr_stress_wr.2496906545 |
|
|
Mar 05 02:36:51 PM PST 24 |
Mar 05 02:37:00 PM PST 24 |
4124377353 ps |
| T1307 |
/workspace/coverage/default/45.i2c_target_stress_rd.3064488000 |
|
|
Mar 05 02:37:22 PM PST 24 |
Mar 05 02:37:53 PM PST 24 |
2958195666 ps |
| T1308 |
/workspace/coverage/default/0.i2c_target_fifo_reset_acq.1638551934 |
|
|
Mar 05 02:23:23 PM PST 24 |
Mar 05 02:24:27 PM PST 24 |
10099152692 ps |
| T1309 |
/workspace/coverage/default/35.i2c_target_timeout.3377276176 |
|
|
Mar 05 02:35:02 PM PST 24 |
Mar 05 02:35:10 PM PST 24 |
5554314903 ps |
| T1310 |
/workspace/coverage/default/33.i2c_target_stress_wr.1324275503 |
|
|
Mar 05 02:34:28 PM PST 24 |
Mar 05 02:34:38 PM PST 24 |
62472748699 ps |
| T1311 |
/workspace/coverage/default/42.i2c_host_override.2672440845 |
|
|
Mar 05 02:36:28 PM PST 24 |
Mar 05 02:36:29 PM PST 24 |
60918910 ps |
| T1312 |
/workspace/coverage/default/32.i2c_target_stress_all.434234648 |
|
|
Mar 05 02:34:18 PM PST 24 |
Mar 05 02:35:38 PM PST 24 |
44821732076 ps |
| T1313 |
/workspace/coverage/default/45.i2c_target_perf.3282850421 |
|
|
Mar 05 02:37:23 PM PST 24 |
Mar 05 02:37:27 PM PST 24 |
2461891174 ps |
| T1314 |
/workspace/coverage/default/20.i2c_host_smoke.4246380821 |
|
|
Mar 05 02:30:47 PM PST 24 |
Mar 05 02:31:52 PM PST 24 |
8983882553 ps |
| T1315 |
/workspace/coverage/default/26.i2c_target_perf.417063944 |
|
|
Mar 05 02:32:42 PM PST 24 |
Mar 05 02:32:46 PM PST 24 |
2585393627 ps |
| T1316 |
/workspace/coverage/default/43.i2c_host_fifo_fmt_empty.135553155 |
|
|
Mar 05 02:36:45 PM PST 24 |
Mar 05 02:36:52 PM PST 24 |
460776719 ps |
| T1317 |
/workspace/coverage/default/2.i2c_target_stress_all.2281184553 |
|
|
Mar 05 02:24:38 PM PST 24 |
Mar 05 02:27:11 PM PST 24 |
44234300071 ps |
| T1318 |
/workspace/coverage/default/40.i2c_target_hrst.3186411677 |
|
|
Mar 05 02:36:14 PM PST 24 |
Mar 05 02:36:17 PM PST 24 |
968602310 ps |
| T1319 |
/workspace/coverage/default/12.i2c_host_stretch_timeout.856784083 |
|
|
Mar 05 02:28:28 PM PST 24 |
Mar 05 02:28:49 PM PST 24 |
4819940876 ps |
| T1320 |
/workspace/coverage/default/39.i2c_target_unexp_stop.3455021087 |
|
|
Mar 05 02:35:54 PM PST 24 |
Mar 05 02:36:01 PM PST 24 |
4024178191 ps |
| T1321 |
/workspace/coverage/default/11.i2c_host_error_intr.335457095 |
|
|
Mar 05 02:28:17 PM PST 24 |
Mar 05 02:28:18 PM PST 24 |
204411571 ps |
| T1322 |
/workspace/coverage/default/47.i2c_target_stress_wr.1920805067 |
|
|
Mar 05 02:37:40 PM PST 24 |
Mar 05 02:46:05 PM PST 24 |
36721807850 ps |
| T1323 |
/workspace/coverage/default/45.i2c_target_bad_addr.1716543492 |
|
|
Mar 05 02:37:26 PM PST 24 |
Mar 05 02:37:30 PM PST 24 |
9723432697 ps |
| T1324 |
/workspace/coverage/default/1.i2c_host_smoke.3328333053 |
|
|
Mar 05 02:23:38 PM PST 24 |
Mar 05 02:24:28 PM PST 24 |
9892462926 ps |
| T1325 |
/workspace/coverage/default/37.i2c_host_stretch_timeout.1205836228 |
|
|
Mar 05 02:35:17 PM PST 24 |
Mar 05 02:35:25 PM PST 24 |
1480483444 ps |
| T1326 |
/workspace/coverage/default/2.i2c_target_hrst.2158785957 |
|
|
Mar 05 02:24:44 PM PST 24 |
Mar 05 02:24:48 PM PST 24 |
1855561232 ps |
| T1327 |
/workspace/coverage/default/38.i2c_target_bad_addr.1475231435 |
|
|
Mar 05 02:35:48 PM PST 24 |
Mar 05 02:35:52 PM PST 24 |
2010246776 ps |
| T1328 |
/workspace/coverage/default/1.i2c_host_fifo_overflow.1138165564 |
|
|
Mar 05 02:23:43 PM PST 24 |
Mar 05 02:27:27 PM PST 24 |
7253644118 ps |
| T1329 |
/workspace/coverage/default/42.i2c_target_intr_stress_wr.902291691 |
|
|
Mar 05 02:36:37 PM PST 24 |
Mar 05 02:36:50 PM PST 24 |
5765211915 ps |
| T1330 |
/workspace/coverage/default/1.i2c_target_intr_stress_wr.1880970840 |
|
|
Mar 05 02:24:04 PM PST 24 |
Mar 05 02:26:19 PM PST 24 |
14948137717 ps |
| T1331 |
/workspace/coverage/default/36.i2c_target_intr_smoke.2424506011 |
|
|
Mar 05 02:35:10 PM PST 24 |
Mar 05 02:35:16 PM PST 24 |
6010143100 ps |
| T1332 |
/workspace/coverage/default/27.i2c_target_stress_wr.2723969017 |
|
|
Mar 05 02:32:48 PM PST 24 |
Mar 05 02:43:21 PM PST 24 |
49387941006 ps |
| T1333 |
/workspace/coverage/default/8.i2c_host_fifo_reset_rx.1151605582 |
|
|
Mar 05 02:27:03 PM PST 24 |
Mar 05 02:27:09 PM PST 24 |
750291856 ps |
| T1334 |
/workspace/coverage/default/38.i2c_target_smoke.1084394663 |
|
|
Mar 05 02:35:40 PM PST 24 |
Mar 05 02:36:21 PM PST 24 |
29514125451 ps |
| T1335 |
/workspace/coverage/default/0.i2c_target_stretch.3309673790 |
|
|
Mar 05 02:23:16 PM PST 24 |
Mar 05 02:25:14 PM PST 24 |
31725967078 ps |
| T1336 |
/workspace/coverage/default/12.i2c_target_perf.4012891081 |
|
|
Mar 05 02:28:37 PM PST 24 |
Mar 05 02:28:43 PM PST 24 |
5211825710 ps |
| T1337 |
/workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2247154812 |
|
|
Mar 05 02:33:18 PM PST 24 |
Mar 05 02:33:43 PM PST 24 |
1004769014 ps |
| T1338 |
/workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2842555384 |
|
|
Mar 05 02:36:44 PM PST 24 |
Mar 05 02:36:46 PM PST 24 |
229350982 ps |
| T1339 |
/workspace/coverage/default/24.i2c_target_intr_stress_wr.3587860396 |
|
|
Mar 05 02:32:02 PM PST 24 |
Mar 05 02:32:28 PM PST 24 |
18623341049 ps |
| T1340 |
/workspace/coverage/default/22.i2c_target_hrst.2055597951 |
|
|
Mar 05 02:31:36 PM PST 24 |
Mar 05 02:31:38 PM PST 24 |
1674110339 ps |
| T1341 |
/workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2598349491 |
|
|
Mar 05 02:34:37 PM PST 24 |
Mar 05 02:34:52 PM PST 24 |
1060084939 ps |
| T38 |
/workspace/coverage/default/15.i2c_host_stress_all.3347611557 |
|
|
Mar 05 02:29:34 PM PST 24 |
Mar 05 02:54:42 PM PST 24 |
109055235351 ps |
| T1342 |
/workspace/coverage/default/33.i2c_host_override.491304719 |
|
|
Mar 05 02:34:20 PM PST 24 |
Mar 05 02:34:21 PM PST 24 |
110168865 ps |
| T1343 |
/workspace/coverage/default/14.i2c_target_bad_addr.4058471834 |
|
|
Mar 05 02:29:20 PM PST 24 |
Mar 05 02:29:24 PM PST 24 |
13044039576 ps |
| T1344 |
/workspace/coverage/default/13.i2c_target_stress_wr.1899388532 |
|
|
Mar 05 02:28:54 PM PST 24 |
Mar 05 02:28:59 PM PST 24 |
11000196718 ps |
| T1345 |
/workspace/coverage/default/48.i2c_target_stretch.638011558 |
|
|
Mar 05 02:37:57 PM PST 24 |
Mar 05 02:48:06 PM PST 24 |
9158313840 ps |
| T1346 |
/workspace/coverage/default/25.i2c_host_override.3831451613 |
|
|
Mar 05 02:32:12 PM PST 24 |
Mar 05 02:32:14 PM PST 24 |
44018705 ps |
| T1347 |
/workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1515762635 |
|
|
Mar 05 02:36:37 PM PST 24 |
Mar 05 02:36:40 PM PST 24 |
780289671 ps |
| T1348 |
/workspace/coverage/default/13.i2c_target_stretch.2492995083 |
|
|
Mar 05 02:28:55 PM PST 24 |
Mar 05 02:35:48 PM PST 24 |
48827132794 ps |
| T1349 |
/workspace/coverage/default/46.i2c_target_unexp_stop.4277848595 |
|
|
Mar 05 02:37:34 PM PST 24 |
Mar 05 02:37:41 PM PST 24 |
24430362998 ps |
| T1350 |
/workspace/coverage/default/8.i2c_target_timeout.4239149019 |
|
|
Mar 05 02:27:13 PM PST 24 |
Mar 05 02:27:20 PM PST 24 |
8128796659 ps |
| T1351 |
/workspace/coverage/default/28.i2c_host_fifo_reset_fmt.354800154 |
|
|
Mar 05 02:33:01 PM PST 24 |
Mar 05 02:33:02 PM PST 24 |
118138150 ps |
| T1352 |
/workspace/coverage/default/47.i2c_target_hrst.2433880903 |
|
|
Mar 05 02:37:47 PM PST 24 |
Mar 05 02:37:50 PM PST 24 |
2218531734 ps |
| T1353 |
/workspace/coverage/default/13.i2c_host_fifo_reset_fmt.773846919 |
|
|
Mar 05 02:28:45 PM PST 24 |
Mar 05 02:28:46 PM PST 24 |
95435763 ps |
| T1354 |
/workspace/coverage/default/41.i2c_host_perf.1574410419 |
|
|
Mar 05 02:36:22 PM PST 24 |
Mar 05 02:43:24 PM PST 24 |
25558278662 ps |
| T1355 |
/workspace/coverage/default/42.i2c_host_stretch_timeout.224088464 |
|
|
Mar 05 02:36:37 PM PST 24 |
Mar 05 02:36:55 PM PST 24 |
3646646435 ps |
| T1356 |
/workspace/coverage/default/42.i2c_host_perf.604132094 |
|
|
Mar 05 02:36:37 PM PST 24 |
Mar 05 02:37:12 PM PST 24 |
1414408734 ps |
| T1357 |
/workspace/coverage/default/16.i2c_target_fifo_reset_tx.1598139295 |
|
|
Mar 05 02:29:55 PM PST 24 |
Mar 05 02:30:09 PM PST 24 |
10263591879 ps |
| T1358 |
/workspace/coverage/default/32.i2c_host_fifo_watermark.1419844804 |
|
|
Mar 05 02:34:03 PM PST 24 |
Mar 05 02:35:55 PM PST 24 |
3899880357 ps |
| T1359 |
/workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3360642815 |
|
|
Mar 05 02:29:40 PM PST 24 |
Mar 05 02:29:42 PM PST 24 |
138417624 ps |
| T1360 |
/workspace/coverage/default/2.i2c_target_bad_addr.4165240084 |
|
|
Mar 05 02:24:43 PM PST 24 |
Mar 05 02:24:50 PM PST 24 |
2986959366 ps |
| T1361 |
/workspace/coverage/default/34.i2c_target_perf.3249506389 |
|
|
Mar 05 02:34:43 PM PST 24 |
Mar 05 02:34:49 PM PST 24 |
4476712652 ps |
| T1362 |
/workspace/coverage/default/40.i2c_host_rx_oversample.2626219539 |
|
|
Mar 05 02:36:01 PM PST 24 |
Mar 05 02:38:45 PM PST 24 |
7864069608 ps |
| T1363 |
/workspace/coverage/default/8.i2c_host_stretch_timeout.1698404895 |
|
|
Mar 05 02:27:03 PM PST 24 |
Mar 05 02:27:18 PM PST 24 |
9970083561 ps |
| T1364 |
/workspace/coverage/default/6.i2c_target_hrst.4024281627 |
|
|
Mar 05 02:26:19 PM PST 24 |
Mar 05 02:26:22 PM PST 24 |
918500798 ps |
| T1365 |
/workspace/coverage/default/18.i2c_target_fifo_reset_tx.3062961331 |
|
|
Mar 05 02:30:27 PM PST 24 |
Mar 05 02:31:29 PM PST 24 |
10028253389 ps |
| T1366 |
/workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2334392044 |
|
|
Mar 05 02:34:45 PM PST 24 |
Mar 05 02:35:08 PM PST 24 |
1845846260 ps |
| T1367 |
/workspace/coverage/default/21.i2c_target_perf.3288973075 |
|
|
Mar 05 02:31:15 PM PST 24 |
Mar 05 02:31:18 PM PST 24 |
3547711964 ps |
| T1368 |
/workspace/coverage/default/31.i2c_target_intr_smoke.2278362581 |
|
|
Mar 05 02:33:56 PM PST 24 |
Mar 05 02:34:03 PM PST 24 |
1290877135 ps |
| T1369 |
/workspace/coverage/default/24.i2c_target_intr_smoke.225610692 |
|
|
Mar 05 02:32:04 PM PST 24 |
Mar 05 02:32:09 PM PST 24 |
1066294794 ps |
| T1370 |
/workspace/coverage/default/32.i2c_target_bad_addr.1317378423 |
|
|
Mar 05 02:34:18 PM PST 24 |
Mar 05 02:34:23 PM PST 24 |
1211011348 ps |
| T1371 |
/workspace/coverage/default/5.i2c_target_stress_wr.2756536482 |
|
|
Mar 05 02:25:52 PM PST 24 |
Mar 05 02:42:09 PM PST 24 |
52898816295 ps |
| T1372 |
/workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2398784899 |
|
|
Mar 05 02:33:38 PM PST 24 |
Mar 05 02:33:39 PM PST 24 |
289844948 ps |
| T1373 |
/workspace/coverage/default/14.i2c_host_mode_toggle.4157548385 |
|
|
Mar 05 02:29:18 PM PST 24 |
Mar 05 02:30:03 PM PST 24 |
9177708627 ps |
| T1374 |
/workspace/coverage/default/20.i2c_target_intr_smoke.2224734487 |
|
|
Mar 05 02:30:54 PM PST 24 |
Mar 05 02:31:00 PM PST 24 |
4198195470 ps |
| T1375 |
/workspace/coverage/default/10.i2c_target_perf.1752464526 |
|
|
Mar 05 02:28:04 PM PST 24 |
Mar 05 02:28:08 PM PST 24 |
1213532457 ps |
| T1376 |
/workspace/coverage/default/49.i2c_host_fifo_watermark.2533420093 |
|
|
Mar 05 02:38:02 PM PST 24 |
Mar 05 02:40:18 PM PST 24 |
26838133205 ps |
| T1377 |
/workspace/coverage/default/38.i2c_target_timeout.936442003 |
|
|
Mar 05 02:35:41 PM PST 24 |
Mar 05 02:35:51 PM PST 24 |
6352232420 ps |
| T1378 |
/workspace/coverage/default/34.i2c_target_fifo_reset_acq.1330598776 |
|
|
Mar 05 02:34:45 PM PST 24 |
Mar 05 02:34:58 PM PST 24 |
10340519338 ps |
| T1379 |
/workspace/coverage/default/23.i2c_host_error_intr.3261434933 |
|
|
Mar 05 02:31:45 PM PST 24 |
Mar 05 02:31:47 PM PST 24 |
41698843 ps |
| T1380 |
/workspace/coverage/default/37.i2c_alert_test.3024393095 |
|
|
Mar 05 02:35:33 PM PST 24 |
Mar 05 02:35:34 PM PST 24 |
17794290 ps |
| T1381 |
/workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2792198924 |
|
|
Mar 05 02:34:46 PM PST 24 |
Mar 05 02:34:48 PM PST 24 |
249024515 ps |
| T1382 |
/workspace/coverage/default/10.i2c_target_hrst.3657897022 |
|
|
Mar 05 02:28:00 PM PST 24 |
Mar 05 02:28:04 PM PST 24 |
697526836 ps |
| T1383 |
/workspace/coverage/default/25.i2c_host_stretch_timeout.420564495 |
|
|
Mar 05 02:32:19 PM PST 24 |
Mar 05 02:32:36 PM PST 24 |
3474706129 ps |
| T1384 |
/workspace/coverage/default/8.i2c_target_bad_addr.3894889807 |
|
|
Mar 05 02:27:11 PM PST 24 |
Mar 05 02:27:15 PM PST 24 |
1995897719 ps |
| T1385 |
/workspace/coverage/default/37.i2c_target_stretch.3979801302 |
|
|
Mar 05 02:35:27 PM PST 24 |
Mar 05 02:35:53 PM PST 24 |
8582155080 ps |
| T1386 |
/workspace/coverage/default/30.i2c_target_unexp_stop.2129669866 |
|
|
Mar 05 02:33:45 PM PST 24 |
Mar 05 02:33:50 PM PST 24 |
3385550232 ps |
| T1387 |
/workspace/coverage/default/40.i2c_host_perf.919903611 |
|
|
Mar 05 02:36:01 PM PST 24 |
Mar 05 02:46:02 PM PST 24 |
13671912219 ps |
| T1388 |
/workspace/coverage/default/8.i2c_host_error_intr.3103448549 |
|
|
Mar 05 02:27:03 PM PST 24 |
Mar 05 02:27:04 PM PST 24 |
61553687 ps |
| T1389 |
/workspace/coverage/default/9.i2c_host_override.3326911899 |
|
|
Mar 05 02:27:21 PM PST 24 |
Mar 05 02:27:22 PM PST 24 |
16222666 ps |
| T1390 |
/workspace/coverage/default/29.i2c_host_override.2078641745 |
|
|
Mar 05 02:33:16 PM PST 24 |
Mar 05 02:33:17 PM PST 24 |
88388870 ps |
| T1391 |
/workspace/coverage/default/5.i2c_target_bad_addr.760987278 |
|
|
Mar 05 02:25:59 PM PST 24 |
Mar 05 02:26:02 PM PST 24 |
610765690 ps |
| T1392 |
/workspace/coverage/default/10.i2c_host_stretch_timeout.853491939 |
|
|
Mar 05 02:27:46 PM PST 24 |
Mar 05 02:28:01 PM PST 24 |
1632094190 ps |
| T1393 |
/workspace/coverage/default/45.i2c_target_intr_stress_wr.3134910917 |
|
|
Mar 05 02:37:20 PM PST 24 |
Mar 05 02:37:25 PM PST 24 |
4023796794 ps |
| T1394 |
/workspace/coverage/default/46.i2c_host_error_intr.3797983506 |
|
|
Mar 05 02:37:28 PM PST 24 |
Mar 05 02:37:29 PM PST 24 |
45954841 ps |
| T1395 |
/workspace/coverage/default/35.i2c_host_fifo_watermark.2627789351 |
|
|
Mar 05 02:34:44 PM PST 24 |
Mar 05 02:38:31 PM PST 24 |
3368657599 ps |
| T1396 |
/workspace/coverage/default/25.i2c_target_hrst.1883641401 |
|
|
Mar 05 02:32:28 PM PST 24 |
Mar 05 02:32:31 PM PST 24 |
683758771 ps |
| T1397 |
/workspace/coverage/default/14.i2c_target_stress_rd.2379321672 |
|
|
Mar 05 02:29:12 PM PST 24 |
Mar 05 02:29:51 PM PST 24 |
2996845208 ps |
| T1398 |
/workspace/coverage/default/42.i2c_alert_test.3021081837 |
|
|
Mar 05 02:36:44 PM PST 24 |
Mar 05 02:36:45 PM PST 24 |
17202319 ps |
| T1399 |
/workspace/coverage/default/2.i2c_target_unexp_stop.2428722987 |
|
|
Mar 05 02:24:38 PM PST 24 |
Mar 05 02:24:45 PM PST 24 |
4727807872 ps |
| T1400 |
/workspace/coverage/default/31.i2c_host_mode_toggle.1985134287 |
|
|
Mar 05 02:34:06 PM PST 24 |
Mar 05 02:35:27 PM PST 24 |
13779474383 ps |
| T1401 |
/workspace/coverage/default/36.i2c_target_fifo_reset_tx.2679448012 |
|
|
Mar 05 02:35:11 PM PST 24 |
Mar 05 02:35:25 PM PST 24 |
10216242827 ps |
| T1402 |
/workspace/coverage/default/13.i2c_target_intr_smoke.1142219983 |
|
|
Mar 05 02:28:53 PM PST 24 |
Mar 05 02:28:57 PM PST 24 |
1114415838 ps |
| T1403 |
/workspace/coverage/default/45.i2c_host_error_intr.2013815997 |
|
|
Mar 05 02:37:14 PM PST 24 |
Mar 05 02:37:17 PM PST 24 |
86342545 ps |
| T1404 |
/workspace/coverage/default/26.i2c_target_fifo_reset_tx.3505879968 |
|
|
Mar 05 02:32:41 PM PST 24 |
Mar 05 02:33:55 PM PST 24 |
10070909139 ps |
| T1405 |
/workspace/coverage/default/28.i2c_host_fifo_fmt_empty.4205843651 |
|
|
Mar 05 02:33:01 PM PST 24 |
Mar 05 02:33:16 PM PST 24 |
1163108583 ps |
| T1406 |
/workspace/coverage/default/43.i2c_target_bad_addr.2601683413 |
|
|
Mar 05 02:36:51 PM PST 24 |
Mar 05 02:36:55 PM PST 24 |
1112738485 ps |
| T1407 |
/workspace/coverage/default/0.i2c_host_smoke.2135861154 |
|
|
Mar 05 02:22:49 PM PST 24 |
Mar 05 02:23:42 PM PST 24 |
3470048528 ps |
| T1408 |
/workspace/coverage/default/13.i2c_target_perf.4282236494 |
|
|
Mar 05 02:28:58 PM PST 24 |
Mar 05 02:29:02 PM PST 24 |
2531358689 ps |
| T1409 |
/workspace/coverage/default/11.i2c_host_fifo_overflow.1557890255 |
|
|
Mar 05 02:28:08 PM PST 24 |
Mar 05 02:29:39 PM PST 24 |
21655016525 ps |
| T1410 |
/workspace/coverage/default/49.i2c_host_override.672071762 |
|
|
Mar 05 02:38:03 PM PST 24 |
Mar 05 02:38:04 PM PST 24 |
16440495 ps |
| T1411 |
/workspace/coverage/default/1.i2c_host_stretch_timeout.2240407387 |
|
|
Mar 05 02:23:52 PM PST 24 |
Mar 05 02:24:40 PM PST 24 |
2181395822 ps |
| T1412 |
/workspace/coverage/default/1.i2c_target_hrst.1477181444 |
|
|
Mar 05 02:24:05 PM PST 24 |
Mar 05 02:24:08 PM PST 24 |
628531106 ps |
| T1413 |
/workspace/coverage/default/34.i2c_host_stretch_timeout.284326171 |
|
|
Mar 05 02:34:38 PM PST 24 |
Mar 05 02:35:06 PM PST 24 |
1517733121 ps |
| T1414 |
/workspace/coverage/default/48.i2c_host_fifo_fmt_empty.964686151 |
|
|
Mar 05 02:37:56 PM PST 24 |
Mar 05 02:38:09 PM PST 24 |
254590417 ps |
| T1415 |
/workspace/coverage/default/33.i2c_target_unexp_stop.751469142 |
|
|
Mar 05 02:34:32 PM PST 24 |
Mar 05 02:34:39 PM PST 24 |
1262978281 ps |
| T1416 |
/workspace/coverage/default/1.i2c_target_fifo_reset_acq.2250518191 |
|
|
Mar 05 02:24:05 PM PST 24 |
Mar 05 02:24:54 PM PST 24 |
10083693718 ps |
| T1417 |
/workspace/coverage/default/37.i2c_target_stress_all.3943555234 |
|
|
Mar 05 02:35:26 PM PST 24 |
Mar 05 02:36:11 PM PST 24 |
38963316952 ps |
| T1418 |
/workspace/coverage/default/17.i2c_host_fifo_reset_rx.2530240451 |
|
|
Mar 05 02:30:03 PM PST 24 |
Mar 05 02:30:07 PM PST 24 |
176428937 ps |
| T1419 |
/workspace/coverage/default/22.i2c_target_stress_rd.3466671638 |
|
|
Mar 05 02:31:28 PM PST 24 |
Mar 05 02:31:41 PM PST 24 |
343082025 ps |
| T1420 |
/workspace/coverage/default/20.i2c_host_stretch_timeout.2302531466 |
|
|
Mar 05 02:30:52 PM PST 24 |
Mar 05 02:31:06 PM PST 24 |
3442987666 ps |
| T1421 |
/workspace/coverage/default/7.i2c_alert_test.909652563 |
|
|
Mar 05 02:26:47 PM PST 24 |
Mar 05 02:26:48 PM PST 24 |
27934152 ps |
| T1422 |
/workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2007309597 |
|
|
Mar 05 02:30:02 PM PST 24 |
Mar 05 02:30:03 PM PST 24 |
80749461 ps |
| T66 |
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.375370809 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:45 PM PST 24 |
32670379 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.229371643 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:42 PM PST 24 |
123524149 ps |
| T68 |
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2603850331 |
|
|
Mar 05 01:28:32 PM PST 24 |
Mar 05 01:28:35 PM PST 24 |
544365544 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.642872908 |
|
|
Mar 05 01:28:32 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
258557907 ps |
| T124 |
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1579401956 |
|
|
Mar 05 01:28:39 PM PST 24 |
Mar 05 01:28:40 PM PST 24 |
26904494 ps |
| T1423 |
/workspace/coverage/cover_reg_top/35.i2c_intr_test.221832444 |
|
|
Mar 05 01:28:53 PM PST 24 |
Mar 05 01:28:54 PM PST 24 |
19548932 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1922077951 |
|
|
Mar 05 01:28:48 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
55883851 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2894351718 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:32 PM PST 24 |
56814422 ps |
| T190 |
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.699770372 |
|
|
Mar 05 01:28:19 PM PST 24 |
Mar 05 01:28:20 PM PST 24 |
42056042 ps |
| T127 |
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2457347990 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
82981068 ps |
| T1424 |
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1468039427 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:27:54 PM PST 24 |
19295335 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3759902691 |
|
|
Mar 05 01:28:41 PM PST 24 |
Mar 05 01:28:42 PM PST 24 |
141389171 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1342795945 |
|
|
Mar 05 01:28:19 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
298708375 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.210152492 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
174411504 ps |
| T1425 |
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1709894074 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:28:57 PM PST 24 |
18204996 ps |
| T1426 |
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2959100922 |
|
|
Mar 05 01:28:09 PM PST 24 |
Mar 05 01:28:10 PM PST 24 |
16065487 ps |
| T70 |
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.610667955 |
|
|
Mar 05 01:27:52 PM PST 24 |
Mar 05 01:27:55 PM PST 24 |
111216951 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3500796720 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
36668543 ps |
| T80 |
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2307973387 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:36 PM PST 24 |
461734103 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1771705938 |
|
|
Mar 05 01:28:26 PM PST 24 |
Mar 05 01:28:29 PM PST 24 |
32281838 ps |
| T1427 |
/workspace/coverage/cover_reg_top/40.i2c_intr_test.3625001159 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
36679233 ps |
| T1428 |
/workspace/coverage/cover_reg_top/45.i2c_intr_test.4260758993 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
36050858 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.464407552 |
|
|
Mar 05 01:28:28 PM PST 24 |
Mar 05 01:28:29 PM PST 24 |
79264214 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1052808657 |
|
|
Mar 05 01:28:01 PM PST 24 |
Mar 05 01:28:03 PM PST 24 |
152007993 ps |
| T1429 |
/workspace/coverage/cover_reg_top/21.i2c_intr_test.2878453659 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
16804565 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4199419949 |
|
|
Mar 05 01:28:21 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
299168223 ps |
| T1430 |
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2093594311 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
18328596 ps |
| T1431 |
/workspace/coverage/cover_reg_top/8.i2c_intr_test.1630523175 |
|
|
Mar 05 01:28:27 PM PST 24 |
Mar 05 01:28:28 PM PST 24 |
23412583 ps |
| T1432 |
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.101684050 |
|
|
Mar 05 01:28:10 PM PST 24 |
Mar 05 01:28:15 PM PST 24 |
1261138411 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3963864233 |
|
|
Mar 05 01:28:20 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
19433501 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2359032484 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
39807337 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2902001707 |
|
|
Mar 05 01:28:26 PM PST 24 |
Mar 05 01:28:27 PM PST 24 |
39188043 ps |
| T1433 |
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2140092849 |
|
|
Mar 05 01:27:58 PM PST 24 |
Mar 05 01:28:00 PM PST 24 |
69718506 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.950207136 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
60579747 ps |
| T131 |
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3298171643 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
54478490 ps |
| T132 |
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1415623800 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:41 PM PST 24 |
325977875 ps |
| T1434 |
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1776740974 |
|
|
Mar 05 01:28:09 PM PST 24 |
Mar 05 01:28:10 PM PST 24 |
37042627 ps |
| T1435 |
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.4153241636 |
|
|
Mar 05 01:28:44 PM PST 24 |
Mar 05 01:28:46 PM PST 24 |
29514396 ps |
| T1436 |
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4072978369 |
|
|
Mar 05 01:28:26 PM PST 24 |
Mar 05 01:28:28 PM PST 24 |
119711698 ps |
| T207 |
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1949424392 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:20 PM PST 24 |
2000901646 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2070590634 |
|
|
Mar 05 01:28:42 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
41496607 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.415969663 |
|
|
Mar 05 01:28:01 PM PST 24 |
Mar 05 01:28:03 PM PST 24 |
332587208 ps |
| T79 |
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2294451252 |
|
|
Mar 05 01:28:27 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
222767062 ps |
| T1437 |
/workspace/coverage/cover_reg_top/1.i2c_intr_test.3500205388 |
|
|
Mar 05 01:27:59 PM PST 24 |
Mar 05 01:28:00 PM PST 24 |
19098373 ps |
| T1438 |
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1407308101 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:41 PM PST 24 |
50713072 ps |
| T1439 |
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3842555281 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:10 PM PST 24 |
233326979 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2696327434 |
|
|
Mar 05 01:28:29 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
106778577 ps |
| T1440 |
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3582134872 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:44 PM PST 24 |
23270461 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.863726659 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:42 PM PST 24 |
126224632 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.124245744 |
|
|
Mar 05 01:28:07 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
109316419 ps |
| T1441 |
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.449927409 |
|
|
Mar 05 01:28:21 PM PST 24 |
Mar 05 01:28:23 PM PST 24 |
44157437 ps |
| T1442 |
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2433032075 |
|
|
Mar 05 01:28:37 PM PST 24 |
Mar 05 01:28:38 PM PST 24 |
51522760 ps |
| T1443 |
/workspace/coverage/cover_reg_top/11.i2c_intr_test.2541203673 |
|
|
Mar 05 01:28:37 PM PST 24 |
Mar 05 01:28:38 PM PST 24 |
18525686 ps |
| T1444 |
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3703092141 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:28:57 PM PST 24 |
24351842 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4149009602 |
|
|
Mar 05 01:28:06 PM PST 24 |
Mar 05 01:28:07 PM PST 24 |
26609746 ps |
| T1445 |
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2162190380 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
42890404 ps |
| T1446 |
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.201983106 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
125714920 ps |
| T1447 |
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4163710888 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:35 PM PST 24 |
49167986 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2539773967 |
|
|
Mar 05 01:28:20 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
894454785 ps |
| T1448 |
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2360170281 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:32 PM PST 24 |
48167359 ps |
| T1449 |
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.3420582476 |
|
|
Mar 05 01:28:09 PM PST 24 |
Mar 05 01:28:10 PM PST 24 |
158469571 ps |
| T1450 |
/workspace/coverage/cover_reg_top/48.i2c_intr_test.2987327389 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
19578093 ps |
| T1451 |
/workspace/coverage/cover_reg_top/30.i2c_intr_test.1562114983 |
|
|
Mar 05 01:28:48 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
52645987 ps |
| T1452 |
/workspace/coverage/cover_reg_top/33.i2c_intr_test.2675769884 |
|
|
Mar 05 01:28:53 PM PST 24 |
Mar 05 01:28:54 PM PST 24 |
49171252 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3340409931 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:37 PM PST 24 |
139803695 ps |
| T1453 |
/workspace/coverage/cover_reg_top/25.i2c_intr_test.2097464933 |
|
|
Mar 05 01:28:48 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
45523546 ps |
| T88 |
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3683838267 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:42 PM PST 24 |
119979177 ps |
| T1454 |
/workspace/coverage/cover_reg_top/34.i2c_intr_test.583481186 |
|
|
Mar 05 01:28:48 PM PST 24 |
Mar 05 01:28:48 PM PST 24 |
53724349 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.208699884 |
|
|
Mar 05 01:28:00 PM PST 24 |
Mar 05 01:28:01 PM PST 24 |
25867171 ps |
| T1455 |
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4136768356 |
|
|
Mar 05 01:28:26 PM PST 24 |
Mar 05 01:28:27 PM PST 24 |
22609394 ps |
| T176 |
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2216832287 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
54134578 ps |
| T1456 |
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.783549583 |
|
|
Mar 05 01:28:33 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
46398209 ps |
| T94 |
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2347408175 |
|
|
Mar 05 01:28:37 PM PST 24 |
Mar 05 01:28:39 PM PST 24 |
271622959 ps |
| T1457 |
/workspace/coverage/cover_reg_top/23.i2c_intr_test.999825126 |
|
|
Mar 05 01:28:46 PM PST 24 |
Mar 05 01:28:47 PM PST 24 |
20614324 ps |
| T1458 |
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1329322660 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
40465633 ps |
| T1459 |
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3825749481 |
|
|
Mar 05 01:28:58 PM PST 24 |
Mar 05 01:28:59 PM PST 24 |
80406298 ps |
| T1460 |
/workspace/coverage/cover_reg_top/37.i2c_intr_test.3786807823 |
|
|
Mar 05 01:28:53 PM PST 24 |
Mar 05 01:28:54 PM PST 24 |
17911838 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3768949156 |
|
|
Mar 05 01:28:09 PM PST 24 |
Mar 05 01:28:11 PM PST 24 |
149110483 ps |
| T1461 |
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.98817160 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:12 PM PST 24 |
395131277 ps |
| T1462 |
/workspace/coverage/cover_reg_top/12.i2c_intr_test.4110153735 |
|
|
Mar 05 01:28:35 PM PST 24 |
Mar 05 01:28:36 PM PST 24 |
19794445 ps |
| T84 |
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.499605276 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
409648868 ps |
| T1463 |
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3137778497 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:44 PM PST 24 |
97321176 ps |
| T1464 |
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1350168506 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:34 PM PST 24 |
632704586 ps |
| T1465 |
/workspace/coverage/cover_reg_top/27.i2c_intr_test.2754747412 |
|
|
Mar 05 01:28:48 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
16372870 ps |
| T1466 |
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.13656998 |
|
|
Mar 05 01:27:59 PM PST 24 |
Mar 05 01:28:01 PM PST 24 |
154975753 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1356509088 |
|
|
Mar 05 01:28:29 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
173553001 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2837702367 |
|
|
Mar 05 01:28:34 PM PST 24 |
Mar 05 01:28:35 PM PST 24 |
19834622 ps |
| T1467 |
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3202890899 |
|
|
Mar 05 01:28:39 PM PST 24 |
Mar 05 01:28:40 PM PST 24 |
74213304 ps |
| T1468 |
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2219007667 |
|
|
Mar 05 01:27:54 PM PST 24 |
Mar 05 01:27:55 PM PST 24 |
32188667 ps |
| T1469 |
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2164129982 |
|
|
Mar 05 01:28:32 PM PST 24 |
Mar 05 01:28:33 PM PST 24 |
18704783 ps |
| T1470 |
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3967452476 |
|
|
Mar 05 01:28:20 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
103523213 ps |
| T1471 |
/workspace/coverage/cover_reg_top/32.i2c_intr_test.2343413143 |
|
|
Mar 05 01:28:50 PM PST 24 |
Mar 05 01:28:51 PM PST 24 |
64574696 ps |
| T1472 |
/workspace/coverage/cover_reg_top/26.i2c_intr_test.115782100 |
|
|
Mar 05 01:28:52 PM PST 24 |
Mar 05 01:28:53 PM PST 24 |
22255968 ps |
| T1473 |
/workspace/coverage/cover_reg_top/9.i2c_intr_test.1618325847 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:32 PM PST 24 |
48258119 ps |
| T1474 |
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1372829317 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:33 PM PST 24 |
24093942 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.893405351 |
|
|
Mar 05 01:28:10 PM PST 24 |
Mar 05 01:28:15 PM PST 24 |
107480008 ps |
| T1475 |
/workspace/coverage/cover_reg_top/10.i2c_intr_test.2524612237 |
|
|
Mar 05 01:28:31 PM PST 24 |
Mar 05 01:28:32 PM PST 24 |
17104230 ps |
| T1476 |
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.3044368860 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:41 PM PST 24 |
66176816 ps |
| T1477 |
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3541144404 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
108810348 ps |
| T1478 |
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2555125814 |
|
|
Mar 05 01:28:50 PM PST 24 |
Mar 05 01:28:51 PM PST 24 |
55341445 ps |
| T1479 |
/workspace/coverage/cover_reg_top/18.i2c_intr_test.2026703129 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:44 PM PST 24 |
33147459 ps |
| T1480 |
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.452205430 |
|
|
Mar 05 01:27:55 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
64469437 ps |
| T1481 |
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1992213450 |
|
|
Mar 05 01:28:17 PM PST 24 |
Mar 05 01:28:18 PM PST 24 |
37246786 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3164843630 |
|
|
Mar 05 01:28:26 PM PST 24 |
Mar 05 01:28:28 PM PST 24 |
506758396 ps |
| T83 |
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2500440642 |
|
|
Mar 05 01:28:20 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
111855267 ps |
| T1482 |
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.985893590 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:41 PM PST 24 |
32641482 ps |
| T1483 |
/workspace/coverage/cover_reg_top/28.i2c_intr_test.790039498 |
|
|
Mar 05 01:28:50 PM PST 24 |
Mar 05 01:28:51 PM PST 24 |
132939176 ps |
| T1484 |
/workspace/coverage/cover_reg_top/7.i2c_intr_test.3593426372 |
|
|
Mar 05 01:28:25 PM PST 24 |
Mar 05 01:28:27 PM PST 24 |
27664818 ps |
| T1485 |
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.2826047965 |
|
|
Mar 05 01:28:28 PM PST 24 |
Mar 05 01:28:29 PM PST 24 |
78090057 ps |
| T1486 |
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1085248753 |
|
|
Mar 05 01:28:17 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
519726198 ps |
| T1487 |
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4286198424 |
|
|
Mar 05 01:28:19 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
77476938 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1928993238 |
|
|
Mar 05 01:28:01 PM PST 24 |
Mar 05 01:28:04 PM PST 24 |
1405991987 ps |
| T1488 |
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1582144660 |
|
|
Mar 05 01:28:42 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
58129900 ps |
| T1489 |
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1999018184 |
|
|
Mar 05 01:28:43 PM PST 24 |
Mar 05 01:28:44 PM PST 24 |
58859175 ps |
| T1490 |
/workspace/coverage/cover_reg_top/29.i2c_intr_test.1326381681 |
|
|
Mar 05 01:28:53 PM PST 24 |
Mar 05 01:28:55 PM PST 24 |
35283705 ps |
| T1491 |
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3464097033 |
|
|
Mar 05 01:28:07 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
94012530 ps |
| T1492 |
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3526567624 |
|
|
Mar 05 01:28:09 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
19793954 ps |
| T1493 |
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3959213824 |
|
|
Mar 05 01:28:08 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
28399201 ps |
| T117 |
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.3901351330 |
|
|
Mar 05 01:28:40 PM PST 24 |
Mar 05 01:28:41 PM PST 24 |
24789305 ps |
| T1494 |
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.967943862 |
|
|
Mar 05 01:28:49 PM PST 24 |
Mar 05 01:28:50 PM PST 24 |
44629310 ps |
| T1495 |
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3274546597 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
47972651 ps |
| T1496 |
/workspace/coverage/cover_reg_top/31.i2c_intr_test.2203219989 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
28560829 ps |
| T1497 |
/workspace/coverage/cover_reg_top/6.i2c_intr_test.2781040243 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
48049671 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2053735136 |
|
|
Mar 05 01:28:02 PM PST 24 |
Mar 05 01:28:03 PM PST 24 |
23886943 ps |
| T1498 |
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3983976298 |
|
|
Mar 05 01:28:17 PM PST 24 |
Mar 05 01:28:18 PM PST 24 |
31453545 ps |
| T1499 |
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2040999960 |
|
|
Mar 05 01:28:45 PM PST 24 |
Mar 05 01:28:46 PM PST 24 |
37454947 ps |
| T1500 |
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2308655270 |
|
|
Mar 05 01:27:54 PM PST 24 |
Mar 05 01:27:55 PM PST 24 |
19814861 ps |
| T1501 |
/workspace/coverage/cover_reg_top/38.i2c_intr_test.1311709281 |
|
|
Mar 05 01:28:49 PM PST 24 |
Mar 05 01:28:50 PM PST 24 |
20830213 ps |
| T197 |
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2254023136 |
|
|
Mar 05 01:28:27 PM PST 24 |
Mar 05 01:28:29 PM PST 24 |
65386527 ps |
| T1502 |
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1836911712 |
|
|
Mar 05 01:28:20 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
57096201 ps |
| T1503 |
/workspace/coverage/cover_reg_top/4.i2c_intr_test.4133799430 |
|
|
Mar 05 01:28:18 PM PST 24 |
Mar 05 01:28:19 PM PST 24 |
26329802 ps |
| T1504 |
/workspace/coverage/cover_reg_top/22.i2c_intr_test.2980871032 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:56 PM PST 24 |
31817290 ps |