Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7123923	1			T1	18741		T2	16		T3	3
all_values[1]	7123923	1			T1	18741		T2	16		T3	3
all_values[2]	7123923	1			T1	18741		T2	16		T3	3
all_values[3]	7123923	1			T1	18741		T2	16		T3	3
all_values[4]	7123923	1			T1	18741		T2	16		T3	3
all_values[5]	7123923	1			T1	18741		T2	16		T3	3
all_values[6]	7123923	1			T1	18741		T2	16		T3	3
all_values[7]	7123923	1			T1	18741		T2	16		T3	3
all_values[8]	7123923	1			T1	18741		T2	16		T3	3
all_values[9]	7123923	1			T1	18741		T2	16		T3	3
all_values[10]	7123923	1			T1	18741		T2	16		T3	3
all_values[11]	7123923	1			T1	18741		T2	16		T3	3
all_values[12]	7123923	1			T1	18741		T2	16		T3	3
all_values[13]	7123923	1			T1	18741		T2	16		T3	3
all_values[14]	7123923	1			T1	18741		T2	16		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90905749

1

T1

244320

T2

208

T3

40

auto[1]

15953096

1

T1

36795

T2

32

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94379328

1

T1

281115

T2

240

T3

45

auto[1]

12479517

1

T14

42461

T47

102112

T51

181336

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1176700	1			T1	2919		T11	41		T12	6652
all_values[0]	auto[0]	auto[1]	160988	1			T14	19		T47	432		T51	546
all_values[0]	auto[1]	auto[0]	5408746	1			T1	15822		T2	16		T3	3
all_values[0]	auto[1]	auto[1]	377489	1			T14	2812		T47	6861		T51	11544
all_values[1]	auto[0]	auto[0]	6252600	1			T1	18741		T2	16		T3	3
all_values[1]	auto[0]	auto[1]	869123	1			T14	2828		T47	7250		T51	12081
all_values[1]	auto[1]	auto[0]	1729	1			T12	62		T55	61		T57	33
all_values[1]	auto[1]	auto[1]	471	1			T14	3		T47	43		T51	9
all_values[2]	auto[0]	auto[0]	6243255	1			T1	18741		T2	16		T3	3
all_values[2]	auto[0]	auto[1]	880470	1			T14	2828		T47	7283		T51	12084
all_values[2]	auto[1]	auto[1]	198	1			T14	4		T47	8		T51	6
all_values[3]	auto[0]	auto[0]	6254327	1			T1	18741		T2	16		T3	3
all_values[3]	auto[0]	auto[1]	869359	1			T14	2826		T47	7285		T51	12085
all_values[3]	auto[1]	auto[1]	237	1			T14	4		T47	7		T51	4
all_values[4]	auto[0]	auto[0]	6242214	1			T1	18741		T2	16		T3	3
all_values[4]	auto[0]	auto[1]	881441	1			T14	2827		T47	7287		T51	12086
all_values[4]	auto[1]	auto[0]	28	1			T31	1		T203	1		T204	26
all_values[4]	auto[1]	auto[1]	240	1			T14	5		T47	6		T51	4
all_values[5]	auto[0]	auto[0]	6273544	1			T1	18741		T2	16		T3	3
all_values[5]	auto[0]	auto[1]	850161	1			T14	2826		T47	7286		T51	12083
all_values[5]	auto[1]	auto[1]	218	1			T14	4		T47	7		T51	6
all_values[6]	auto[0]	auto[0]	5532076	1			T1	18710		T2	16		T3	3
all_values[6]	auto[0]	auto[1]	751514	1			T14	2823		T47	14		T51	6452
all_values[6]	auto[1]	auto[0]	717446	1			T1	31		T11	1		T12	8363
all_values[6]	auto[1]	auto[1]	122887	1			T14	7		T47	9		T51	5637
all_values[7]	auto[0]	auto[0]	5917621	1			T1	17073		T2	16		T3	3
all_values[7]	auto[0]	auto[1]	852529	1			T14	2670		T47	6516		T51	10203
all_values[7]	auto[1]	auto[0]	317785	1			T1	1668		T11	18		T12	1716
all_values[7]	auto[1]	auto[1]	35988	1			T14	158		T47	776		T51	1886
all_values[8]	auto[0]	auto[0]	5342544	1			T1	18231		T2	16		T3	3
all_values[8]	auto[0]	auto[1]	746242	1			T14	2811		T47	6908		T51	6277
all_values[8]	auto[1]	auto[0]	902365	1			T1	510		T11	50		T12	9595
all_values[8]	auto[1]	auto[1]	132772	1			T14	20		T47	384		T51	5812
all_values[9]	auto[0]	auto[0]	5549714	1			T1	18713		T2	16		T3	2
all_values[9]	auto[0]	auto[1]	760757	1			T14	2824		T47	7240		T51	6848
all_values[9]	auto[1]	auto[0]	693526	1			T1	28		T3	1		T11	5
all_values[9]	auto[1]	auto[1]	119926	1			T14	8		T47	53		T51	5241
all_values[10]	auto[0]	auto[0]	6235418	1			T1	18741		T2	16		T3	3
all_values[10]	auto[0]	auto[1]	888283	1			T14	2829		T47	7283		T51	12087
all_values[10]	auto[1]	auto[1]	222	1			T14	2		T47	9		T51	3
all_values[11]	auto[0]	auto[0]	3221	1			T1	5		T3	2		T7	1
all_values[11]	auto[0]	auto[1]	571	1			T14	17		T47	29		T51	9
all_values[11]	auto[1]	auto[0]	6241088	1			T1	18736		T2	16		T3	1
all_values[11]	auto[1]	auto[1]	879043	1			T14	2814		T47	7260		T51	12078
all_values[12]	auto[0]	auto[0]	6242110	1			T1	18741		T2	16		T3	3
all_values[12]	auto[0]	auto[1]	881606	1			T14	2828		T47	7280		T51	12086
all_values[12]	auto[1]	auto[1]	207	1			T14	4		T47	13		T51	1
all_values[13]	auto[0]	auto[0]	6584167	1			T1	18741		T2	16		T3	3
all_values[13]	auto[0]	auto[1]	539513	1			T14	2827		T47	7279		T51	12085
all_values[13]	auto[1]	auto[0]	8	1			T205	1		T206	1		T207	1
all_values[13]	auto[1]	auto[1]	235	1			T14	2		T47	12		T51	3
all_values[14]	auto[0]	auto[0]	6247096	1			T1	18741		T2	16		T3	3
all_values[14]	auto[0]	auto[1]	876585	1			T14	2828		T47	7283		T51	12086
all_values[14]	auto[1]	auto[1]	242	1			T14	3		T47	9		T51	4