Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7123923	1			T1	18741		T2	16		T3	3
all_pins[1]	7123923	1			T1	18741		T2	16		T3	3
all_pins[2]	7123923	1			T1	18741		T2	16		T3	3
all_pins[3]	7123923	1			T1	18741		T2	16		T3	3
all_pins[4]	7123923	1			T1	18741		T2	16		T3	3
all_pins[5]	7123923	1			T1	18741		T2	16		T3	3
all_pins[6]	7123923	1			T1	18741		T2	16		T3	3
all_pins[7]	7123923	1			T1	18741		T2	16		T3	3
all_pins[8]	7123923	1			T1	18741		T2	16		T3	3
all_pins[9]	7123923	1			T1	18741		T2	16		T3	3
all_pins[10]	7123923	1			T1	18741		T2	16		T3	3
all_pins[11]	7123923	1			T1	18741		T2	16		T3	3
all_pins[12]	7123923	1			T1	18741		T2	16		T3	3
all_pins[13]	7123923	1			T1	18741		T2	16		T3	3
all_pins[14]	7123923	1			T1	18741		T2	16		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	90834635	1			T1	244027		T2	208		T3	40
values[0x1]	16024210	1			T1	37088		T2	32		T3	5
transitions[0x0=>0x1]	15118730	1			T1	37033		T2	32		T3	5
transitions[0x1=>0x0]	15117597	1			T1	37032		T2	31		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1337862	1			T1	2919		T11	41		T12	6651
all_pins[0]	values[0x1]	5786061	1			T1	15822		T2	16		T3	3
all_pins[0]	transitions[0x0=>0x1]	5783862	1			T1	15822		T2	16		T3	3
all_pins[0]	transitions[0x1=>0x0]	229	1			T14	2		T47	3		T51	1
all_pins[1]	values[0x0]	7121495	1			T1	18741		T2	16		T3	3
all_pins[1]	values[0x1]	2428	1			T12	65		T14	2		T55	67
all_pins[1]	transitions[0x0=>0x1]	2402	1			T12	65		T14	2		T55	67
all_pins[1]	transitions[0x1=>0x0]	70	1			T14	2		T47	2		T51	3
all_pins[2]	values[0x0]	7123827	1			T1	18741		T2	16		T3	3
all_pins[2]	values[0x1]	96	1			T14	2		T47	3		T51	3
all_pins[2]	transitions[0x0=>0x1]	75	1			T14	2		T47	3		T51	3
all_pins[2]	transitions[0x1=>0x0]	96	1			T14	3		T47	3		T51	2
all_pins[3]	values[0x0]	7123806	1			T1	18741		T2	16		T3	3
all_pins[3]	values[0x1]	117	1			T14	3		T47	3		T51	2
all_pins[3]	transitions[0x0=>0x1]	85	1			T14	3		T47	3		T51	2
all_pins[3]	transitions[0x1=>0x0]	129	1			T14	3		T47	3		T51	1
all_pins[4]	values[0x0]	7123762	1			T1	18741		T2	16		T3	3
all_pins[4]	values[0x1]	161	1			T14	3		T47	3		T51	1
all_pins[4]	transitions[0x0=>0x1]	120	1			T14	3		T47	3		T51	1
all_pins[4]	transitions[0x1=>0x0]	64	1			T14	1		T47	3		T51	2
all_pins[5]	values[0x0]	7123818	1			T1	18741		T2	16		T3	3
all_pins[5]	values[0x1]	105	1			T14	1		T47	3		T51	2
all_pins[5]	transitions[0x0=>0x1]	77	1			T47	3		T51	1		T120	1
all_pins[5]	transitions[0x1=>0x0]	843800	1			T1	32		T11	2		T12	8364
all_pins[6]	values[0x0]	6280095	1			T1	18709		T2	16		T3	3
all_pins[6]	values[0x1]	843828	1			T1	32		T11	2		T12	8364
all_pins[6]	transitions[0x0=>0x1]	817689	1			T1	30		T11	1		T12	8115
all_pins[6]	transitions[0x1=>0x0]	369465	1			T1	1875		T11	20		T12	1559
all_pins[7]	values[0x0]	6728319	1			T1	16864		T2	16		T3	3
all_pins[7]	values[0x1]	395604	1			T1	1877		T11	21		T12	1808
all_pins[7]	transitions[0x0=>0x1]	323770	1			T1	1824		T11	16		T12	1301
all_pins[7]	transitions[0x1=>0x0]	989293	1			T1	536		T11	55		T12	9112
all_pins[8]	values[0x0]	6062796	1			T1	18152		T2	16		T3	3
all_pins[8]	values[0x1]	1061127	1			T1	589		T11	60		T12	9619
all_pins[8]	transitions[0x0=>0x1]	256137	1			T1	589		T11	60		T12	630
all_pins[8]	transitions[0x1=>0x0]	9267	1			T1	32		T3	1		T11	5
all_pins[9]	values[0x0]	6309666	1			T1	18709		T2	16		T3	2
all_pins[9]	values[0x1]	814257	1			T1	32		T3	1		T11	5
all_pins[9]	transitions[0x0=>0x1]	814230	1			T1	32		T3	1		T11	5
all_pins[9]	transitions[0x1=>0x0]	81	1			T14	1		T47	3		T172	2
all_pins[10]	values[0x0]	7123815	1			T1	18741		T2	16		T3	3
all_pins[10]	values[0x1]	108	1			T14	1		T47	5		T51	1
all_pins[10]	transitions[0x0=>0x1]	75	1			T14	1		T47	4		T51	1
all_pins[10]	transitions[0x1=>0x0]	7119939	1			T1	18736		T2	16		T3	1
all_pins[11]	values[0x0]	3951	1			T1	5		T3	2		T7	1
all_pins[11]	values[0x1]	7119972	1			T1	18736		T2	16		T3	1
all_pins[11]	transitions[0x0=>0x1]	7119951	1			T1	18736		T2	16		T3	1
all_pins[11]	transitions[0x1=>0x0]	74	1			T47	7		T120	2		T119	3
all_pins[12]	values[0x0]	7123828	1			T1	18741		T2	16		T3	3
all_pins[12]	values[0x1]	95	1			T47	7		T120	2		T119	3
all_pins[12]	transitions[0x0=>0x1]	79	1			T47	5		T120	2		T119	1
all_pins[12]	transitions[0x1=>0x0]	106	1			T47	5		T51	3		T119	1
all_pins[13]	values[0x0]	7123801	1			T1	18741		T2	16		T3	3
all_pins[13]	values[0x1]	122	1			T47	7		T51	3		T119	3
all_pins[13]	transitions[0x0=>0x1]	91	1			T47	6		T51	2		T119	3
all_pins[13]	transitions[0x1=>0x0]	98	1			T14	2		T47	2		T51	1
all_pins[14]	values[0x0]	7123794	1			T1	18741		T2	16		T3	3
all_pins[14]	values[0x1]	129	1			T14	2		T47	3		T51	2
all_pins[14]	transitions[0x0=>0x1]	87	1			T14	2		T47	2		T51	2
all_pins[14]	transitions[0x1=>0x0]	5784886	1			T1	15821		T2	15		T3	2