Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	515	1			T14	7		T47	21		T51	7
all_values[1]	515	1			T14	7		T47	21		T51	7
all_values[2]	515	1			T14	7		T47	21		T51	7
all_values[3]	515	1			T14	7		T47	21		T51	7
all_values[4]	515	1			T14	7		T47	21		T51	7
all_values[5]	515	1			T14	7		T47	21		T51	7
all_values[6]	515	1			T14	7		T47	21		T51	7
all_values[7]	515	1			T14	7		T47	21		T51	7
all_values[8]	515	1			T14	7		T47	21		T51	7
all_values[9]	515	1			T14	7		T47	21		T51	7
all_values[10]	515	1			T14	7		T47	21		T51	7
all_values[11]	515	1			T14	7		T47	21		T51	7
all_values[12]	515	1			T14	7		T47	21		T51	7
all_values[13]	515	1			T14	7		T47	21		T51	7
all_values[14]	515	1			T14	7		T47	21		T51	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4137

1

T14

60

T47

162

T51

57

auto[1]

3588

1

T14

45

T47

153

T51

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T14

19

T47

20

T51

14

auto[1]

6549

1

T14

86

T47

295

T51

91

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4580

1

T14

64

T47

178

T51

56

auto[1]

3145

1

T14

41

T47

137

T51

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	55	1			T119	1		T172	1		T224	3
all_values[0]	auto[0]	auto[0]	auto[1]	105	1			T14	2		T47	3		T51	2
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T14	1		T172	1		T190	1
all_values[0]	auto[0]	auto[1]	auto[1]	129	1			T14	3		T47	9		T51	2
all_values[0]	auto[1]	auto[0]	auto[1]	111	1			T14	1		T47	3		T51	2
all_values[0]	auto[1]	auto[1]	auto[1]	87	1			T47	6		T51	1		T172	1
all_values[1]	auto[0]	auto[0]	auto[0]	49	1			T14	1		T120	1		T172	1
all_values[1]	auto[0]	auto[0]	auto[1]	123	1			T14	1		T47	4		T51	2
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T225	3		T190	2		T224	4
all_values[1]	auto[0]	auto[1]	auto[1]	105	1			T14	2		T47	10		T51	2
all_values[1]	auto[1]	auto[0]	auto[1]	106	1			T14	1		T47	4		T51	2
all_values[1]	auto[1]	auto[1]	auto[1]	106	1			T14	2		T47	3		T51	1
all_values[2]	auto[0]	auto[0]	auto[0]	52	1			T47	1		T120	2		T225	1
all_values[2]	auto[0]	auto[0]	auto[1]	114	1			T14	1		T47	2		T51	1
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T47	1		T190	1		T143	2
all_values[2]	auto[0]	auto[1]	auto[1]	120	1			T14	2		T47	9		T119	1
all_values[2]	auto[1]	auto[0]	auto[1]	101	1			T14	3		T47	5		T51	3
all_values[2]	auto[1]	auto[1]	auto[1]	97	1			T14	1		T47	3		T51	3
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T14	2		T47	1		T120	1
all_values[3]	auto[0]	auto[0]	auto[1]	118	1			T47	8		T51	2		T120	1
all_values[3]	auto[0]	auto[1]	auto[0]	27	1			T51	1		T172	2		T225	3
all_values[3]	auto[0]	auto[1]	auto[1]	110	1			T14	1		T47	5		T51	2
all_values[3]	auto[1]	auto[0]	auto[1]	121	1			T14	2		T47	2		T51	1
all_values[3]	auto[1]	auto[1]	auto[1]	94	1			T14	2		T47	5		T51	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T120	1		T225	1		T224	1
all_values[4]	auto[0]	auto[0]	auto[1]	125	1			T14	3		T47	7		T51	2
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T119	2		T31	1		T141	2
all_values[4]	auto[0]	auto[1]	auto[1]	102	1			T14	1		T47	4		T51	2
all_values[4]	auto[1]	auto[0]	auto[1]	103	1			T47	6		T51	2		T172	1
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T14	3		T47	4		T51	1
all_values[5]	auto[0]	auto[0]	auto[0]	47	1			T14	1		T119	1		T225	4
all_values[5]	auto[0]	auto[0]	auto[1]	95	1			T14	1		T47	3		T51	2
all_values[5]	auto[0]	auto[1]	auto[0]	52	1			T14	1		T51	1		T120	1
all_values[5]	auto[0]	auto[1]	auto[1]	130	1			T14	1		T47	8		T51	2
all_values[5]	auto[1]	auto[0]	auto[1]	114	1			T14	2		T47	7		T51	1
all_values[5]	auto[1]	auto[1]	auto[1]	77	1			T14	1		T47	3		T51	1
all_values[6]	auto[0]	auto[0]	auto[0]	55	1			T14	2		T47	7		T51	1
all_values[6]	auto[0]	auto[0]	auto[1]	125	1			T14	2		T47	4		T119	2
all_values[6]	auto[0]	auto[1]	auto[0]	28	1			T120	1		T225	1		T190	1
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T14	1		T47	5		T51	1
all_values[6]	auto[1]	auto[0]	auto[1]	108	1			T14	1		T47	2		T51	2
all_values[6]	auto[1]	auto[1]	auto[1]	102	1			T14	1		T47	3		T51	3
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T14	1		T47	1		T51	1
all_values[7]	auto[0]	auto[0]	auto[1]	125	1			T47	6		T51	1		T120	1
all_values[7]	auto[0]	auto[1]	auto[0]	22	1			T14	3		T172	1		T144	1
all_values[7]	auto[0]	auto[1]	auto[1]	113	1			T14	1		T47	5		T51	2
all_values[7]	auto[1]	auto[0]	auto[1]	107	1			T14	2		T47	7		T51	2
all_values[7]	auto[1]	auto[1]	auto[1]	103	1			T47	2		T51	1		T119	2
all_values[8]	auto[0]	auto[0]	auto[0]	42	1			T47	1		T51	1		T172	1
all_values[8]	auto[0]	auto[0]	auto[1]	113	1			T14	2		T47	3		T51	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T14	1		T120	1		T141	2
all_values[8]	auto[0]	auto[1]	auto[1]	122	1			T14	1		T47	6		T120	1
all_values[8]	auto[1]	auto[0]	auto[1]	105	1			T14	3		T47	6		T51	4
all_values[8]	auto[1]	auto[1]	auto[1]	108	1			T47	5		T119	1		T225	4
all_values[9]	auto[0]	auto[0]	auto[0]	47	1			T120	1		T119	2		T225	1
all_values[9]	auto[0]	auto[0]	auto[1]	128	1			T14	3		T47	2		T51	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T51	1		T225	1		T31	2
all_values[9]	auto[0]	auto[1]	auto[1]	101	1			T14	1		T47	7		T120	1
all_values[9]	auto[1]	auto[0]	auto[1]	118	1			T14	2		T47	7		T51	1
all_values[9]	auto[1]	auto[1]	auto[1]	94	1			T14	1		T47	5		T51	4
all_values[10]	auto[0]	auto[0]	auto[0]	47	1			T14	1		T47	1		T120	1
all_values[10]	auto[0]	auto[0]	auto[1]	116	1			T14	1		T47	7		T51	2
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T120	1		T190	1		T141	1
all_values[10]	auto[0]	auto[1]	auto[1]	101	1			T14	3		T47	4		T51	2
all_values[10]	auto[1]	auto[0]	auto[1]	109	1			T47	4		T51	2		T119	3
all_values[10]	auto[1]	auto[1]	auto[1]	113	1			T14	2		T47	5		T51	1
all_values[11]	auto[0]	auto[0]	auto[0]	49	1			T14	1		T47	1		T51	3
all_values[11]	auto[0]	auto[0]	auto[1]	118	1			T14	3		T47	7		T51	1
all_values[11]	auto[0]	auto[1]	auto[0]	45	1			T47	3		T120	1		T119	1
all_values[11]	auto[0]	auto[1]	auto[1]	97	1			T47	2		T119	2		T225	2
all_values[11]	auto[1]	auto[0]	auto[1]	117	1			T14	3		T47	4		T51	3
all_values[11]	auto[1]	auto[1]	auto[1]	89	1			T47	4		T119	2		T172	1
all_values[12]	auto[0]	auto[0]	auto[0]	45	1			T172	1		T225	2		T226	1
all_values[12]	auto[0]	auto[0]	auto[1]	126	1			T14	2		T47	6		T51	3
all_values[12]	auto[0]	auto[1]	auto[0]	30	1			T51	3		T120	1		T172	1
all_values[12]	auto[0]	auto[1]	auto[1]	107	1			T14	1		T47	2		T120	1
all_values[12]	auto[1]	auto[0]	auto[1]	119	1			T14	4		T47	7		T51	1
all_values[12]	auto[1]	auto[1]	auto[1]	88	1			T47	6		T120	2		T119	2
all_values[13]	auto[0]	auto[0]	auto[0]	57	1			T14	1		T47	2		T172	4
all_values[13]	auto[0]	auto[0]	auto[1]	98	1			T14	2		T47	4		T120	1
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T14	2		T51	2		T120	1
all_values[13]	auto[0]	auto[1]	auto[1]	124	1			T47	6		T51	2		T120	1
all_values[13]	auto[1]	auto[0]	auto[1]	119	1			T14	1		T47	2		T120	1
all_values[13]	auto[1]	auto[1]	auto[1]	89	1			T14	1		T47	7		T51	3
all_values[14]	auto[0]	auto[0]	auto[0]	48	1			T47	1		T119	2		T172	1
all_values[14]	auto[0]	auto[0]	auto[1]	110	1			T14	1		T47	8		T51	3
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T14	1		T120	1		T119	2
all_values[14]	auto[0]	auto[1]	auto[1]	107	1			T14	3		T47	2		T51	1
all_values[14]	auto[1]	auto[0]	auto[1]	117	1			T14	1		T47	6		T51	1
all_values[14]	auto[1]	auto[1]	auto[1]	107	1			T14	1		T47	4		T51	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal