| T1301 |
/workspace/coverage/default/47.i2c_host_stress_all.3330530170 |
|
|
Mar 07 02:37:45 PM PST 24 |
Mar 07 03:00:49 PM PST 24 |
87371436306 ps |
| T1302 |
/workspace/coverage/default/17.i2c_host_fifo_reset_rx.1923253355 |
|
|
Mar 07 02:28:05 PM PST 24 |
Mar 07 02:28:10 PM PST 24 |
328406563 ps |
| T1303 |
/workspace/coverage/default/24.i2c_host_fifo_overflow.1790582885 |
|
|
Mar 07 02:30:32 PM PST 24 |
Mar 07 02:33:05 PM PST 24 |
2042390697 ps |
| T1304 |
/workspace/coverage/default/26.i2c_target_stress_wr.1352238216 |
|
|
Mar 07 02:31:15 PM PST 24 |
Mar 07 02:36:22 PM PST 24 |
46382498996 ps |
| T1305 |
/workspace/coverage/default/34.i2c_host_stretch_timeout.1361424216 |
|
|
Mar 07 02:34:02 PM PST 24 |
Mar 07 02:34:13 PM PST 24 |
2633670718 ps |
| T1306 |
/workspace/coverage/default/13.i2c_target_stress_wr.110061465 |
|
|
Mar 07 02:26:47 PM PST 24 |
Mar 07 02:27:11 PM PST 24 |
11493395816 ps |
| T1307 |
/workspace/coverage/default/23.i2c_target_unexp_stop.2610702719 |
|
|
Mar 07 02:30:29 PM PST 24 |
Mar 07 02:30:37 PM PST 24 |
2795353755 ps |
| T1308 |
/workspace/coverage/default/33.i2c_host_rx_oversample.2527816035 |
|
|
Mar 07 02:33:38 PM PST 24 |
Mar 07 02:36:20 PM PST 24 |
9538935096 ps |
| T1309 |
/workspace/coverage/default/20.i2c_target_intr_stress_wr.4281196062 |
|
|
Mar 07 02:29:21 PM PST 24 |
Mar 07 02:29:25 PM PST 24 |
11510240098 ps |
| T1310 |
/workspace/coverage/default/31.i2c_target_perf.1216042069 |
|
|
Mar 07 02:33:13 PM PST 24 |
Mar 07 02:33:19 PM PST 24 |
3907382152 ps |
| T1311 |
/workspace/coverage/default/33.i2c_target_intr_smoke.2991703915 |
|
|
Mar 07 02:33:49 PM PST 24 |
Mar 07 02:33:53 PM PST 24 |
1680131275 ps |
| T1312 |
/workspace/coverage/default/36.i2c_target_stretch.2548573333 |
|
|
Mar 07 02:34:31 PM PST 24 |
Mar 07 03:17:36 PM PST 24 |
34262928601 ps |
| T1313 |
/workspace/coverage/default/38.i2c_target_stretch.1601569585 |
|
|
Mar 07 02:35:19 PM PST 24 |
Mar 07 03:02:40 PM PST 24 |
24873229396 ps |
| T1314 |
/workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3973533128 |
|
|
Mar 07 02:26:56 PM PST 24 |
Mar 07 02:27:24 PM PST 24 |
895964321 ps |
| T1315 |
/workspace/coverage/default/10.i2c_target_bad_addr.3903172201 |
|
|
Mar 07 02:25:37 PM PST 24 |
Mar 07 02:25:41 PM PST 24 |
4519640638 ps |
| T1316 |
/workspace/coverage/default/17.i2c_target_intr_stress_wr.59384323 |
|
|
Mar 07 02:28:08 PM PST 24 |
Mar 07 02:28:10 PM PST 24 |
9485384280 ps |
| T1317 |
/workspace/coverage/default/20.i2c_target_fifo_reset_tx.4075388663 |
|
|
Mar 07 02:29:22 PM PST 24 |
Mar 07 02:29:39 PM PST 24 |
10295767989 ps |
| T1318 |
/workspace/coverage/default/18.i2c_host_mode_toggle.555504813 |
|
|
Mar 07 02:28:44 PM PST 24 |
Mar 07 02:31:45 PM PST 24 |
3254818920 ps |
| T1319 |
/workspace/coverage/default/25.i2c_target_fifo_reset_tx.2205323067 |
|
|
Mar 07 02:31:05 PM PST 24 |
Mar 07 02:31:09 PM PST 24 |
11267623493 ps |
| T1320 |
/workspace/coverage/default/26.i2c_target_perf.3366271881 |
|
|
Mar 07 02:31:29 PM PST 24 |
Mar 07 02:31:33 PM PST 24 |
519730851 ps |
| T1321 |
/workspace/coverage/default/22.i2c_host_fifo_watermark.2150672338 |
|
|
Mar 07 02:29:45 PM PST 24 |
Mar 07 02:33:27 PM PST 24 |
28012228120 ps |
| T1322 |
/workspace/coverage/default/41.i2c_host_stretch_timeout.2285382615 |
|
|
Mar 07 02:36:04 PM PST 24 |
Mar 07 02:36:22 PM PST 24 |
3927821224 ps |
| T1323 |
/workspace/coverage/default/4.i2c_target_fifo_reset_tx.2037486191 |
|
|
Mar 07 02:22:44 PM PST 24 |
Mar 07 02:22:58 PM PST 24 |
10387818864 ps |
| T1324 |
/workspace/coverage/default/48.i2c_host_fifo_watermark.55014522 |
|
|
Mar 07 02:37:53 PM PST 24 |
Mar 07 02:43:25 PM PST 24 |
20139579228 ps |
| T1325 |
/workspace/coverage/default/8.i2c_target_perf.1402596576 |
|
|
Mar 07 02:24:30 PM PST 24 |
Mar 07 02:24:34 PM PST 24 |
1249351451 ps |
| T145 |
/workspace/coverage/default/26.i2c_host_stress_all.3873307454 |
|
|
Mar 07 02:31:16 PM PST 24 |
Mar 07 02:41:37 PM PST 24 |
52965040471 ps |
| T1326 |
/workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1253110656 |
|
|
Mar 07 02:33:37 PM PST 24 |
Mar 07 02:33:51 PM PST 24 |
244816189 ps |
| T1327 |
/workspace/coverage/default/6.i2c_host_override.397799326 |
|
|
Mar 07 02:23:20 PM PST 24 |
Mar 07 02:23:21 PM PST 24 |
20403916 ps |
| T1328 |
/workspace/coverage/default/24.i2c_host_mode_toggle.4095859139 |
|
|
Mar 07 02:30:41 PM PST 24 |
Mar 07 02:32:15 PM PST 24 |
3067463102 ps |
| T1329 |
/workspace/coverage/default/13.i2c_target_fifo_reset_tx.3900219273 |
|
|
Mar 07 02:26:52 PM PST 24 |
Mar 07 02:27:03 PM PST 24 |
10200023913 ps |
| T1330 |
/workspace/coverage/default/24.i2c_target_intr_stress_wr.2488612458 |
|
|
Mar 07 02:30:34 PM PST 24 |
Mar 07 02:30:41 PM PST 24 |
10950904298 ps |
| T1331 |
/workspace/coverage/default/28.i2c_alert_test.3475735762 |
|
|
Mar 07 02:32:10 PM PST 24 |
Mar 07 02:32:10 PM PST 24 |
40812667 ps |
| T1332 |
/workspace/coverage/default/15.i2c_host_fifo_watermark.308600759 |
|
|
Mar 07 02:27:15 PM PST 24 |
Mar 07 02:34:16 PM PST 24 |
21528963858 ps |
| T1333 |
/workspace/coverage/default/18.i2c_target_fifo_reset_acq.3394200879 |
|
|
Mar 07 02:28:36 PM PST 24 |
Mar 07 02:29:39 PM PST 24 |
10034128076 ps |
| T1334 |
/workspace/coverage/default/23.i2c_target_fifo_reset_tx.741090584 |
|
|
Mar 07 02:30:29 PM PST 24 |
Mar 07 02:30:38 PM PST 24 |
10124483474 ps |
| T1335 |
/workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1092211993 |
|
|
Mar 07 02:33:24 PM PST 24 |
Mar 07 02:33:50 PM PST 24 |
498350213 ps |
| T1336 |
/workspace/coverage/default/42.i2c_alert_test.912073028 |
|
|
Mar 07 02:36:33 PM PST 24 |
Mar 07 02:36:33 PM PST 24 |
41458610 ps |
| T1337 |
/workspace/coverage/default/5.i2c_target_bad_addr.4059896372 |
|
|
Mar 07 02:23:20 PM PST 24 |
Mar 07 02:23:25 PM PST 24 |
3580138278 ps |
| T1338 |
/workspace/coverage/default/32.i2c_target_intr_smoke.1813922941 |
|
|
Mar 07 02:33:32 PM PST 24 |
Mar 07 02:33:37 PM PST 24 |
4817223469 ps |
| T1339 |
/workspace/coverage/default/11.i2c_host_fifo_overflow.1372728295 |
|
|
Mar 07 02:25:43 PM PST 24 |
Mar 07 02:26:35 PM PST 24 |
2648109647 ps |
| T1340 |
/workspace/coverage/default/13.i2c_alert_test.1656202216 |
|
|
Mar 07 02:26:52 PM PST 24 |
Mar 07 02:26:53 PM PST 24 |
24427137 ps |
| T1341 |
/workspace/coverage/default/0.i2c_host_perf.1398454316 |
|
|
Mar 07 02:19:35 PM PST 24 |
Mar 07 02:21:36 PM PST 24 |
25994605417 ps |
| T1342 |
/workspace/coverage/default/42.i2c_host_perf.323212822 |
|
|
Mar 07 02:36:20 PM PST 24 |
Mar 07 02:37:25 PM PST 24 |
25986459960 ps |
| T1343 |
/workspace/coverage/default/46.i2c_host_mode_toggle.979928920 |
|
|
Mar 07 02:37:38 PM PST 24 |
Mar 07 02:39:36 PM PST 24 |
7088735702 ps |
| T1344 |
/workspace/coverage/default/33.i2c_target_perf.3862729197 |
|
|
Mar 07 02:33:45 PM PST 24 |
Mar 07 02:33:48 PM PST 24 |
2448802478 ps |
| T1345 |
/workspace/coverage/default/11.i2c_target_stress_all.2351358850 |
|
|
Mar 07 02:26:04 PM PST 24 |
Mar 07 02:26:58 PM PST 24 |
137678412528 ps |
| T1346 |
/workspace/coverage/default/30.i2c_target_unexp_stop.2264644757 |
|
|
Mar 07 02:32:50 PM PST 24 |
Mar 07 02:32:55 PM PST 24 |
2542029580 ps |
| T1347 |
/workspace/coverage/default/25.i2c_target_hrst.3674958179 |
|
|
Mar 07 02:31:05 PM PST 24 |
Mar 07 02:31:08 PM PST 24 |
500197313 ps |
| T1348 |
/workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2392278788 |
|
|
Mar 07 02:29:45 PM PST 24 |
Mar 07 02:29:46 PM PST 24 |
265484346 ps |
| T1349 |
/workspace/coverage/default/25.i2c_host_rx_oversample.3055935605 |
|
|
Mar 07 02:30:41 PM PST 24 |
Mar 07 02:34:21 PM PST 24 |
2514088513 ps |
| T1350 |
/workspace/coverage/default/38.i2c_host_smoke.342483030 |
|
|
Mar 07 02:35:10 PM PST 24 |
Mar 07 02:36:30 PM PST 24 |
9522282052 ps |
| T1351 |
/workspace/coverage/default/16.i2c_host_fifo_overflow.2264834164 |
|
|
Mar 07 02:27:43 PM PST 24 |
Mar 07 02:30:41 PM PST 24 |
4525275540 ps |
| T1352 |
/workspace/coverage/default/25.i2c_target_stress_wr.248132068 |
|
|
Mar 07 02:30:54 PM PST 24 |
Mar 07 02:31:29 PM PST 24 |
31328232325 ps |
| T1353 |
/workspace/coverage/default/32.i2c_host_fifo_full.3782233831 |
|
|
Mar 07 02:33:23 PM PST 24 |
Mar 07 02:35:22 PM PST 24 |
3233979480 ps |
| T1354 |
/workspace/coverage/default/35.i2c_target_stress_wr.778481984 |
|
|
Mar 07 02:34:17 PM PST 24 |
Mar 07 02:34:32 PM PST 24 |
10662996700 ps |
| T1355 |
/workspace/coverage/default/48.i2c_host_fifo_fmt_empty.4131434593 |
|
|
Mar 07 02:37:55 PM PST 24 |
Mar 07 02:38:06 PM PST 24 |
442635481 ps |
| T1356 |
/workspace/coverage/default/40.i2c_target_stress_rd.3926405983 |
|
|
Mar 07 02:35:48 PM PST 24 |
Mar 07 02:36:04 PM PST 24 |
920051819 ps |
| T1357 |
/workspace/coverage/default/34.i2c_target_stress_wr.2621963238 |
|
|
Mar 07 02:34:04 PM PST 24 |
Mar 07 02:34:07 PM PST 24 |
15366650376 ps |
| T1358 |
/workspace/coverage/default/10.i2c_host_fifo_overflow.676209751 |
|
|
Mar 07 02:25:28 PM PST 24 |
Mar 07 02:29:03 PM PST 24 |
2750378901 ps |
| T1359 |
/workspace/coverage/default/39.i2c_target_stress_rd.2477601239 |
|
|
Mar 07 02:35:39 PM PST 24 |
Mar 07 02:35:44 PM PST 24 |
249554341 ps |
| T1360 |
/workspace/coverage/default/16.i2c_target_bad_addr.646117599 |
|
|
Mar 07 02:28:04 PM PST 24 |
Mar 07 02:28:10 PM PST 24 |
6688846194 ps |
| T1361 |
/workspace/coverage/default/18.i2c_target_perf.2893513537 |
|
|
Mar 07 02:28:37 PM PST 24 |
Mar 07 02:28:43 PM PST 24 |
4053415967 ps |
| T1362 |
/workspace/coverage/default/9.i2c_target_intr_smoke.2571755023 |
|
|
Mar 07 02:24:58 PM PST 24 |
Mar 07 02:25:04 PM PST 24 |
2694355220 ps |
| T1363 |
/workspace/coverage/default/32.i2c_target_stress_wr.1589086521 |
|
|
Mar 07 02:33:37 PM PST 24 |
Mar 07 02:33:53 PM PST 24 |
13064941989 ps |
| T1364 |
/workspace/coverage/default/10.i2c_host_stress_all.397550953 |
|
|
Mar 07 02:25:22 PM PST 24 |
Mar 07 03:18:22 PM PST 24 |
14774056709 ps |
| T1365 |
/workspace/coverage/default/13.i2c_host_fifo_watermark.1174668601 |
|
|
Mar 07 02:26:38 PM PST 24 |
Mar 07 02:28:38 PM PST 24 |
14900934727 ps |
| T1366 |
/workspace/coverage/default/4.i2c_target_fifo_reset_acq.3898095514 |
|
|
Mar 07 02:22:49 PM PST 24 |
Mar 07 02:22:52 PM PST 24 |
10807288805 ps |
| T1367 |
/workspace/coverage/default/39.i2c_host_fifo_reset_fmt.403084679 |
|
|
Mar 07 02:35:32 PM PST 24 |
Mar 07 02:35:33 PM PST 24 |
224507913 ps |
| T1368 |
/workspace/coverage/default/3.i2c_target_unexp_stop.2637935941 |
|
|
Mar 07 02:22:20 PM PST 24 |
Mar 07 02:22:27 PM PST 24 |
5526881231 ps |
| T1369 |
/workspace/coverage/default/49.i2c_host_fifo_overflow.2419249067 |
|
|
Mar 07 02:38:10 PM PST 24 |
Mar 07 02:38:52 PM PST 24 |
7609714354 ps |
| T1370 |
/workspace/coverage/default/21.i2c_host_fifo_reset_rx.1972001265 |
|
|
Mar 07 02:29:29 PM PST 24 |
Mar 07 02:29:39 PM PST 24 |
540699679 ps |
| T34 |
/workspace/coverage/default/32.i2c_host_mode_toggle.1178667696 |
|
|
Mar 07 02:33:37 PM PST 24 |
Mar 07 02:36:25 PM PST 24 |
13335053721 ps |
| T1371 |
/workspace/coverage/default/16.i2c_host_rx_oversample.3825731101 |
|
|
Mar 07 02:27:43 PM PST 24 |
Mar 07 02:28:57 PM PST 24 |
1892185049 ps |
| T1372 |
/workspace/coverage/default/34.i2c_host_fifo_fmt_empty.825304795 |
|
|
Mar 07 02:34:02 PM PST 24 |
Mar 07 02:34:25 PM PST 24 |
831373981 ps |
| T1373 |
/workspace/coverage/default/6.i2c_host_rx_oversample.2698339808 |
|
|
Mar 07 02:23:28 PM PST 24 |
Mar 07 02:25:16 PM PST 24 |
2289387434 ps |
| T1374 |
/workspace/coverage/default/13.i2c_target_perf.2490706745 |
|
|
Mar 07 02:26:52 PM PST 24 |
Mar 07 02:26:56 PM PST 24 |
562541396 ps |
| T1375 |
/workspace/coverage/default/26.i2c_host_mode_toggle.3289745037 |
|
|
Mar 07 02:31:28 PM PST 24 |
Mar 07 02:32:57 PM PST 24 |
3250742800 ps |
| T204 |
/workspace/coverage/default/11.i2c_host_perf.3012830 |
|
|
Mar 07 02:25:55 PM PST 24 |
Mar 07 02:26:30 PM PST 24 |
9213622509 ps |
| T1376 |
/workspace/coverage/default/41.i2c_host_rx_oversample.4182076804 |
|
|
Mar 07 02:36:05 PM PST 24 |
Mar 07 02:37:26 PM PST 24 |
4214758562 ps |
| T1377 |
/workspace/coverage/default/28.i2c_host_mode_toggle.3596980196 |
|
|
Mar 07 02:32:09 PM PST 24 |
Mar 07 02:33:18 PM PST 24 |
3235976368 ps |
| T1378 |
/workspace/coverage/default/43.i2c_host_fifo_overflow.3463212104 |
|
|
Mar 07 02:36:31 PM PST 24 |
Mar 07 02:39:08 PM PST 24 |
2268740814 ps |
| T1379 |
/workspace/coverage/default/36.i2c_target_fifo_reset_acq.3125234712 |
|
|
Mar 07 02:34:46 PM PST 24 |
Mar 07 02:34:59 PM PST 24 |
10238161735 ps |
| T1380 |
/workspace/coverage/default/22.i2c_host_smoke.4104070175 |
|
|
Mar 07 02:29:46 PM PST 24 |
Mar 07 02:31:59 PM PST 24 |
2308715951 ps |
| T1381 |
/workspace/coverage/default/43.i2c_target_timeout.1410311 |
|
|
Mar 07 02:36:40 PM PST 24 |
Mar 07 02:36:47 PM PST 24 |
15329656266 ps |
| T1382 |
/workspace/coverage/default/48.i2c_target_stress_wr.1976128970 |
|
|
Mar 07 02:38:02 PM PST 24 |
Mar 07 02:44:54 PM PST 24 |
37048698655 ps |
| T1383 |
/workspace/coverage/default/40.i2c_target_unexp_stop.1572369009 |
|
|
Mar 07 02:36:02 PM PST 24 |
Mar 07 02:36:08 PM PST 24 |
883628792 ps |
| T1384 |
/workspace/coverage/default/41.i2c_host_stress_all.865198127 |
|
|
Mar 07 02:36:11 PM PST 24 |
Mar 07 02:51:12 PM PST 24 |
52990886675 ps |
| T1385 |
/workspace/coverage/default/14.i2c_target_intr_smoke.1816560596 |
|
|
Mar 07 02:27:02 PM PST 24 |
Mar 07 02:27:08 PM PST 24 |
2510476097 ps |
| T1386 |
/workspace/coverage/default/15.i2c_host_rx_oversample.2881871850 |
|
|
Mar 07 02:27:14 PM PST 24 |
Mar 07 02:29:50 PM PST 24 |
3199220113 ps |
| T1387 |
/workspace/coverage/default/39.i2c_host_stress_all.3084727541 |
|
|
Mar 07 02:35:33 PM PST 24 |
Mar 07 03:11:05 PM PST 24 |
23022651204 ps |
| T1388 |
/workspace/coverage/default/11.i2c_host_fifo_reset_fmt.45814655 |
|
|
Mar 07 02:25:43 PM PST 24 |
Mar 07 02:25:44 PM PST 24 |
125524564 ps |
| T1389 |
/workspace/coverage/default/34.i2c_host_stress_all.1134727578 |
|
|
Mar 07 02:34:01 PM PST 24 |
Mar 07 03:01:40 PM PST 24 |
94029183904 ps |
| T1390 |
/workspace/coverage/default/31.i2c_target_stress_wr.372143980 |
|
|
Mar 07 02:33:07 PM PST 24 |
Mar 07 02:35:38 PM PST 24 |
56558926471 ps |
| T1391 |
/workspace/coverage/default/48.i2c_host_stretch_timeout.2941836675 |
|
|
Mar 07 02:38:01 PM PST 24 |
Mar 07 02:38:13 PM PST 24 |
2708792856 ps |
| T1392 |
/workspace/coverage/default/38.i2c_host_stress_all.3170622972 |
|
|
Mar 07 02:35:21 PM PST 24 |
Mar 07 02:56:46 PM PST 24 |
16268848107 ps |
| T1393 |
/workspace/coverage/default/24.i2c_target_hrst.2526216262 |
|
|
Mar 07 02:30:44 PM PST 24 |
Mar 07 02:30:47 PM PST 24 |
629211121 ps |
| T1394 |
/workspace/coverage/default/2.i2c_target_hrst.1098139007 |
|
|
Mar 07 02:21:56 PM PST 24 |
Mar 07 02:21:59 PM PST 24 |
4699869698 ps |
| T1395 |
/workspace/coverage/default/45.i2c_host_smoke.3467134692 |
|
|
Mar 07 02:37:05 PM PST 24 |
Mar 07 02:38:19 PM PST 24 |
2623450762 ps |
| T1396 |
/workspace/coverage/default/30.i2c_host_rx_oversample.1558238650 |
|
|
Mar 07 02:32:37 PM PST 24 |
Mar 07 02:35:58 PM PST 24 |
17870113646 ps |
| T1397 |
/workspace/coverage/default/36.i2c_host_override.2875755379 |
|
|
Mar 07 02:34:32 PM PST 24 |
Mar 07 02:34:33 PM PST 24 |
39266355 ps |
| T1398 |
/workspace/coverage/default/46.i2c_host_fifo_overflow.56291255 |
|
|
Mar 07 02:37:30 PM PST 24 |
Mar 07 02:38:19 PM PST 24 |
2579420814 ps |
| T1399 |
/workspace/coverage/default/4.i2c_host_stretch_timeout.1038677718 |
|
|
Mar 07 02:22:40 PM PST 24 |
Mar 07 02:22:55 PM PST 24 |
845095937 ps |
| T1400 |
/workspace/coverage/default/4.i2c_host_perf.1617590801 |
|
|
Mar 07 02:22:37 PM PST 24 |
Mar 07 02:24:53 PM PST 24 |
24912192877 ps |
| T1401 |
/workspace/coverage/default/44.i2c_target_unexp_stop.3797432521 |
|
|
Mar 07 02:37:05 PM PST 24 |
Mar 07 02:37:14 PM PST 24 |
4626669668 ps |
| T1402 |
/workspace/coverage/default/32.i2c_host_fifo_overflow.4066803953 |
|
|
Mar 07 02:33:22 PM PST 24 |
Mar 07 02:37:36 PM PST 24 |
5117646269 ps |
| T1403 |
/workspace/coverage/default/13.i2c_target_bad_addr.3298382867 |
|
|
Mar 07 02:26:47 PM PST 24 |
Mar 07 02:26:50 PM PST 24 |
740758947 ps |
| T111 |
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1272962535 |
|
|
Mar 07 12:53:01 PM PST 24 |
Mar 07 12:53:02 PM PST 24 |
19288654 ps |
| T1404 |
/workspace/coverage/cover_reg_top/0.i2c_intr_test.591016637 |
|
|
Mar 07 12:53:20 PM PST 24 |
Mar 07 12:53:21 PM PST 24 |
51467229 ps |
| T97 |
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2734788471 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
37099103 ps |
| T58 |
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.279033676 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
154361924 ps |
| T1405 |
/workspace/coverage/cover_reg_top/48.i2c_intr_test.672650028 |
|
|
Mar 07 12:53:29 PM PST 24 |
Mar 07 12:53:30 PM PST 24 |
57845427 ps |
| T1406 |
/workspace/coverage/cover_reg_top/46.i2c_intr_test.126197888 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
16860557 ps |
| T59 |
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.530401868 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:13 PM PST 24 |
46811988 ps |
| T60 |
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.602010560 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
20845664 ps |
| T1407 |
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2097607484 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
168369912 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.705629636 |
|
|
Mar 07 12:53:27 PM PST 24 |
Mar 07 12:53:29 PM PST 24 |
52913976 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3037046691 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
98795266 ps |
| T62 |
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3162225415 |
|
|
Mar 07 12:53:18 PM PST 24 |
Mar 07 12:53:19 PM PST 24 |
311552985 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3316549648 |
|
|
Mar 07 12:52:55 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
1650933985 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3010455301 |
|
|
Mar 07 12:53:15 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
37110331 ps |
| T98 |
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4122946015 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
30452298 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3877931077 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:29 PM PST 24 |
21732762 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1303693374 |
|
|
Mar 07 12:53:21 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
24765595 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.10405700 |
|
|
Mar 07 12:52:59 PM PST 24 |
Mar 07 12:53:01 PM PST 24 |
438047965 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1418349243 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
18666094 ps |
| T117 |
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3182011663 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:57 PM PST 24 |
30921047 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.2932530104 |
|
|
Mar 07 12:53:02 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
186444369 ps |
| T68 |
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.542417049 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
41794390 ps |
| T118 |
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.339754737 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
24396928 ps |
| T1408 |
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1585594560 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
131971042 ps |
| T1409 |
/workspace/coverage/cover_reg_top/43.i2c_intr_test.1301799020 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
29720780 ps |
| T1410 |
/workspace/coverage/cover_reg_top/26.i2c_intr_test.181656944 |
|
|
Mar 07 12:53:02 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
167620678 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.131836770 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
326372510 ps |
| T99 |
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1601162406 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
46125329 ps |
| T1411 |
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1033132510 |
|
|
Mar 07 12:53:26 PM PST 24 |
Mar 07 12:53:27 PM PST 24 |
22051912 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1115483485 |
|
|
Mar 07 12:53:19 PM PST 24 |
Mar 07 12:53:21 PM PST 24 |
152679584 ps |
| T92 |
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2143018996 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:18 PM PST 24 |
27250776 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1548795719 |
|
|
Mar 07 12:53:21 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
53159131 ps |
| T100 |
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2140120549 |
|
|
Mar 07 12:53:03 PM PST 24 |
Mar 07 12:53:04 PM PST 24 |
15591341 ps |
| T1412 |
/workspace/coverage/cover_reg_top/36.i2c_intr_test.1411932126 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
20133737 ps |
| T1413 |
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2467611447 |
|
|
Mar 07 12:53:03 PM PST 24 |
Mar 07 12:53:04 PM PST 24 |
26913899 ps |
| T1414 |
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3074376610 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
42178784 ps |
| T1415 |
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.268357157 |
|
|
Mar 07 12:53:02 PM PST 24 |
Mar 07 12:53:06 PM PST 24 |
481559740 ps |
| T1416 |
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2310510758 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
80349165 ps |
| T1417 |
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2443204115 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
18884959 ps |
| T1418 |
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3169282369 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
57324197 ps |
| T1419 |
/workspace/coverage/cover_reg_top/20.i2c_intr_test.202800872 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
42946337 ps |
| T1420 |
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1656678683 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:11 PM PST 24 |
57422310 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3099688209 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
73458159 ps |
| T121 |
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1432108127 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
42579197 ps |
| T69 |
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1440115731 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
38592258 ps |
| T1421 |
/workspace/coverage/cover_reg_top/30.i2c_intr_test.1402376992 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:13 PM PST 24 |
160300531 ps |
| T1422 |
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3961996498 |
|
|
Mar 07 12:53:26 PM PST 24 |
Mar 07 12:53:28 PM PST 24 |
29888120 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1307478037 |
|
|
Mar 07 12:53:15 PM PST 24 |
Mar 07 12:53:19 PM PST 24 |
423644867 ps |
| T1423 |
/workspace/coverage/cover_reg_top/17.i2c_intr_test.3789216279 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
20007055 ps |
| T1424 |
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1057599329 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
44217086 ps |
| T1425 |
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.528036524 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
154452803 ps |
| T1426 |
/workspace/coverage/cover_reg_top/34.i2c_intr_test.1769779157 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:57 PM PST 24 |
14946400 ps |
| T1427 |
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3075531621 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
34400935 ps |
| T1428 |
/workspace/coverage/cover_reg_top/18.i2c_intr_test.3724961114 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:13 PM PST 24 |
247105606 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3386908998 |
|
|
Mar 07 12:52:59 PM PST 24 |
Mar 07 12:53:00 PM PST 24 |
393275453 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2755919936 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
344470217 ps |
| T1429 |
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3975653207 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
74992964 ps |
| T1430 |
/workspace/coverage/cover_reg_top/33.i2c_intr_test.4216188070 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:57 PM PST 24 |
54051219 ps |
| T77 |
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2799738496 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:16 PM PST 24 |
79796166 ps |
| T1431 |
/workspace/coverage/cover_reg_top/44.i2c_intr_test.4041336155 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
16995034 ps |
| T101 |
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2452242149 |
|
|
Mar 07 12:52:55 PM PST 24 |
Mar 07 12:52:56 PM PST 24 |
28825635 ps |
| T1432 |
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3748056796 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
87385315 ps |
| T1433 |
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1999252796 |
|
|
Mar 07 12:53:24 PM PST 24 |
Mar 07 12:53:25 PM PST 24 |
79361062 ps |
| T1434 |
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.402842881 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
80451039 ps |
| T1435 |
/workspace/coverage/cover_reg_top/9.i2c_intr_test.953350750 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:18 PM PST 24 |
18149061 ps |
| T1436 |
/workspace/coverage/cover_reg_top/22.i2c_intr_test.236491702 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
48788511 ps |
| T123 |
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.2991762671 |
|
|
Mar 07 12:53:19 PM PST 24 |
Mar 07 12:53:20 PM PST 24 |
308493248 ps |
| T1437 |
/workspace/coverage/cover_reg_top/16.i2c_intr_test.4018273248 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
49873958 ps |
| T102 |
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1654492380 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
99643184 ps |
| T1438 |
/workspace/coverage/cover_reg_top/27.i2c_intr_test.2346258949 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
16033941 ps |
| T1439 |
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1266411490 |
|
|
Mar 07 12:53:03 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
57155007 ps |
| T1440 |
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3170092131 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
306923990 ps |
| T1441 |
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2362159487 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:53:06 PM PST 24 |
16022873 ps |
| T1442 |
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.3935667898 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:53:06 PM PST 24 |
49329442 ps |
| T1443 |
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2102418236 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
26861223 ps |
| T1444 |
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2019317679 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
26492223 ps |
| T78 |
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1422109583 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
184118568 ps |
| T1445 |
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3863322907 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
86299992 ps |
| T208 |
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.324751548 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
166266106 ps |
| T1446 |
/workspace/coverage/cover_reg_top/15.i2c_intr_test.540752596 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
37272025 ps |
| T1447 |
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3082837359 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
22574202 ps |
| T1448 |
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.4249783383 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
257140202 ps |
| T1449 |
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3107965883 |
|
|
Mar 07 12:52:58 PM PST 24 |
Mar 07 12:53:00 PM PST 24 |
29324113 ps |
| T1450 |
/workspace/coverage/cover_reg_top/3.i2c_intr_test.4011589012 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
16072040 ps |
| T1451 |
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2318062412 |
|
|
Mar 07 12:53:01 PM PST 24 |
Mar 07 12:53:02 PM PST 24 |
42026804 ps |
| T209 |
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3997216212 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
1103140575 ps |
| T1452 |
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1797682082 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
31688287 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2560053002 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
44879868 ps |
| T1453 |
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.822827586 |
|
|
Mar 07 12:53:01 PM PST 24 |
Mar 07 12:53:02 PM PST 24 |
379159409 ps |
| T1454 |
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3259066438 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
526517045 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.54729015 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:23 PM PST 24 |
19832306 ps |
| T1455 |
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3311109142 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:11 PM PST 24 |
38335463 ps |
| T1456 |
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2116079907 |
|
|
Mar 07 12:52:59 PM PST 24 |
Mar 07 12:53:00 PM PST 24 |
310963828 ps |
| T1457 |
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1470552798 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
28230824 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.405883011 |
|
|
Mar 07 12:53:02 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
100297921 ps |
| T1458 |
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3375144417 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
273308497 ps |
| T1459 |
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.426608905 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
94204641 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1464502993 |
|
|
Mar 07 12:53:00 PM PST 24 |
Mar 07 12:53:00 PM PST 24 |
120576884 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3468486733 |
|
|
Mar 07 12:52:59 PM PST 24 |
Mar 07 12:53:01 PM PST 24 |
502071359 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2215218987 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:04 PM PST 24 |
19956625 ps |
| T1460 |
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1103256230 |
|
|
Mar 07 12:53:19 PM PST 24 |
Mar 07 12:53:20 PM PST 24 |
77074801 ps |
| T1461 |
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1410463762 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
48977492 ps |
| T1462 |
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.315535303 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
75212482 ps |
| T1463 |
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2412391301 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
37153144 ps |
| T1464 |
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.15228825 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
221565628 ps |
| T1465 |
/workspace/coverage/cover_reg_top/11.i2c_intr_test.2065810731 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:13 PM PST 24 |
19751205 ps |
| T1466 |
/workspace/coverage/cover_reg_top/31.i2c_intr_test.4004648122 |
|
|
Mar 07 12:53:19 PM PST 24 |
Mar 07 12:53:20 PM PST 24 |
16661582 ps |
| T1467 |
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2747366748 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:06 PM PST 24 |
21694481 ps |
| T1468 |
/workspace/coverage/cover_reg_top/21.i2c_intr_test.471035509 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:13 PM PST 24 |
20551673 ps |
| T1469 |
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.800407511 |
|
|
Mar 07 12:53:03 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
47855689 ps |
| T1470 |
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1985196067 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
39112518 ps |
| T1471 |
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3729873300 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
39232637 ps |
| T1472 |
/workspace/coverage/cover_reg_top/39.i2c_intr_test.73480375 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
54572828 ps |
| T1473 |
/workspace/coverage/cover_reg_top/8.i2c_intr_test.3440574450 |
|
|
Mar 07 12:53:15 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
22361717 ps |
| T1474 |
/workspace/coverage/cover_reg_top/10.i2c_intr_test.3246425805 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:07 PM PST 24 |
39929061 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1163170074 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
74454041 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1773477543 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:57 PM PST 24 |
27285868 ps |
| T1475 |
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3568129191 |
|
|
Mar 07 12:53:20 PM PST 24 |
Mar 07 12:53:21 PM PST 24 |
25874170 ps |
| T1476 |
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.775836553 |
|
|
Mar 07 12:52:56 PM PST 24 |
Mar 07 12:52:59 PM PST 24 |
57545358 ps |
| T1477 |
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2585128671 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
39452053 ps |
| T1478 |
/workspace/coverage/cover_reg_top/23.i2c_intr_test.867010647 |
|
|
Mar 07 12:53:21 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
129353539 ps |
| T1479 |
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3177874541 |
|
|
Mar 07 12:53:15 PM PST 24 |
Mar 07 12:53:16 PM PST 24 |
51647669 ps |
| T1480 |
/workspace/coverage/cover_reg_top/24.i2c_intr_test.3812790050 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
20869611 ps |
| T1481 |
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1290099278 |
|
|
Mar 07 12:53:18 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
51750006 ps |
| T1482 |
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2868630950 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
26690938 ps |
| T1483 |
/workspace/coverage/cover_reg_top/12.i2c_intr_test.2138070270 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:05 PM PST 24 |
17385760 ps |
| T1484 |
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1449391277 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
39680793 ps |
| T1485 |
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2892457623 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:15 PM PST 24 |
53007469 ps |
| T1486 |
/workspace/coverage/cover_reg_top/6.i2c_intr_test.3113916312 |
|
|
Mar 07 12:53:03 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
14892903 ps |
| T1487 |
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2404707751 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
17881348 ps |
| T1488 |
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3392904477 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
18615786 ps |
| T1489 |
/workspace/coverage/cover_reg_top/35.i2c_intr_test.4157832860 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:57 PM PST 24 |
20871524 ps |
| T1490 |
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2779542108 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
88753695 ps |
| T1491 |
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1774027977 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:16 PM PST 24 |
116260816 ps |
| T1492 |
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1184568095 |
|
|
Mar 07 12:53:20 PM PST 24 |
Mar 07 12:53:21 PM PST 24 |
36229698 ps |
| T1493 |
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1817014259 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:08 PM PST 24 |
100838296 ps |
| T1494 |
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2759577946 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:11 PM PST 24 |
32500149 ps |
| T1495 |
/workspace/coverage/cover_reg_top/45.i2c_intr_test.547742010 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
17954800 ps |
| T1496 |
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2350051442 |
|
|
Mar 07 12:53:19 PM PST 24 |
Mar 07 12:53:20 PM PST 24 |
20444142 ps |
| T1497 |
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2430332245 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
361008236 ps |
| T1498 |
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3465520104 |
|
|
Mar 07 12:53:02 PM PST 24 |
Mar 07 12:53:03 PM PST 24 |
316829550 ps |
| T1499 |
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.197515949 |
|
|
Mar 07 12:53:04 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
47929779 ps |
| T1500 |
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2544347724 |
|
|
Mar 07 12:52:57 PM PST 24 |
Mar 07 12:52:58 PM PST 24 |
201899671 ps |
| T1501 |
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1553140608 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:16 PM PST 24 |
1199775005 ps |