Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	348	1			T1	1		T2	1		T3	5
all_pins[1]	348	1			T1	1		T2	1		T3	5
all_pins[2]	348	1			T1	1		T2	1		T3	5
all_pins[3]	348	1			T1	1		T2	1		T3	5
all_pins[4]	348	1			T1	1		T2	1		T3	5
all_pins[5]	348	1			T1	1		T2	1		T3	5
all_pins[6]	348	1			T1	1		T2	1		T3	5
all_pins[7]	348	1			T1	1		T2	1		T3	5
all_pins[8]	348	1			T1	1		T2	1		T3	5
all_pins[9]	348	1			T1	1		T2	1		T3	5
all_pins[10]	348	1			T1	1		T2	1		T3	5
all_pins[11]	348	1			T1	1		T2	1		T3	5
all_pins[12]	348	1			T1	1		T2	1		T3	5
all_pins[13]	348	1			T1	1		T2	1		T3	5
all_pins[14]	348	1			T1	1		T2	1		T3	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4255	1			T1	15		T2	15		T3	59
values[0x1]	965	1			T3	16		T7	23		T8	18
transitions[0x0=>0x1]	711	1			T3	8		T7	11		T8	11
transitions[0x1=>0x0]	717	1			T3	8		T7	11		T8	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280	1			T1	1		T2	1		T3	4
all_pins[0]	values[0x1]	68	1			T3	1		T8	3		T11	2
all_pins[0]	transitions[0x0=>0x1]	42	1			T3	1		T8	3		T11	1
all_pins[0]	transitions[0x1=>0x0]	33	1			T7	2		T8	1		T46	1
all_pins[1]	values[0x0]	289	1			T1	1		T2	1		T3	5
all_pins[1]	values[0x1]	59	1			T7	2		T8	1		T11	1
all_pins[1]	transitions[0x0=>0x1]	47	1			T7	2		T8	1		T11	1
all_pins[1]	transitions[0x1=>0x0]	44	1			T7	1		T8	2		T11	3
all_pins[2]	values[0x0]	292	1			T1	1		T2	1		T3	5
all_pins[2]	values[0x1]	56	1			T7	1		T8	2		T11	3
all_pins[2]	transitions[0x0=>0x1]	37	1			T7	1		T8	1		T11	2
all_pins[2]	transitions[0x1=>0x0]	63	1			T7	2		T11	2		T52	1
all_pins[3]	values[0x0]	266	1			T1	1		T2	1		T3	5
all_pins[3]	values[0x1]	82	1			T7	2		T8	1		T11	3
all_pins[3]	transitions[0x0=>0x1]	58	1			T8	1		T11	3		T60	1
all_pins[3]	transitions[0x1=>0x0]	47	1			T8	1		T22	1		T60	3
all_pins[4]	values[0x0]	277	1			T1	1		T2	1		T3	5
all_pins[4]	values[0x1]	71	1			T7	2		T8	1		T22	1
all_pins[4]	transitions[0x0=>0x1]	52	1			T8	1		T22	1		T52	2
all_pins[4]	transitions[0x1=>0x0]	49	1			T7	1		T22	3		T52	2
all_pins[5]	values[0x0]	280	1			T1	1		T2	1		T3	5
all_pins[5]	values[0x1]	68	1			T7	3		T22	3		T52	3
all_pins[5]	transitions[0x0=>0x1]	53	1			T7	1		T22	3		T52	2
all_pins[5]	transitions[0x1=>0x0]	46	1			T3	2		T8	1		T12	3
all_pins[6]	values[0x0]	287	1			T1	1		T2	1		T3	3
all_pins[6]	values[0x1]	61	1			T3	2		T7	2		T8	1
all_pins[6]	transitions[0x0=>0x1]	49	1			T12	3		T52	2		T60	3
all_pins[6]	transitions[0x1=>0x0]	58	1			T7	1		T8	2		T11	1
all_pins[7]	values[0x0]	278	1			T1	1		T2	1		T3	3
all_pins[7]	values[0x1]	70	1			T3	2		T7	3		T8	3
all_pins[7]	transitions[0x0=>0x1]	55	1			T3	1		T7	2		T8	1
all_pins[7]	transitions[0x1=>0x0]	57	1			T12	1		T52	2		T46	1
all_pins[8]	values[0x0]	276	1			T1	1		T2	1		T3	4
all_pins[8]	values[0x1]	72	1			T3	1		T7	1		T8	2
all_pins[8]	transitions[0x0=>0x1]	55	1			T3	1		T8	1		T12	1
all_pins[8]	transitions[0x1=>0x0]	44	1			T22	4		T60	1		T61	3
all_pins[9]	values[0x0]	287	1			T1	1		T2	1		T3	5
all_pins[9]	values[0x1]	61	1			T7	1		T8	1		T22	4
all_pins[9]	transitions[0x0=>0x1]	48	1			T7	1		T8	1		T22	4
all_pins[9]	transitions[0x1=>0x0]	48	1			T3	2		T7	1		T11	4
all_pins[10]	values[0x0]	287	1			T1	1		T2	1		T3	3
all_pins[10]	values[0x1]	61	1			T3	2		T7	1		T11	4
all_pins[10]	transitions[0x0=>0x1]	50	1			T3	1		T7	1		T11	4
all_pins[10]	transitions[0x1=>0x0]	34	1			T8	1		T11	1		T12	1
all_pins[11]	values[0x0]	303	1			T1	1		T2	1		T3	4
all_pins[11]	values[0x1]	45	1			T3	1		T8	1		T11	1
all_pins[11]	transitions[0x0=>0x1]	34	1			T3	1		T8	1		T11	1
all_pins[11]	transitions[0x1=>0x0]	51	1			T3	2		T7	2		T11	3
all_pins[12]	values[0x0]	286	1			T1	1		T2	1		T3	3
all_pins[12]	values[0x1]	62	1			T3	2		T7	2		T11	3
all_pins[12]	transitions[0x0=>0x1]	47	1			T3	1		T7	1		T11	1
all_pins[12]	transitions[0x1=>0x0]	53	1			T3	2		T7	1		T11	1
all_pins[13]	values[0x0]	280	1			T1	1		T2	1		T3	2
all_pins[13]	values[0x1]	68	1			T3	3		T7	2		T11	3
all_pins[13]	transitions[0x0=>0x1]	49	1			T3	1		T7	1		T11	3
all_pins[13]	transitions[0x1=>0x0]	42	1			T8	2		T52	2		T46	2
all_pins[14]	values[0x0]	287	1			T1	1		T2	1		T3	3
all_pins[14]	values[0x1]	61	1			T3	2		T7	1		T8	2
all_pins[14]	transitions[0x0=>0x1]	35	1			T3	1		T7	1		T52	1
all_pins[14]	transitions[0x1=>0x0]	48	1			T8	1		T11	2		T12	1