| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 59.25 | 52.83 | 59.96 | 94.44 | 0.00 | 53.33 | 100.00 | 54.20 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 52.50 | 52.50 | 50.29 | 50.29 | 53.79 | 53.79 | 96.93 | 96.93 | 0.00 | 0.00 | 51.50 | 51.50 | 96.47 | 96.47 | 18.49 | 18.49 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.681380357 |
| 57.73 | 5.24 | 52.16 | 1.87 | 57.93 | 4.13 | 99.49 | 2.56 | 0.00 | 0.00 | 53.22 | 1.72 | 96.79 | 0.32 | 44.54 | 26.05 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.3425767652 |
| 58.42 | 0.69 | 52.16 | 0.00 | 59.28 | 1.36 | 99.49 | 0.00 | 0.00 | 0.00 | 53.33 | 0.11 | 97.12 | 0.32 | 47.58 | 3.05 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1086017646 |
| 58.98 | 0.56 | 52.16 | 0.00 | 59.28 | 0.00 | 99.74 | 0.26 | 0.00 | 0.00 | 53.33 | 0.00 | 97.12 | 0.00 | 51.26 | 3.68 | /workspace/coverage/cover_reg_top/43.i2c_intr_test.3132896266 |
| 59.37 | 0.38 | 52.83 | 0.67 | 59.49 | 0.20 | 99.74 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 98.72 | 1.60 | 51.47 | 0.21 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2913350476 |
| 59.57 | 0.20 | 52.83 | 0.00 | 59.49 | 0.00 | 100.00 | 0.26 | 0.00 | 0.00 | 53.33 | 0.00 | 98.72 | 0.00 | 52.63 | 1.16 | /workspace/coverage/cover_reg_top/17.i2c_intr_test.3580909418 |
| 59.72 | 0.15 | 52.83 | 0.00 | 59.49 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 99.36 | 0.64 | 53.05 | 0.42 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2223125696 |
| 59.81 | 0.09 | 52.83 | 0.00 | 59.49 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.64 | 53.05 | 0.00 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2791257185 |
| 59.87 | 0.06 | 52.83 | 0.00 | 59.49 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.47 | 0.42 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3626796384 |
| 59.93 | 0.06 | 52.83 | 0.00 | 59.69 | 0.20 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.68 | 0.21 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1357719160 |
| 59.98 | 0.05 | 52.83 | 0.00 | 59.69 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.99 | 0.32 | /workspace/coverage/cover_reg_top/10.i2c_intr_test.3253067696 |
| 60.01 | 0.03 | 52.83 | 0.00 | 59.89 | 0.20 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.99 | 0.00 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.784033113 |
| 60.02 | 0.02 | 52.83 | 0.00 | 59.89 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 54.10 | 0.11 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1460047780 |
| 60.04 | 0.02 | 52.83 | 0.00 | 59.89 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 54.20 | 0.11 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4031070465 |
| 60.05 | 0.01 | 52.83 | 0.00 | 59.96 | 0.07 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 54.20 | 0.00 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3677144379 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.302408117 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2756261763 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.806399308 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.402137551 |
| /workspace/coverage/cover_reg_top/0.i2c_intr_test.521593835 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4225289291 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3415648657 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2301460315 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3035082458 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1668924122 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3137894682 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.2921740900 |
| /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3979019219 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2131445777 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1671208786 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3931934685 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2671774185 |
| /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1502737988 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1345175519 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4215454210 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.326128181 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3068610992 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.4224290358 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2922301335 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.835401718 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.299278423 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3449168087 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_rw.433406926 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.2760850810 |
| /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3596453000 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2454455756 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3034502889 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1484493054 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3618360335 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.2772420901 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3305293187 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.765893042 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1921354930 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4065663195 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.3613563966 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2276492656 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2321527935 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1695463289 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4267927435 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1908556416 |
| /workspace/coverage/cover_reg_top/15.i2c_intr_test.333014450 |
| /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.935218264 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_errors.258658981 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3271901018 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3041666616 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.4003483626 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2827083489 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1802847429 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1027397834 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1508810882 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2432326499 |
| /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2676879242 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2994891838 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2370172285 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1821389178 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3974117361 |
| /workspace/coverage/cover_reg_top/18.i2c_intr_test.554297219 |
| /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2078974119 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3408875418 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3995872870 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2624095961 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2393695783 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.766565635 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3385918576 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.616116310 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2747539947 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.112401766 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.818335201 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.1938490851 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4042774118 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1559375120 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.497549942 |
| /workspace/coverage/cover_reg_top/20.i2c_intr_test.2435635466 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.1327111089 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.1279775374 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.4121970080 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.1698119260 |
| /workspace/coverage/cover_reg_top/26.i2c_intr_test.127572511 |
| /workspace/coverage/cover_reg_top/27.i2c_intr_test.758731280 |
| /workspace/coverage/cover_reg_top/28.i2c_intr_test.3628845164 |
| /workspace/coverage/cover_reg_top/29.i2c_intr_test.1187457767 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4089966855 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1119726846 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.712828356 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1589550817 |
| /workspace/coverage/cover_reg_top/3.i2c_intr_test.999862112 |
| /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3306884660 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.334898064 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1224000978 |
| /workspace/coverage/cover_reg_top/30.i2c_intr_test.312969537 |
| /workspace/coverage/cover_reg_top/31.i2c_intr_test.119315959 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.3905660158 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.1115128231 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.3799376830 |
| /workspace/coverage/cover_reg_top/35.i2c_intr_test.2511333436 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.3211813812 |
| /workspace/coverage/cover_reg_top/37.i2c_intr_test.2715651411 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.1686598432 |
| /workspace/coverage/cover_reg_top/39.i2c_intr_test.4197626315 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.797430517 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2113854027 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.636684930 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.621326951 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1231780679 |
| /workspace/coverage/cover_reg_top/4.i2c_intr_test.2905577708 |
| /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.367617292 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_errors.370463492 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4116780664 |
| /workspace/coverage/cover_reg_top/40.i2c_intr_test.3257776004 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.962497024 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.4188373800 |
| /workspace/coverage/cover_reg_top/44.i2c_intr_test.3283656918 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.2459838212 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.2273950802 |
| /workspace/coverage/cover_reg_top/47.i2c_intr_test.867093474 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.339206682 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.4102000206 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3133323192 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.288437695 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.2109427964 |
| /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3886679955 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2789434703 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1205152919 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.182288133 |
| /workspace/coverage/cover_reg_top/6.i2c_intr_test.2452404014 |
| /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4294025073 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_errors.144822006 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1072007642 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.926807233 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.681754632 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.1173910917 |
| /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4075219457 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.29374356 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1764377030 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2479984575 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.317385484 |
| /workspace/coverage/cover_reg_top/8.i2c_intr_test.3857194386 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3321442797 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2040962629 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1998697186 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2229644273 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2102954995 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.1276685232 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2313207820 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1552686123 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1345175519 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:04 PM PDT 24 | 31131793 ps | ||
| T2 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.29374356 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:03 PM PDT 24 | 44172597 ps | ||
| T3 | /workspace/coverage/cover_reg_top/11.i2c_intr_test.4224290358 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 21741891 ps | ||
| T7 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.339206682 | Mar 10 01:11:21 PM PDT 24 | Mar 10 01:11:22 PM PDT 24 | 90723631 ps | ||
| T8 | /workspace/coverage/cover_reg_top/14.i2c_intr_test.3613563966 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 30151978 ps | ||
| T4 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.681380357 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:04 PM PDT 24 | 116335350 ps | ||
| T11 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.3425767652 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 54255356 ps | ||
| T12 | /workspace/coverage/cover_reg_top/26.i2c_intr_test.127572511 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 23472204 ps | ||
| T9 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.818335201 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:54 PM PDT 24 | 16434778 ps | ||
| T13 | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2321527935 | Mar 10 01:11:08 PM PDT 24 | Mar 10 01:11:10 PM PDT 24 | 85051203 ps | ||
| T10 | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2078974119 | Mar 10 01:11:15 PM PDT 24 | Mar 10 01:11:16 PM PDT 24 | 136810580 ps | ||
| T5 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1357719160 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 484675758 ps | ||
| T6 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2223125696 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 713715211 ps | ||
| T14 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1086017646 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 190928256 ps | ||
| T15 | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1764377030 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 363354666 ps | ||
| T22 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.554297219 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 19695792 ps | ||
| T23 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3886679955 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 86709616 ps | ||
| T16 | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1998697186 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:03 PM PDT 24 | 212926604 ps | ||
| T17 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3408875418 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 191058865 ps | ||
| T21 | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1224000978 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 282030863 ps | ||
| T52 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.333014450 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 19468506 ps | ||
| T60 | /workspace/coverage/cover_reg_top/7.i2c_intr_test.1173910917 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 59953443 ps | ||
| T18 | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2789434703 | Mar 10 01:10:57 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 358688839 ps | ||
| T19 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.299278423 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 158179527 ps | ||
| T20 | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.326128181 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 115202166 ps | ||
| T61 | /workspace/coverage/cover_reg_top/17.i2c_intr_test.3580909418 | Mar 10 01:11:21 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 20005618 ps | ||
| T24 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4089966855 | Mar 10 01:10:56 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 394810781 ps | ||
| T46 | /workspace/coverage/cover_reg_top/41.i2c_intr_test.962497024 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 18222053 ps | ||
| T25 | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2432326499 | Mar 10 01:11:12 PM PDT 24 | Mar 10 01:11:13 PM PDT 24 | 59565151 ps | ||
| T33 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.797430517 | Mar 10 01:10:57 PM PDT 24 | Mar 10 01:10:58 PM PDT 24 | 41937763 ps | ||
| T34 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4294025073 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 96539193 ps | ||
| T35 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3034502889 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:08 PM PDT 24 | 443781069 ps | ||
| T26 | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3137894682 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 83259779 ps | ||
| T36 | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3618360335 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 18609188 ps | ||
| T37 | /workspace/coverage/cover_reg_top/36.i2c_intr_test.3211813812 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 39490124 ps | ||
| T27 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2676879242 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 37625707 ps | ||
| T28 | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1231780679 | Mar 10 01:10:58 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 40356353 ps | ||
| T38 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2747539947 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:58 PM PDT 24 | 377423117 ps | ||
| T70 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1187457767 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 15223347 ps | ||
| T29 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2791257185 | Mar 10 01:10:53 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 79233474 ps | ||
| T54 | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3133323192 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:53 PM PDT 24 | 30439633 ps | ||
| T80 | /workspace/coverage/cover_reg_top/33.i2c_intr_test.1115128231 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 65043742 ps | ||
| T82 | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2393695783 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 39459682 ps | ||
| T30 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.935218264 | Mar 10 01:11:09 PM PDT 24 | Mar 10 01:11:10 PM PDT 24 | 19322515 ps | ||
| T57 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.784033113 | Mar 10 01:10:49 PM PDT 24 | Mar 10 01:10:52 PM PDT 24 | 241111931 ps | ||
| T62 | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3306884660 | Mar 10 01:10:56 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 72130145 ps | ||
| T78 | /workspace/coverage/cover_reg_top/23.i2c_intr_test.4121970080 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 19364951 ps | ||
| T83 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2040962629 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 206107435 ps | ||
| T69 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.616116310 | Mar 10 01:11:12 PM PDT 24 | Mar 10 01:11:14 PM PDT 24 | 345271094 ps | ||
| T84 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3979019219 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:53 PM PDT 24 | 96797782 ps | ||
| T55 | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1205152919 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 37056766 ps | ||
| T85 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3931934685 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 129908972 ps | ||
| T66 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1119726846 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 25610614 ps | ||
| T86 | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1802847429 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 42669960 ps | ||
| T71 | /workspace/coverage/cover_reg_top/43.i2c_intr_test.3132896266 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 52255813 ps | ||
| T77 | /workspace/coverage/cover_reg_top/21.i2c_intr_test.1327111089 | Mar 10 01:11:11 PM PDT 24 | Mar 10 01:11:12 PM PDT 24 | 61728460 ps | ||
| T79 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3857194386 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 19086456 ps | ||
| T31 | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2922301335 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 196119090 ps | ||
| T87 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2229644273 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:03 PM PDT 24 | 26109373 ps | ||
| T88 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3305293187 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 814545007 ps | ||
| T89 | /workspace/coverage/cover_reg_top/27.i2c_intr_test.758731280 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 25397318 ps | ||
| T32 | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.317385484 | Mar 10 01:10:59 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 18813987 ps | ||
| T65 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3385918576 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 56125787 ps | ||
| T74 | /workspace/coverage/cover_reg_top/34.i2c_intr_test.3799376830 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 50400377 ps | ||
| T90 | /workspace/coverage/cover_reg_top/32.i2c_intr_test.3905660158 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 46522935 ps | ||
| T56 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3677144379 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 70419471 ps | ||
| T58 | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4116780664 | Mar 10 01:10:57 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 806645153 ps | ||
| T91 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1508810882 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 220997614 ps | ||
| T81 | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2109427964 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 49051995 ps | ||
| T92 | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.765893042 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 70385136 ps | ||
| T68 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1072007642 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 232264532 ps | ||
| T93 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2313207820 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 133380438 ps | ||
| T39 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2913350476 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 27145570 ps | ||
| T94 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2435635466 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 18002658 ps | ||
| T40 | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4065663195 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 66267717 ps | ||
| T95 | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.806399308 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 81058752 ps | ||
| T96 | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1821389178 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 128854145 ps | ||
| T97 | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.334898064 | Mar 10 01:10:56 PM PDT 24 | Mar 10 01:10:58 PM PDT 24 | 128389435 ps | ||
| T41 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3035082458 | Mar 10 01:10:51 PM PDT 24 | Mar 10 01:10:52 PM PDT 24 | 26102524 ps | ||
| T72 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.2452404014 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 28780232 ps | ||
| T67 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1460047780 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 30533431 ps | ||
| T47 | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2301460315 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 1597392084 ps | ||
| T63 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3626796384 | Mar 10 01:11:07 PM PDT 24 | Mar 10 01:11:08 PM PDT 24 | 78109512 ps | ||
| T98 | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3068610992 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 26877933 ps | ||
| T75 | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2760850810 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 121402991 ps | ||
| T99 | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1921354930 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 68731458 ps | ||
| T100 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.4188373800 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 204550703 ps | ||
| T73 | /workspace/coverage/cover_reg_top/10.i2c_intr_test.3253067696 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 55744440 ps | ||
| T76 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.4197626315 | Mar 10 01:11:15 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 98689855 ps | ||
| T42 | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.402137551 | Mar 10 01:10:49 PM PDT 24 | Mar 10 01:10:50 PM PDT 24 | 155875635 ps | ||
| T101 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.3628845164 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 50365688 ps | ||
| T43 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.302408117 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 43344634 ps | ||
| T102 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1559375120 | Mar 10 01:10:48 PM PDT 24 | Mar 10 01:10:50 PM PDT 24 | 68678946 ps | ||
| T103 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.2772420901 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 17300041 ps | ||
| T104 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.621326951 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 37835591 ps | ||
| T105 | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.681754632 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 18632045 ps | ||
| T106 | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1686598432 | Mar 10 01:11:21 PM PDT 24 | Mar 10 01:11:22 PM PDT 24 | 26055691 ps | ||
| T44 | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2102954995 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 22835154 ps | ||
| T107 | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1552686123 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 98839065 ps | ||
| T108 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.367617292 | Mar 10 01:10:58 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 21655052 ps | ||
| T109 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.112401766 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 26072038 ps | ||
| T110 | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.835401718 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:04 PM PDT 24 | 51714351 ps | ||
| T111 | /workspace/coverage/cover_reg_top/16.i2c_intr_test.4003483626 | Mar 10 01:11:12 PM PDT 24 | Mar 10 01:11:13 PM PDT 24 | 30942441 ps | ||
| T59 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4225289291 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 215368089 ps | ||
| T112 | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2827083489 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 25241911 ps | ||
| T113 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.3283656918 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 26620580 ps | ||
| T114 | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4075219457 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 23552437 ps | ||
| T115 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3271901018 | Mar 10 01:11:10 PM PDT 24 | Mar 10 01:11:11 PM PDT 24 | 321086782 ps | ||
| T116 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1668924122 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:54 PM PDT 24 | 26335428 ps | ||
| T64 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3596453000 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 75521341 ps | ||
| T117 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2479984575 | Mar 10 01:11:00 PM PDT 24 | Mar 10 01:11:01 PM PDT 24 | 38687955 ps | ||
| T118 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.433406926 | Mar 10 01:11:06 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 52444224 ps | ||
| T119 | /workspace/coverage/cover_reg_top/25.i2c_intr_test.1698119260 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 53891831 ps | ||
| T45 | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.182288133 | Mar 10 01:10:58 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 66978127 ps | ||
| T120 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.119315959 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 34593706 ps | ||
| T121 | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2131445777 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:52 PM PDT 24 | 66083639 ps | ||
| T122 | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1938490851 | Mar 10 01:10:56 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 17890633 ps | ||
| T123 | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.926807233 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 89739676 ps | ||
| T124 | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3321442797 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 116468750 ps | ||
| T125 | /workspace/coverage/cover_reg_top/49.i2c_intr_test.4102000206 | Mar 10 01:11:16 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 20163295 ps | ||
| T126 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.258658981 | Mar 10 01:11:08 PM PDT 24 | Mar 10 01:11:11 PM PDT 24 | 590979265 ps | ||
| T127 | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1027397834 | Mar 10 01:11:10 PM PDT 24 | Mar 10 01:11:11 PM PDT 24 | 75720361 ps | ||
| T53 | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.497549942 | Mar 10 01:10:49 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 86828714 ps | ||
| T128 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2454455756 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:08 PM PDT 24 | 132378057 ps | ||
| T129 | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2994891838 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:22 PM PDT 24 | 34878605 ps | ||
| T130 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.2511333436 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 35802034 ps | ||
| T131 | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1484493054 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 25935841 ps | ||
| T132 | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2273950802 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 32418777 ps | ||
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| T134 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4042774118 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:53 PM PDT 24 | 80928141 ps | ||
| T135 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2756261763 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:56 PM PDT 24 | 219618387 ps | ||
| T136 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2671774185 | Mar 10 01:11:01 PM PDT 24 | Mar 10 01:11:02 PM PDT 24 | 24729557 ps | ||
| T137 | /workspace/coverage/cover_reg_top/1.i2c_intr_test.2921740900 | Mar 10 01:10:51 PM PDT 24 | Mar 10 01:10:52 PM PDT 24 | 46966861 ps | ||
| T138 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3257776004 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 25967278 ps | ||
| T139 | /workspace/coverage/cover_reg_top/19.i2c_intr_test.766565635 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:17 PM PDT 24 | 28825327 ps | ||
| T140 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4215454210 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:04 PM PDT 24 | 93099369 ps | ||
| T141 | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3995872870 | Mar 10 01:11:12 PM PDT 24 | Mar 10 01:11:14 PM PDT 24 | 83273011 ps | ||
| T142 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1695463289 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:06 PM PDT 24 | 513188676 ps | ||
| T143 | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2113854027 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 618735409 ps | ||
| T144 | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1589550817 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 44365472 ps | ||
| T48 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3415648657 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 127952620 ps | ||
| T145 | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.288437695 | Mar 10 01:10:58 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 86807639 ps | ||
| T146 | /workspace/coverage/cover_reg_top/45.i2c_intr_test.2459838212 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 44759207 ps | ||
| T147 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.312969537 | Mar 10 01:11:19 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 20299650 ps | ||
| T148 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2624095961 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 42237513 ps | ||
| T149 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.2715651411 | Mar 10 01:11:20 PM PDT 24 | Mar 10 01:11:21 PM PDT 24 | 15617421 ps | ||
| T150 | /workspace/coverage/cover_reg_top/4.i2c_intr_test.2905577708 | Mar 10 01:10:59 PM PDT 24 | Mar 10 01:11:00 PM PDT 24 | 17577236 ps | ||
| T49 | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3041666616 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 181208121 ps | ||
| T151 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1671208786 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:51 PM PDT 24 | 67181667 ps | ||
| T152 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.712828356 | Mar 10 01:10:54 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 107432945 ps | ||
| T153 | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2370172285 | Mar 10 01:11:14 PM PDT 24 | Mar 10 01:11:15 PM PDT 24 | 281822985 ps | ||
| T154 | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4267927435 | Mar 10 01:11:17 PM PDT 24 | Mar 10 01:11:19 PM PDT 24 | 29824170 ps | ||
| T50 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.636684930 | Mar 10 01:10:57 PM PDT 24 | Mar 10 01:10:58 PM PDT 24 | 33673399 ps | ||
| T155 | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3449168087 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 120282809 ps | ||
| T156 | /workspace/coverage/cover_reg_top/0.i2c_intr_test.521593835 | Mar 10 01:10:52 PM PDT 24 | Mar 10 01:10:53 PM PDT 24 | 16266555 ps | ||
| T157 | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2276492656 | Mar 10 01:11:04 PM PDT 24 | Mar 10 01:11:05 PM PDT 24 | 59269343 ps | ||
| T158 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.144822006 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:57 PM PDT 24 | 215604750 ps | ||
| T159 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.867093474 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:18 PM PDT 24 | 28876859 ps | ||
| T160 | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1908556416 | Mar 10 01:11:05 PM PDT 24 | Mar 10 01:11:07 PM PDT 24 | 26238812 ps | ||
| T161 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1502737988 | Mar 10 01:11:03 PM PDT 24 | Mar 10 01:11:04 PM PDT 24 | 45830552 ps | ||
| T162 | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1276685232 | Mar 10 01:11:02 PM PDT 24 | Mar 10 01:11:03 PM PDT 24 | 16843687 ps | ||
| T163 | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3974117361 | Mar 10 01:11:18 PM PDT 24 | Mar 10 01:11:20 PM PDT 24 | 20942785 ps | ||
| T164 | /workspace/coverage/cover_reg_top/3.i2c_intr_test.999862112 | Mar 10 01:10:55 PM PDT 24 | Mar 10 01:10:55 PM PDT 24 | 17724598 ps | ||
| T165 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.370463492 | Mar 10 01:10:56 PM PDT 24 | Mar 10 01:10:59 PM PDT 24 | 120913663 ps | ||
| T51 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4031070465 | Mar 10 01:10:50 PM PDT 24 | Mar 10 01:10:52 PM PDT 24 | 467516252 ps |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.681380357 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 116335350 ps |
| CPU time | 2.09 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:04 PM PDT 24 |
| Peak memory | 202924 kb |
| Host | smart-46e6d97a-56bd-4feb-9aa9-90f7999fda3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681380357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.681380357 |
| Directory | /workspace/9.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.3425767652 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 54255356 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202776 kb |
| Host | smart-1531d009-aa02-4dc1-bd01-93649f5ebcda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425767652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3425767652 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1086017646 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 190928256 ps |
| CPU time | 2.72 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-f48f682b-9830-468b-be13-264896249489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086017646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1086017646 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.3132896266 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 52255813 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202752 kb |
| Host | smart-1ff054d3-09d8-4323-a705-b63fcfa7816c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132896266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3132896266 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2913350476 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 27145570 ps |
| CPU time | 0.73 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 202788 kb |
| Host | smart-cdd61616-c5ed-4390-b2fe-97c458c5dc56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913350476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2913350476 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.3580909418 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 20005618 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:21 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-1ef2256a-3869-45dd-b74b-1cd4d7dc9f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580909418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3580909418 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2223125696 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 713715211 ps |
| CPU time | 1.09 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 202932 kb |
| Host | smart-211b496c-88b2-4cc8-a39e-385f408ac591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223125696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.2223125696 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2791257185 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 79233474 ps |
| CPU time | 1.53 seconds |
| Started | Mar 10 01:10:53 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202828 kb |
| Host | smart-74c26eef-1240-4458-a812-f2a3967dd472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791257185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2791257185 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3626796384 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 78109512 ps |
| CPU time | 0.97 seconds |
| Started | Mar 10 01:11:07 PM PDT 24 |
| Finished | Mar 10 01:11:08 PM PDT 24 |
| Peak memory | 202952 kb |
| Host | smart-995dbb72-1d87-4175-9f85-8f2e695af6e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626796384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3626796384 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1357719160 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 484675758 ps |
| CPU time | 2.05 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 203012 kb |
| Host | smart-845f0de4-f864-4617-a275-8bc7c14fc9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357719160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1357719160 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.3253067696 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 55744440 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202704 kb |
| Host | smart-8ca0747d-d2d5-4e92-b9bd-c416461e5650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253067696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3253067696 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.784033113 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 241111931 ps |
| CPU time | 2.43 seconds |
| Started | Mar 10 01:10:49 PM PDT 24 |
| Finished | Mar 10 01:10:52 PM PDT 24 |
| Peak memory | 202992 kb |
| Host | smart-da76f0e9-54d9-4db0-8890-889ba0240084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784033113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.784033113 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1460047780 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 30533431 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 202740 kb |
| Host | smart-073540d1-8b6f-4365-ac89-27d6b9204fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460047780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1460047780 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4031070465 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 467516252 ps |
| CPU time | 1.55 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:52 PM PDT 24 |
| Peak memory | 202852 kb |
| Host | smart-1532c5fb-3ccd-4f6d-9fc4-b16b9b262bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031070465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4031070465 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3677144379 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 70419471 ps |
| CPU time | 1.29 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-47b34542-ba3b-4dcb-8985-38bac5a37533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677144379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3677144379 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.302408117 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 43344634 ps |
| CPU time | 1.04 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 202896 kb |
| Host | smart-1111af5a-48ef-43ee-b178-61108ace5647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302408117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.302408117 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2756261763 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 219618387 ps |
| CPU time | 4.16 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 202980 kb |
| Host | smart-961990d8-cc6b-4839-80a8-b6e93793a50f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756261763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2756261763 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.806399308 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 81058752 ps |
| CPU time | 1.12 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 203156 kb |
| Host | smart-7cef32ca-87c5-4cd1-9b24-4ce515a10dc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806399308 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.806399308 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.402137551 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 155875635 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:10:49 PM PDT 24 |
| Finished | Mar 10 01:10:50 PM PDT 24 |
| Peak memory | 202776 kb |
| Host | smart-492c467c-5a7e-4f75-8a01-71d3ebb837d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402137551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.402137551 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.521593835 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 16266555 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:53 PM PDT 24 |
| Peak memory | 202820 kb |
| Host | smart-5f2d5091-7c55-4d31-be36-8ead06967ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521593835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.521593835 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4225289291 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 215368089 ps |
| CPU time | 1.96 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 203060 kb |
| Host | smart-075784fc-24ed-4cc2-8a27-bb984580a4c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225289291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4225289291 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3415648657 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 127952620 ps |
| CPU time | 1.45 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 203012 kb |
| Host | smart-50a5d9be-d770-4178-98da-250a9bd15820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415648657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3415648657 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2301460315 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1597392084 ps |
| CPU time | 4.73 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-5568f34e-4499-4ad8-8499-0da223851193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301460315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2301460315 |
| Directory | /workspace/1.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3035082458 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 26102524 ps |
| CPU time | 0.77 seconds |
| Started | Mar 10 01:10:51 PM PDT 24 |
| Finished | Mar 10 01:10:52 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-0d0cb455-51e8-4913-a1e8-d5c9950dffbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035082458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3035082458 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1668924122 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 26335428 ps |
| CPU time | 0.77 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:54 PM PDT 24 |
| Peak memory | 202364 kb |
| Host | smart-5bf23424-5274-4876-b9d5-154efff179e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668924122 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1668924122 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3137894682 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 83259779 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 202556 kb |
| Host | smart-9fb7b8c5-59b7-4539-a2f7-8410fd3e15ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137894682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3137894682 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.2921740900 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 46966861 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:10:51 PM PDT 24 |
| Finished | Mar 10 01:10:52 PM PDT 24 |
| Peak memory | 202780 kb |
| Host | smart-43c5e504-434c-41e1-86dc-5f5e6ad1696c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921740900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2921740900 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3979019219 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 96797782 ps |
| CPU time | 1.02 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:53 PM PDT 24 |
| Peak memory | 203080 kb |
| Host | smart-a66fb1a0-137a-43b5-b046-4f3a115983e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979019219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.3979019219 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2131445777 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 66083639 ps |
| CPU time | 1.69 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:52 PM PDT 24 |
| Peak memory | 202952 kb |
| Host | smart-6644dfdf-9c33-44d5-988b-c960a4510654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131445777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2131445777 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1671208786 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 67181667 ps |
| CPU time | 1.25 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 202924 kb |
| Host | smart-b8f558d1-f1d9-40e3-a71d-d28831137b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671208786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1671208786 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3931934685 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 129908972 ps |
| CPU time | 1.28 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 203080 kb |
| Host | smart-f8a2655f-43e0-41e1-95e4-931858e1bce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931934685 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3931934685 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2671774185 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 24729557 ps |
| CPU time | 0.72 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 202788 kb |
| Host | smart-b4a51aa5-660a-4f8a-b1e7-8568bd555f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671774185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2671774185 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1502737988 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 45830552 ps |
| CPU time | 0.84 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:04 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-580335b8-1bfa-43fc-aabc-0d5bf75cae15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502737988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.1502737988 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1345175519 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 31131793 ps |
| CPU time | 1.54 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:04 PM PDT 24 |
| Peak memory | 203176 kb |
| Host | smart-ce33eede-6857-4cc4-80b1-b74b1e1688ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345175519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1345175519 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4215454210 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 93099369 ps |
| CPU time | 1.26 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:04 PM PDT 24 |
| Peak memory | 203140 kb |
| Host | smart-9d4166e8-7c70-4131-875b-0998168cf145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215454210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4215454210 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.326128181 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 115202166 ps |
| CPU time | 0.95 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 202820 kb |
| Host | smart-301e97c9-7f53-45ae-86ba-01287dd10b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326128181 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.326128181 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3068610992 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 26877933 ps |
| CPU time | 0.76 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202628 kb |
| Host | smart-217a2499-eb98-44a0-9058-d5a2f41bc4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068610992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3068610992 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.4224290358 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 21741891 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-0c4dfd62-3f50-4c0b-b2e6-729050cbcbd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224290358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.4224290358 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2922301335 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 196119090 ps |
| CPU time | 1.02 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-eb572abc-1170-4fe5-86ca-d4cb6a3a1c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922301335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.2922301335 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.835401718 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 51714351 ps |
| CPU time | 1.22 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:04 PM PDT 24 |
| Peak memory | 203012 kb |
| Host | smart-432a35c0-dfa2-4c00-aa9e-e4e0a04c009d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835401718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.835401718 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.299278423 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 158179527 ps |
| CPU time | 2.05 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-9ef55d3e-7bba-433f-a460-a1dcc2ed04bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299278423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.299278423 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3449168087 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 120282809 ps |
| CPU time | 0.95 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202928 kb |
| Host | smart-72ad29cd-31e5-4081-a791-1990dfad2290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449168087 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3449168087 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.433406926 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 52444224 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202656 kb |
| Host | smart-563f3352-23bd-4d49-a16e-eee7d36b8d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433406926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.433406926 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2760850810 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 121402991 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-048533b2-a11e-484e-91ce-d61e93ab9947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760850810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2760850810 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3596453000 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 75521341 ps |
| CPU time | 1.03 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-48647241-718a-4539-8ff1-4edfb7afbc5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596453000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.3596453000 |
| Directory | /workspace/12.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2454455756 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 132378057 ps |
| CPU time | 2.58 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:08 PM PDT 24 |
| Peak memory | 203016 kb |
| Host | smart-5013bf71-3fcd-4816-9ac8-a5f6b010beb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454455756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2454455756 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3034502889 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 443781069 ps |
| CPU time | 1.91 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:08 PM PDT 24 |
| Peak memory | 202952 kb |
| Host | smart-29543d05-6f3f-4192-949d-545013a03e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034502889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3034502889 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1484493054 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 25935841 ps |
| CPU time | 0.84 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 202876 kb |
| Host | smart-072c009c-85a5-434a-bc02-d26458d8dfd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484493054 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1484493054 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3618360335 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 18609188 ps |
| CPU time | 0.72 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202668 kb |
| Host | smart-132dba07-678f-4370-a38e-caedefb78ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618360335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3618360335 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.2772420901 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 17300041 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-afd9945d-967a-4b73-88e7-bdaf09aa0062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772420901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2772420901 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3305293187 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 814545007 ps |
| CPU time | 1.64 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-d8dc9972-2264-497f-a474-8e195e6f3ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305293187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3305293187 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.765893042 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 70385136 ps |
| CPU time | 1.3 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 203148 kb |
| Host | smart-d85fed5f-5cd9-4c07-b14e-e1434dd54be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765893042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.765893042 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1921354930 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 68731458 ps |
| CPU time | 0.74 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-db34ec56-a495-41bb-956e-4978ce0db8ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921354930 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1921354930 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4065663195 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 66267717 ps |
| CPU time | 0.77 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-5f8a752a-776c-4640-a695-e7443286dcb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065663195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4065663195 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.3613563966 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 30151978 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:11:06 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202784 kb |
| Host | smart-b34f01c9-1f0f-4866-8a99-f0dcf35d09c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613563966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3613563966 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2276492656 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 59269343 ps |
| CPU time | 0.79 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202756 kb |
| Host | smart-3a769b2b-0396-4d9f-bb80-e9347408bd1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276492656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.2276492656 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2321527935 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 85051203 ps |
| CPU time | 1.59 seconds |
| Started | Mar 10 01:11:08 PM PDT 24 |
| Finished | Mar 10 01:11:10 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-d41586be-9369-45c4-8b75-de1b67c53957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321527935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2321527935 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1695463289 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 513188676 ps |
| CPU time | 2.04 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 203068 kb |
| Host | smart-fd8a3c60-56ee-4e8c-b8d9-3aa1f0ebb098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695463289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1695463289 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4267927435 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 29824170 ps |
| CPU time | 1.29 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 203072 kb |
| Host | smart-65119166-a041-4f9d-bed2-587f8603a1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267927435 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.4267927435 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1908556416 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 26238812 ps |
| CPU time | 0.78 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202768 kb |
| Host | smart-6da34fd8-566b-4665-b5ca-866904abbc1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908556416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1908556416 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.333014450 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 19468506 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:05 PM PDT 24 |
| Finished | Mar 10 01:11:07 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-cd6e4d0c-e9ad-41cf-be37-4b775bb1c760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333014450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.333014450 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.935218264 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 19322515 ps |
| CPU time | 0.76 seconds |
| Started | Mar 10 01:11:09 PM PDT 24 |
| Finished | Mar 10 01:11:10 PM PDT 24 |
| Peak memory | 202820 kb |
| Host | smart-815bda20-cdf4-4991-acfc-41fe85b9b41c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935218264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou tstanding.935218264 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.258658981 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 590979265 ps |
| CPU time | 2.76 seconds |
| Started | Mar 10 01:11:08 PM PDT 24 |
| Finished | Mar 10 01:11:11 PM PDT 24 |
| Peak memory | 203020 kb |
| Host | smart-3e1e37ff-b425-451e-81e4-d9007ef6221b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258658981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.258658981 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3271901018 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 321086782 ps |
| CPU time | 0.8 seconds |
| Started | Mar 10 01:11:10 PM PDT 24 |
| Finished | Mar 10 01:11:11 PM PDT 24 |
| Peak memory | 202964 kb |
| Host | smart-0e955602-dae3-482a-8470-acc10c4ffb24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271901018 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3271901018 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3041666616 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 181208121 ps |
| CPU time | 0.77 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202644 kb |
| Host | smart-6f5f6283-351b-4f24-a38a-7e7ee14159e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041666616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3041666616 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.4003483626 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 30942441 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:12 PM PDT 24 |
| Finished | Mar 10 01:11:13 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-14c95b0b-e2fe-4880-9328-bc6cab463864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003483626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4003483626 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2827083489 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 25241911 ps |
| CPU time | 0.8 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-031df624-8e47-474a-9555-9a4fa857ba6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827083489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.2827083489 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1802847429 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 42669960 ps |
| CPU time | 2.13 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-528fd0d7-29ae-441d-aba2-9aafbf94df3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802847429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1802847429 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1027397834 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 75720361 ps |
| CPU time | 1.29 seconds |
| Started | Mar 10 01:11:10 PM PDT 24 |
| Finished | Mar 10 01:11:11 PM PDT 24 |
| Peak memory | 202940 kb |
| Host | smart-3eb2d71f-bb67-458f-8102-f5d4307d1adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027397834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1027397834 |
| Directory | /workspace/16.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1508810882 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 220997614 ps |
| CPU time | 0.84 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202860 kb |
| Host | smart-bfc2ad95-affe-4acc-8fca-62be967c3998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508810882 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1508810882 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2432326499 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 59565151 ps |
| CPU time | 0.73 seconds |
| Started | Mar 10 01:11:12 PM PDT 24 |
| Finished | Mar 10 01:11:13 PM PDT 24 |
| Peak memory | 202652 kb |
| Host | smart-ac4c700a-87e5-4642-9fbb-1e02c320b241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432326499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2432326499 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2676879242 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 37625707 ps |
| CPU time | 0.82 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202744 kb |
| Host | smart-d9075e01-d0b0-4143-b85f-45126e673f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676879242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.2676879242 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2994891838 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 34878605 ps |
| CPU time | 1.69 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:22 PM PDT 24 |
| Peak memory | 203008 kb |
| Host | smart-3bbc07e4-4ff6-4fee-82ee-0e7f4307138d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994891838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2994891838 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2370172285 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 281822985 ps |
| CPU time | 1.36 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 203104 kb |
| Host | smart-fe40bedb-6048-4714-8507-597b68c39051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370172285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2370172285 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1821389178 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 128854145 ps |
| CPU time | 1.01 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202808 kb |
| Host | smart-e4499521-7bd7-4a3d-9a82-de396b9fe8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821389178 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1821389178 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3974117361 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 20942785 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202680 kb |
| Host | smart-0a3b5e24-12e3-4eb8-a78c-9e3bc58110aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974117361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3974117361 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.554297219 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 19695792 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202760 kb |
| Host | smart-cda2ab86-5452-4871-bd38-5dc7bf4b546a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554297219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.554297219 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2078974119 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 136810580 ps |
| CPU time | 1 seconds |
| Started | Mar 10 01:11:15 PM PDT 24 |
| Finished | Mar 10 01:11:16 PM PDT 24 |
| Peak memory | 202936 kb |
| Host | smart-090a3fe7-ebfe-4d31-954e-078003ab3b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078974119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2078974119 |
| Directory | /workspace/18.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3408875418 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 191058865 ps |
| CPU time | 2.39 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202992 kb |
| Host | smart-1839a212-9b53-423e-ba51-09a3961a363a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408875418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3408875418 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3995872870 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 83273011 ps |
| CPU time | 1.19 seconds |
| Started | Mar 10 01:11:12 PM PDT 24 |
| Finished | Mar 10 01:11:14 PM PDT 24 |
| Peak memory | 202912 kb |
| Host | smart-7a8aeee3-c0f9-42be-b736-8998890c2658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995872870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3995872870 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2624095961 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 42237513 ps |
| CPU time | 0.77 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-7e6f0f6a-2625-4d72-a981-3d315f16da6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624095961 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2624095961 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2393695783 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 39459682 ps |
| CPU time | 0.73 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-5e220de1-f290-479c-8ed6-0461bc4d5e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393695783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2393695783 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.766565635 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 28825327 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202800 kb |
| Host | smart-6e43c139-6da6-4b40-a825-e10bf00b5de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766565635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.766565635 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3385918576 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 56125787 ps |
| CPU time | 0.86 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202796 kb |
| Host | smart-bee9a117-ad41-4976-b057-34fb97eda79e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385918576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.3385918576 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.616116310 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 345271094 ps |
| CPU time | 1.77 seconds |
| Started | Mar 10 01:11:12 PM PDT 24 |
| Finished | Mar 10 01:11:14 PM PDT 24 |
| Peak memory | 203032 kb |
| Host | smart-06f2344a-bb84-4b76-bb40-4b30afb68160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616116310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.616116310 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2747539947 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 377423117 ps |
| CPU time | 3.92 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:58 PM PDT 24 |
| Peak memory | 202500 kb |
| Host | smart-81563606-8e51-4422-b6ee-c2e36fc628de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747539947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2747539947 |
| Directory | /workspace/2.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.112401766 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 26072038 ps |
| CPU time | 1.2 seconds |
| Started | Mar 10 01:10:50 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 203204 kb |
| Host | smart-ed026308-9de8-4e50-9b90-7ca67424db00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112401766 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.112401766 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.818335201 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 16434778 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:54 PM PDT 24 |
| Peak memory | 202628 kb |
| Host | smart-6e652399-1d53-41a3-b60e-929f48c02964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818335201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.818335201 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1938490851 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 17890633 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:10:56 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 202784 kb |
| Host | smart-9390eaa3-9f42-45ea-afd3-a5a02e935d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938490851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1938490851 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4042774118 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 80928141 ps |
| CPU time | 0.96 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:53 PM PDT 24 |
| Peak memory | 203028 kb |
| Host | smart-02a05480-50b2-467e-a848-9b5277b3e24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042774118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.4042774118 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1559375120 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 68678946 ps |
| CPU time | 1.32 seconds |
| Started | Mar 10 01:10:48 PM PDT 24 |
| Finished | Mar 10 01:10:50 PM PDT 24 |
| Peak memory | 203008 kb |
| Host | smart-e8f549b8-f23d-4efd-b0e2-0a39978d4fce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559375120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1559375120 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.497549942 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 86828714 ps |
| CPU time | 1.27 seconds |
| Started | Mar 10 01:10:49 PM PDT 24 |
| Finished | Mar 10 01:10:51 PM PDT 24 |
| Peak memory | 203016 kb |
| Host | smart-9d1d7622-a1a8-4fbd-8248-1e2ddf3c7218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497549942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.497549942 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2435635466 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 18002658 ps |
| CPU time | 0.7 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202800 kb |
| Host | smart-fc4423ea-a438-4ab3-a9b0-b0688efc2d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435635466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2435635466 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.1327111089 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 61728460 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:11 PM PDT 24 |
| Finished | Mar 10 01:11:12 PM PDT 24 |
| Peak memory | 202620 kb |
| Host | smart-f3735f51-5533-479f-b962-f9a09e034c3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327111089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1327111089 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.1279775374 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 19316513 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202720 kb |
| Host | smart-51ddc459-b33e-420d-94b3-9711d7186ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279775374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1279775374 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.4121970080 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 19364951 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202704 kb |
| Host | smart-8a09e466-9321-4262-9eed-b74b0ad3ff83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121970080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4121970080 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.1698119260 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 53891831 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-7be28c42-fffc-4d77-b774-f781a1ed4b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698119260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1698119260 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.127572511 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 23472204 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:14 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202664 kb |
| Host | smart-7f51dbee-53d5-4279-8a76-3472d6387c7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127572511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.127572511 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.758731280 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 25397318 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-8253b1b0-0108-4154-a557-a701452ec574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758731280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.758731280 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.3628845164 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 50365688 ps |
| CPU time | 0.63 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202776 kb |
| Host | smart-43ca65bd-0545-4b44-b0a4-bd0aae0804f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628845164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3628845164 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1187457767 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 15223347 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-cd985de4-76c2-48d2-bee7-3b99279bc3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187457767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1187457767 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4089966855 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 394810781 ps |
| CPU time | 4.16 seconds |
| Started | Mar 10 01:10:56 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 203012 kb |
| Host | smart-6dc48c7c-6650-46c3-bd66-d35fe9b02956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089966855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.4089966855 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1119726846 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25610614 ps |
| CPU time | 0.79 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202764 kb |
| Host | smart-f988e9ea-9771-47dd-9f3a-a41b484cfacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119726846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1119726846 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.712828356 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 107432945 ps |
| CPU time | 0.8 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-0d242ce6-b7e0-4cc7-9059-a98cb73e1041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712828356 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.712828356 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1589550817 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 44365472 ps |
| CPU time | 0.7 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-7e376872-26f6-40e1-87bc-775ecb287fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589550817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1589550817 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.999862112 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 17724598 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-81a2bf93-4f5b-4ce4-88e9-5addd11ead59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999862112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.999862112 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3306884660 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 72130145 ps |
| CPU time | 0.99 seconds |
| Started | Mar 10 01:10:56 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 202980 kb |
| Host | smart-a96429ad-411c-4631-bd38-7192e66e38b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306884660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.3306884660 |
| Directory | /workspace/3.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.334898064 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 128389435 ps |
| CPU time | 1.91 seconds |
| Started | Mar 10 01:10:56 PM PDT 24 |
| Finished | Mar 10 01:10:58 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-39b28ecd-d33c-41a0-81a0-84dac4b845f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334898064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.334898064 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1224000978 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 282030863 ps |
| CPU time | 1.37 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 202984 kb |
| Host | smart-0627b878-934d-4799-9264-8da751989505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224000978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1224000978 |
| Directory | /workspace/3.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.312969537 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 20299650 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202756 kb |
| Host | smart-00c2ba93-34b6-456f-a710-90997f9b9e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312969537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.312969537 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.119315959 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 34593706 ps |
| CPU time | 0.64 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-586f91ac-2010-4233-86b8-7d913cf17f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119315959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.119315959 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.3905660158 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 46522935 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202732 kb |
| Host | smart-17e51781-e218-4390-bea7-d3143cad1b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905660158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3905660158 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.1115128231 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 65043742 ps |
| CPU time | 0.74 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202740 kb |
| Host | smart-cbd41155-b7a3-4f97-bb79-061b7007f3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115128231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1115128231 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.3799376830 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 50400377 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202716 kb |
| Host | smart-7b1fc1b5-b60c-4073-8153-400f14480502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799376830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3799376830 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.2511333436 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 35802034 ps |
| CPU time | 0.6 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-7cc93cdb-54b8-4638-ae90-770704729c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511333436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2511333436 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.3211813812 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 39490124 ps |
| CPU time | 0.63 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202800 kb |
| Host | smart-42d892e8-33f8-49e8-8890-e5df3dda4c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211813812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3211813812 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.2715651411 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 15617421 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:20 PM PDT 24 |
| Finished | Mar 10 01:11:21 PM PDT 24 |
| Peak memory | 202796 kb |
| Host | smart-d7a68cec-cec2-495e-bf64-f0ef5a73a18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715651411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2715651411 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1686598432 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 26055691 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:21 PM PDT 24 |
| Finished | Mar 10 01:11:22 PM PDT 24 |
| Peak memory | 202776 kb |
| Host | smart-7c72f952-167b-4649-9b71-7a7c45f53655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686598432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1686598432 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.4197626315 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 98689855 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:11:15 PM PDT 24 |
| Finished | Mar 10 01:11:15 PM PDT 24 |
| Peak memory | 202756 kb |
| Host | smart-78932867-0fca-45a6-9059-76377babea99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197626315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4197626315 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.797430517 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 41937763 ps |
| CPU time | 1.07 seconds |
| Started | Mar 10 01:10:57 PM PDT 24 |
| Finished | Mar 10 01:10:58 PM PDT 24 |
| Peak memory | 202936 kb |
| Host | smart-09bde311-3f5c-41b9-badf-4aeca7dcd5c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797430517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.797430517 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2113854027 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 618735409 ps |
| CPU time | 2.62 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 202960 kb |
| Host | smart-6be0762c-4249-428e-b270-55f8979e4df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113854027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2113854027 |
| Directory | /workspace/4.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.636684930 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 33673399 ps |
| CPU time | 0.75 seconds |
| Started | Mar 10 01:10:57 PM PDT 24 |
| Finished | Mar 10 01:10:58 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-6122aa86-cbcf-4484-ada7-46e5ae41632a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636684930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.636684930 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.621326951 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 37835591 ps |
| CPU time | 0.94 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202804 kb |
| Host | smart-78684fc6-1481-4702-a683-e54b77f25b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621326951 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.621326951 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1231780679 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 40356353 ps |
| CPU time | 0.79 seconds |
| Started | Mar 10 01:10:58 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202608 kb |
| Host | smart-8970f852-8a8a-4ffd-b797-80d5555a66fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231780679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1231780679 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.2905577708 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 17577236 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:10:59 PM PDT 24 |
| Finished | Mar 10 01:11:00 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-5eade6d3-0f92-4ad3-aaba-ab5521b9b4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905577708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2905577708 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.367617292 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 21655052 ps |
| CPU time | 0.82 seconds |
| Started | Mar 10 01:10:58 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202736 kb |
| Host | smart-9b379a71-c094-4d6e-ac57-4cb8f7cf800a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367617292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out standing.367617292 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.370463492 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 120913663 ps |
| CPU time | 2.35 seconds |
| Started | Mar 10 01:10:56 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 203112 kb |
| Host | smart-1b08a8fa-22c6-4b50-bfdc-d1dd0b7c2e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370463492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.370463492 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4116780664 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 806645153 ps |
| CPU time | 1.4 seconds |
| Started | Mar 10 01:10:57 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-2a0efb0f-fc59-48a9-b0a9-12045aa44993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116780664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4116780664 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3257776004 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 25967278 ps |
| CPU time | 0.64 seconds |
| Started | Mar 10 01:11:19 PM PDT 24 |
| Finished | Mar 10 01:11:20 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-20e73275-2a92-409a-adab-eb5a45ae0016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257776004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3257776004 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.962497024 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 18222053 ps |
| CPU time | 0.69 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-6422e16b-d8ca-4ce3-a01a-6021f768bfe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962497024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.962497024 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.4188373800 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 204550703 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202604 kb |
| Host | smart-ba84b93c-3723-44b1-85dd-9dc291d706c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188373800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4188373800 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.3283656918 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 26620580 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202648 kb |
| Host | smart-3d77c26b-b011-401a-96dd-3be2d39e0829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283656918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3283656918 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.2459838212 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 44759207 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:19 PM PDT 24 |
| Peak memory | 202724 kb |
| Host | smart-062f5c29-9300-4a03-a9c3-19e852ec4e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459838212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2459838212 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2273950802 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 32418777 ps |
| CPU time | 0.65 seconds |
| Started | Mar 10 01:11:17 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202408 kb |
| Host | smart-506eea73-da86-448d-a5be-1320e7529985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273950802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2273950802 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.867093474 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 28876859 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:18 PM PDT 24 |
| Finished | Mar 10 01:11:18 PM PDT 24 |
| Peak memory | 202596 kb |
| Host | smart-79ddc888-3927-4ef7-b07f-2026a9020609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867093474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.867093474 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.339206682 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 90723631 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:21 PM PDT 24 |
| Finished | Mar 10 01:11:22 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-73ac9e3c-0ed2-468e-9235-da4c0ecbac12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339206682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.339206682 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.4102000206 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 20163295 ps |
| CPU time | 0.67 seconds |
| Started | Mar 10 01:11:16 PM PDT 24 |
| Finished | Mar 10 01:11:17 PM PDT 24 |
| Peak memory | 202728 kb |
| Host | smart-a42d7f83-4d48-43e7-ab1a-10a76a7d2fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102000206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4102000206 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3133323192 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30439633 ps |
| CPU time | 0.9 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:53 PM PDT 24 |
| Peak memory | 202896 kb |
| Host | smart-79a4956a-ee54-462b-86cf-a888c75083cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133323192 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3133323192 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.288437695 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 86807639 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:10:58 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202796 kb |
| Host | smart-b81da28b-922f-4897-9a67-6bfebfa1886c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288437695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.288437695 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2109427964 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 49051995 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202748 kb |
| Host | smart-3c5091d0-8483-4023-a256-37fc2e490a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109427964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2109427964 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3886679955 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 86709616 ps |
| CPU time | 1.06 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:56 PM PDT 24 |
| Peak memory | 202992 kb |
| Host | smart-fcaae3cb-d36d-4b3a-b5b8-fefd2adbe760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886679955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.3886679955 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2789434703 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 358688839 ps |
| CPU time | 2.43 seconds |
| Started | Mar 10 01:10:57 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202956 kb |
| Host | smart-9ee0bdf5-0d5f-438c-980a-809acdb38305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789434703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2789434703 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1205152919 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 37056766 ps |
| CPU time | 0.75 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202928 kb |
| Host | smart-cd3c89f0-8293-4a19-b233-2dd057354d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205152919 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1205152919 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.182288133 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 66978127 ps |
| CPU time | 0.72 seconds |
| Started | Mar 10 01:10:58 PM PDT 24 |
| Finished | Mar 10 01:10:59 PM PDT 24 |
| Peak memory | 202808 kb |
| Host | smart-553a411e-7172-4b5a-a191-34ab8794e288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182288133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.182288133 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.2452404014 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28780232 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:10:54 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-ed4fb3b4-eaa6-4037-8d80-9d06f90be721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452404014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2452404014 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4294025073 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 96539193 ps |
| CPU time | 0.82 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202784 kb |
| Host | smart-a4d4cd94-6fe3-47a4-a002-76d900d29b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294025073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.4294025073 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.144822006 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 215604750 ps |
| CPU time | 1.24 seconds |
| Started | Mar 10 01:10:55 PM PDT 24 |
| Finished | Mar 10 01:10:57 PM PDT 24 |
| Peak memory | 202936 kb |
| Host | smart-67aa579c-80f3-462d-bf7e-ba23d85e7fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144822006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.144822006 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1072007642 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 232264532 ps |
| CPU time | 2.01 seconds |
| Started | Mar 10 01:10:52 PM PDT 24 |
| Finished | Mar 10 01:10:55 PM PDT 24 |
| Peak memory | 202924 kb |
| Host | smart-a55bc389-eb47-4e00-8d58-5a648beff7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072007642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1072007642 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.926807233 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 89739676 ps |
| CPU time | 1.44 seconds |
| Started | Mar 10 01:11:04 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 203044 kb |
| Host | smart-b0076241-16df-4ff8-a7b3-ecf79df46364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926807233 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.926807233 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.681754632 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 18632045 ps |
| CPU time | 0.72 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-572b34f6-7f47-4e3e-b392-8ea13ec192ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681754632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.681754632 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.1173910917 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 59953443 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-d83f3933-c0fd-4310-8a53-05c4ce327598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173910917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1173910917 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4075219457 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 23552437 ps |
| CPU time | 1.01 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202944 kb |
| Host | smart-30844bed-effa-415e-8ad4-56aa773d6ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075219457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.4075219457 |
| Directory | /workspace/7.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.29374356 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 44172597 ps |
| CPU time | 1.28 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:03 PM PDT 24 |
| Peak memory | 202984 kb |
| Host | smart-5fb93827-803d-4d5c-8432-f6d818fbda09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29374356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.29374356 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1764377030 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 363354666 ps |
| CPU time | 2.05 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:06 PM PDT 24 |
| Peak memory | 203064 kb |
| Host | smart-ee1571b2-a28b-4b79-823a-0be09db24757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764377030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1764377030 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2479984575 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 38687955 ps |
| CPU time | 0.79 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202864 kb |
| Host | smart-e6c8d2c3-1a41-48e0-808b-b961bc126491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479984575 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2479984575 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.317385484 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 18813987 ps |
| CPU time | 0.78 seconds |
| Started | Mar 10 01:10:59 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-dcd9b99a-3438-4128-b10a-4e03f0069fd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317385484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.317385484 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3857194386 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19086456 ps |
| CPU time | 0.66 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 202756 kb |
| Host | smart-21338e44-0dda-4907-9ac1-bf4e652cb4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857194386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3857194386 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3321442797 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 116468750 ps |
| CPU time | 0.85 seconds |
| Started | Mar 10 01:11:03 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 202808 kb |
| Host | smart-7e317179-1daa-48b5-8543-eb4f2488b603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321442797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.3321442797 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2040962629 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 206107435 ps |
| CPU time | 1.49 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 203040 kb |
| Host | smart-221fd60d-0108-48e3-89b4-c175f8258afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040962629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2040962629 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1998697186 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 212926604 ps |
| CPU time | 2.07 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:03 PM PDT 24 |
| Peak memory | 202940 kb |
| Host | smart-b2218bee-11d0-4449-aeaf-77accd0f4fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998697186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1998697186 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2229644273 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 26109373 ps |
| CPU time | 1.08 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:03 PM PDT 24 |
| Peak memory | 202960 kb |
| Host | smart-ace560c5-2f25-4100-a3c3-abe5dc6ffc17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229644273 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2229644273 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2102954995 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 22835154 ps |
| CPU time | 0.71 seconds |
| Started | Mar 10 01:11:00 PM PDT 24 |
| Finished | Mar 10 01:11:01 PM PDT 24 |
| Peak memory | 201728 kb |
| Host | smart-ef7d7296-a232-4d47-85f5-8b4989f587f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102954995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2102954995 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1276685232 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 16843687 ps |
| CPU time | 0.68 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:03 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-cac01efe-0f2c-42b1-81d1-9ac77e8c8b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276685232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1276685232 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2313207820 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 133380438 ps |
| CPU time | 0.88 seconds |
| Started | Mar 10 01:11:01 PM PDT 24 |
| Finished | Mar 10 01:11:02 PM PDT 24 |
| Peak memory | 202780 kb |
| Host | smart-a75c5d1c-0234-4ea0-9bfd-e57f1c30ab43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313207820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.2313207820 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1552686123 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 98839065 ps |
| CPU time | 1.45 seconds |
| Started | Mar 10 01:11:02 PM PDT 24 |
| Finished | Mar 10 01:11:05 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-9dfe7f8c-52d8-44c7-bd52-fe1c31a282f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552686123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1552686123 |
| Directory | /workspace/9.i2c_tl_errors/latest |
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