Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T3	4		T7	4		T8	7
all_values[1]	278	1			T3	4		T7	4		T8	7
all_values[2]	278	1			T3	4		T7	4		T8	7
all_values[3]	278	1			T3	4		T7	4		T8	7
all_values[4]	278	1			T3	4		T7	4		T8	7
all_values[5]	278	1			T3	4		T7	4		T8	7
all_values[6]	278	1			T3	4		T7	4		T8	7
all_values[7]	278	1			T3	4		T7	4		T8	7
all_values[8]	278	1			T3	4		T7	4		T8	7
all_values[9]	278	1			T3	4		T7	4		T8	7
all_values[10]	278	1			T3	4		T7	4		T8	7
all_values[11]	278	1			T3	4		T7	4		T8	7
all_values[12]	278	1			T3	4		T7	4		T8	7
all_values[13]	278	1			T3	4		T7	4		T8	7
all_values[14]	278	1			T3	4		T7	4		T8	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T3

37

T7

35

T8

59

auto[1]

1876

1

T3

23

T7

25

T8

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772

1

T3

10

T7

7

T8

13

auto[1]

3398

1

T3

50

T7

53

T8

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2479

1

T3

39

T7

31

T8

62

auto[1]

1691

1

T3

21

T7

29

T8

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1			T3	1		T70	1		T71	1
all_values[0]	auto[0]	auto[0]	auto[1]	51	1			T7	2		T8	3		T11	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1			T70	1		T72	3		T73	3
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T3	1		T7	1		T11	2
all_values[0]	auto[1]	auto[0]	auto[1]	58	1			T7	1		T8	1		T11	2
all_values[0]	auto[1]	auto[1]	auto[1]	61	1			T3	2		T8	3		T11	2
all_values[1]	auto[0]	auto[0]	auto[0]	29	1			T11	1		T12	3		T46	1
all_values[1]	auto[0]	auto[0]	auto[1]	60	1			T3	3		T8	2		T11	2
all_values[1]	auto[0]	auto[1]	auto[0]	13	1			T12	1		T71	1		T74	2
all_values[1]	auto[0]	auto[1]	auto[1]	53	1			T7	2		T8	1		T11	1
all_values[1]	auto[1]	auto[0]	auto[1]	69	1			T3	1		T7	1		T8	4
all_values[1]	auto[1]	auto[1]	auto[1]	54	1			T7	1		T11	2		T52	2
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T3	1		T7	1		T8	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T7	1		T8	1		T11	1
all_values[2]	auto[0]	auto[1]	auto[0]	13	1			T71	1		T75	1		T76	1
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T3	2		T8	2		T11	1
all_values[2]	auto[1]	auto[0]	auto[1]	55	1			T11	3		T12	2		T22	1
all_values[2]	auto[1]	auto[1]	auto[1]	51	1			T3	1		T7	2		T8	3
all_values[3]	auto[0]	auto[0]	auto[0]	26	1			T7	2		T8	1		T11	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1			T3	1		T8	1		T11	1
all_values[3]	auto[0]	auto[1]	auto[0]	15	1			T22	2		T37	2		T71	1
all_values[3]	auto[0]	auto[1]	auto[1]	63	1			T3	1		T7	1		T8	3
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T3	1		T7	1		T8	1
all_values[3]	auto[1]	auto[1]	auto[1]	50	1			T3	1		T8	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[0]	32	1			T3	2		T7	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T3	1		T8	2		T11	4
all_values[4]	auto[0]	auto[1]	auto[0]	17	1			T12	1		T71	3		T77	1
all_values[4]	auto[0]	auto[1]	auto[1]	46	1			T7	1		T8	1		T11	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1			T3	1		T7	2		T8	3
all_values[4]	auto[1]	auto[1]	auto[1]	56	1			T8	1		T11	1		T12	1
all_values[5]	auto[0]	auto[0]	auto[0]	24	1			T11	2		T12	1		T60	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T3	3		T8	2		T11	2
all_values[5]	auto[0]	auto[1]	auto[0]	9	1			T11	1		T12	1		T46	1
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T7	1		T8	2		T22	2
all_values[5]	auto[1]	auto[0]	auto[1]	58	1			T3	1		T7	3		T8	1
all_values[5]	auto[1]	auto[1]	auto[1]	60	1			T8	2		T12	1		T52	2
all_values[6]	auto[0]	auto[0]	auto[0]	42	1			T8	1		T61	2		T46	1
all_values[6]	auto[0]	auto[0]	auto[1]	46	1			T3	1		T8	1		T11	1
all_values[6]	auto[0]	auto[1]	auto[0]	21	1			T22	4		T61	1		T37	2
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T7	1		T8	4		T11	1
all_values[6]	auto[1]	auto[0]	auto[1]	73	1			T3	2		T7	3		T8	1
all_values[6]	auto[1]	auto[1]	auto[1]	45	1			T3	1		T11	2		T52	1
all_values[7]	auto[0]	auto[0]	auto[0]	29	1			T7	1		T8	1		T22	1
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T11	1		T52	1		T60	1
all_values[7]	auto[0]	auto[1]	auto[0]	17	1			T78	4		T71	1		T79	1
all_values[7]	auto[0]	auto[1]	auto[1]	63	1			T3	3		T7	2		T8	4
all_values[7]	auto[1]	auto[0]	auto[1]	63	1			T3	1		T8	1		T11	2
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T7	1		T8	1		T11	1
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T7	1		T22	4		T52	1
all_values[8]	auto[0]	auto[0]	auto[1]	56	1			T3	2		T7	1		T11	5
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T61	1		T37	4		T78	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1			T3	1		T7	1		T8	4
all_values[8]	auto[1]	auto[0]	auto[1]	55	1			T3	1		T8	2		T11	1
all_values[8]	auto[1]	auto[1]	auto[1]	55	1			T7	1		T8	1		T11	1
all_values[9]	auto[0]	auto[0]	auto[0]	35	1			T3	3		T8	1		T11	2
all_values[9]	auto[0]	auto[0]	auto[1]	57	1			T7	1		T8	2		T11	1
all_values[9]	auto[0]	auto[1]	auto[0]	18	1			T3	1		T11	2		T52	1
all_values[9]	auto[0]	auto[1]	auto[1]	58	1			T7	1		T8	1		T22	2
all_values[9]	auto[1]	auto[0]	auto[1]	61	1			T7	1		T8	2		T11	2
all_values[9]	auto[1]	auto[1]	auto[1]	49	1			T7	1		T8	1		T12	2
all_values[10]	auto[0]	auto[0]	auto[0]	23	1			T7	1		T8	2		T22	1
all_values[10]	auto[0]	auto[0]	auto[1]	61	1			T3	2		T8	1		T12	2
all_values[10]	auto[0]	auto[1]	auto[0]	19	1			T8	2		T70	1		T80	2
all_values[10]	auto[0]	auto[1]	auto[1]	63	1			T7	1		T11	2		T12	1
all_values[10]	auto[1]	auto[0]	auto[1]	60	1			T3	1		T7	2		T8	2
all_values[10]	auto[1]	auto[1]	auto[1]	52	1			T3	1		T11	4		T52	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T3	1		T8	1		T11	1
all_values[11]	auto[0]	auto[0]	auto[1]	53	1			T3	2		T7	1		T8	1
all_values[11]	auto[0]	auto[1]	auto[0]	27	1			T11	1		T52	1		T46	1
all_values[11]	auto[0]	auto[1]	auto[1]	44	1			T8	3		T12	3		T52	2
all_values[11]	auto[1]	auto[0]	auto[1]	60	1			T3	1		T7	3		T11	3
all_values[11]	auto[1]	auto[1]	auto[1]	46	1			T8	2		T52	2		T60	3
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T8	1		T11	1		T60	2
all_values[12]	auto[0]	auto[0]	auto[1]	62	1			T8	3		T11	1		T12	3
all_values[12]	auto[0]	auto[1]	auto[0]	15	1			T60	1		T71	1		T81	3
all_values[12]	auto[0]	auto[1]	auto[1]	52	1			T3	2		T7	2		T8	1
all_values[12]	auto[1]	auto[0]	auto[1]	65	1			T3	1		T7	1		T8	2
all_values[12]	auto[1]	auto[1]	auto[1]	52	1			T3	1		T7	1		T11	1
all_values[13]	auto[0]	auto[0]	auto[0]	45	1			T8	1		T11	1		T12	2
all_values[13]	auto[0]	auto[0]	auto[1]	51	1			T7	1		T8	2		T11	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1			T60	1		T78	2		T77	1
all_values[13]	auto[0]	auto[1]	auto[1]	52	1			T3	2		T7	1		T11	2
all_values[13]	auto[1]	auto[0]	auto[1]	62	1			T3	2		T7	1		T8	3
all_values[13]	auto[1]	auto[1]	auto[1]	48	1			T7	1		T8	1		T11	1
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T3	1		T8	1		T12	1
all_values[14]	auto[0]	auto[0]	auto[1]	60	1			T7	1		T8	2		T11	4
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T12	1		T60	6		T61	1
all_values[14]	auto[0]	auto[1]	auto[1]	56	1			T3	2		T7	1		T11	1
all_values[14]	auto[1]	auto[0]	auto[1]	55	1			T7	1		T8	2		T11	1
all_values[14]	auto[1]	auto[1]	auto[1]	41	1			T3	1		T7	1		T8	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal