Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6446163	1			T1	3		T2	3		T3	3
all_values[1]	6446163	1			T1	3		T2	3		T3	3
all_values[2]	6446163	1			T1	3		T2	3		T3	3
all_values[3]	6446163	1			T1	3		T2	3		T3	3
all_values[4]	6446163	1			T1	3		T2	3		T3	3
all_values[5]	6446163	1			T1	3		T2	3		T3	3
all_values[6]	6446163	1			T1	3		T2	3		T3	3
all_values[7]	6446163	1			T1	3		T2	3		T3	3
all_values[8]	6446163	1			T1	3		T2	3		T3	3
all_values[9]	6446163	1			T1	3		T2	3		T3	3
all_values[10]	6446163	1			T1	3		T2	3		T3	3
all_values[11]	6446163	1			T1	3		T2	3		T3	3
all_values[12]	6446163	1			T1	3		T2	3		T3	3
all_values[13]	6446163	1			T1	3		T2	3		T3	3
all_values[14]	6446163	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83239468

1

T1

38

T2

38

T3

38

auto[1]

13452977

1

T1

7

T2

7

T3

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89277862

1

T1

45

T2

45

T3

45

auto[1]

7414583

1

T69

360233

T70

449311

T71

73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3] , all_values[4]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1891839	1			T2	1		T3	1		T12	1
all_values[0]	auto[0]	auto[1]	174936	1			T69	969		T70	13250		T72	2
all_values[0]	auto[1]	auto[0]	4040575	1			T1	3		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	338813	1			T69	29050		T70	18841		T71	5
all_values[1]	auto[0]	auto[0]	5930537	1			T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	513205	1			T69	29995		T70	32047		T72	14
all_values[1]	auto[1]	auto[0]	1915	1			T13	2		T10	2		T37	1
all_values[1]	auto[1]	auto[1]	506	1			T69	23		T70	45		T72	3
all_values[2]	auto[0]	auto[0]	5932425	1			T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	513560	1			T69	30017		T70	32091		T71	4
all_values[2]	auto[1]	auto[0]	1	1			T177	1		-	-		-	-
all_values[2]	auto[1]	auto[1]	177	1			T69	2		T70	1		T71	2
all_values[3]	auto[0]	auto[0]	5980235	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	465718	1			T70	32093		T71	2		T72	16
all_values[3]	auto[1]	auto[1]	210	1			T70	1		T71	2		T72	1
all_values[4]	auto[0]	auto[0]	5955071	1			T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	490897	1			T69	30018		T70	32089		T71	3
all_values[4]	auto[1]	auto[1]	195	1			T70	4		T71	3		T139	3
all_values[5]	auto[0]	auto[0]	5949010	1			T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	495702	1			T69	30017		T70	32091		T72	17
all_values[5]	auto[1]	auto[0]	1231	1			T36	1231		-	-		-	-
all_values[5]	auto[1]	auto[1]	220	1			T69	3		T70	4		T139	2
all_values[6]	auto[0]	auto[0]	5251789	1			T1	3		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	428995	1			T69	22597		T70	24298		T71	4
all_values[6]	auto[1]	auto[0]	680658	1			T2	1		T12	1		T13	6752
all_values[6]	auto[1]	auto[1]	84721	1			T69	7423		T70	7797		T71	1
all_values[7]	auto[0]	auto[0]	5727155	1			T1	3		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	460769	1			T69	26565		T71	3		T139	18784
all_values[7]	auto[1]	auto[0]	237401	1			T3	1		T12	1		T13	215
all_values[7]	auto[1]	auto[1]	20838	1			T69	3455		T71	3		T139	218
all_values[8]	auto[0]	auto[0]	5180996	1			T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	420340	1			T69	21851		T70	23004		T71	3
all_values[8]	auto[1]	auto[0]	751447	1			T2	1		T3	1		T12	1
all_values[8]	auto[1]	auto[1]	93380	1			T69	8169		T70	9090		T71	3
all_values[9]	auto[0]	auto[0]	5258310	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	430562	1			T69	22981		T70	24836		T71	5
all_values[9]	auto[1]	auto[0]	674102	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	83189	1			T69	7039		T70	7259		T71	1
all_values[10]	auto[0]	auto[0]	5962446	1			T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	483530	1			T70	32091		T71	4		T72	14
all_values[10]	auto[1]	auto[1]	187	1			T70	3		T71	2		T72	1
all_values[11]	auto[0]	auto[0]	3041	1			T2	1		T3	1		T12	1
all_values[11]	auto[0]	auto[1]	522	1			T69	27		T70	29		T72	2
all_values[11]	auto[1]	auto[0]	5929385	1			T1	3		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	513215	1			T69	29992		T70	32065		T71	6
all_values[12]	auto[0]	auto[0]	5962447	1			T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	483536	1			T70	32092		T71	5		T72	15
all_values[12]	auto[1]	auto[1]	180	1			T70	2		T71	1		T72	2
all_values[13]	auto[0]	auto[0]	5937269	1			T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	508678	1			T69	30016		T70	32089		T71	2
all_values[13]	auto[1]	auto[0]	9	1			T200	1		T193	1		T201	1
all_values[13]	auto[1]	auto[1]	207	1			T69	4		T70	5		T71	4
all_values[14]	auto[0]	auto[0]	6038568	1			T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	407380	1			T69	30018		T70	32092		T71	4
all_values[14]	auto[1]	auto[1]	215	1			T69	2		T70	2		T71	1