Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6446163	1			T1	3		T2	3		T3	3
all_pins[1]	6446163	1			T1	3		T2	3		T3	3
all_pins[2]	6446163	1			T1	3		T2	3		T3	3
all_pins[3]	6446163	1			T1	3		T2	3		T3	3
all_pins[4]	6446163	1			T1	3		T2	3		T3	3
all_pins[5]	6446163	1			T1	3		T2	3		T3	3
all_pins[6]	6446163	1			T1	3		T2	3		T3	3
all_pins[7]	6446163	1			T1	3		T2	3		T3	3
all_pins[8]	6446163	1			T1	3		T2	3		T3	3
all_pins[9]	6446163	1			T1	3		T2	3		T3	3
all_pins[10]	6446163	1			T1	3		T2	3		T3	3
all_pins[11]	6446163	1			T1	3		T2	3		T3	3
all_pins[12]	6446163	1			T1	3		T2	3		T3	3
all_pins[13]	6446163	1			T1	3		T2	3		T3	3
all_pins[14]	6446163	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	83200054	1			T1	38		T2	38		T3	38
values[0x1]	13492391	1			T1	7		T2	7		T3	7
transitions[0x0=>0x1]	12681107	1			T1	7		T2	6		T3	5
transitions[0x1=>0x0]	12680117	1			T1	6		T2	5		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2066927	1			T2	1		T3	1		T12	1
all_pins[0]	values[0x1]	4379236	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	4376639	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	111	1			T69	1		T70	1		T72	2
all_pins[1]	values[0x0]	6443455	1			T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	2708	1			T13	3		T10	2		T37	1
all_pins[1]	transitions[0x0=>0x1]	2680	1			T13	3		T10	2		T37	1
all_pins[1]	transitions[0x1=>0x0]	71	1			T71	1		T139	1		T177	1
all_pins[2]	values[0x0]	6446064	1			T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	99	1			T69	1		T71	1		T72	1
all_pins[2]	transitions[0x0=>0x1]	76	1			T69	1		T71	1		T72	1
all_pins[2]	transitions[0x1=>0x0]	82	1			T139	1		T147	6		T151	1
all_pins[3]	values[0x0]	6446058	1			T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	105	1			T139	1		T147	6		T151	3
all_pins[3]	transitions[0x0=>0x1]	76	1			T139	1		T147	4		T151	3
all_pins[3]	transitions[0x1=>0x0]	81	1			T70	1		T71	2		T140	1
all_pins[4]	values[0x0]	6446053	1			T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	110	1			T70	1		T71	2		T140	1
all_pins[4]	transitions[0x0=>0x1]	77	1			T70	1		T71	2		T140	1
all_pins[4]	transitions[0x1=>0x0]	1398	1			T69	1		T70	1		T139	2
all_pins[5]	values[0x0]	6444732	1			T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	1431	1			T69	1		T70	1		T139	2
all_pins[5]	transitions[0x0=>0x1]	1220	1			T69	1		T139	2		T147	1
all_pins[5]	transitions[0x1=>0x0]	766108	1			T2	1		T12	1		T13	6752
all_pins[6]	values[0x0]	5679844	1			T1	3		T2	2		T3	3
all_pins[6]	values[0x1]	766319	1			T2	1		T12	1		T13	6752
all_pins[6]	transitions[0x0=>0x1]	747445	1			T2	1		T13	6518		T10	30
all_pins[6]	transitions[0x1=>0x0]	268769	1			T3	1		T13	2		T10	1228
all_pins[7]	values[0x0]	6158520	1			T1	3		T2	3		T3	2
all_pins[7]	values[0x1]	287643	1			T3	1		T12	1		T13	236
all_pins[7]	transitions[0x0=>0x1]	251100	1			T10	1123		T37	629		T11	1396
all_pins[7]	transitions[0x1=>0x0]	817669	1			T2	1		T17	1		T13	6534
all_pins[8]	values[0x0]	5591951	1			T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	854212	1			T2	1		T3	1		T12	1
all_pins[8]	transitions[0x0=>0x1]	101442	1			T13	18		T10	492		T37	272
all_pins[8]	transitions[0x1=>0x0]	4878	1			T1	1		T7	1		T8	1
all_pins[9]	values[0x0]	5688515	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	757648	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	757629	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	80	1			T70	3		T71	1		T139	1
all_pins[10]	values[0x0]	6446064	1			T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	99	1			T70	3		T71	1		T139	2
all_pins[10]	transitions[0x0=>0x1]	69	1			T70	2		T139	1		T140	2
all_pins[10]	transitions[0x1=>0x0]	6442455	1			T1	3		T2	2		T3	2
all_pins[11]	values[0x0]	3678	1			T2	1		T3	1		T12	1
all_pins[11]	values[0x1]	6442485	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	6442452	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	58	1			T139	1		T175	1		T147	1
all_pins[12]	values[0x0]	6446072	1			T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	91	1			T70	1		T71	1		T139	1
all_pins[12]	transitions[0x0=>0x1]	70	1			T70	1		T71	1		T139	1
all_pins[12]	transitions[0x1=>0x0]	82	1			T69	2		T70	5		T71	1
all_pins[13]	values[0x0]	6446060	1			T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	103	1			T69	2		T70	5		T71	1
all_pins[13]	transitions[0x0=>0x1]	76	1			T70	5		T72	1		T200	1
all_pins[13]	transitions[0x1=>0x0]	75	1			T175	1		T147	1		T151	3
all_pins[14]	values[0x0]	6446061	1			T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	102	1			T69	2		T71	1		T175	2
all_pins[14]	transitions[0x0=>0x1]	56	1			T69	2		T71	1		T147	1
all_pins[14]	transitions[0x1=>0x0]	4378200	1			T1	2		T2	1		T3	1