Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	456	1			T69	4		T70	7		T71	4
all_values[1]	456	1			T69	4		T70	7		T71	4
all_values[2]	456	1			T69	4		T70	7		T71	4
all_values[3]	456	1			T69	4		T70	7		T71	4
all_values[4]	456	1			T69	4		T70	7		T71	4
all_values[5]	456	1			T69	4		T70	7		T71	4
all_values[6]	456	1			T69	4		T70	7		T71	4
all_values[7]	456	1			T69	4		T70	7		T71	4
all_values[8]	456	1			T69	4		T70	7		T71	4
all_values[9]	456	1			T69	4		T70	7		T71	4
all_values[10]	456	1			T69	4		T70	7		T71	4
all_values[11]	456	1			T69	4		T70	7		T71	4
all_values[12]	456	1			T69	4		T70	7		T71	4
all_values[13]	456	1			T69	4		T70	7		T71	4
all_values[14]	456	1			T69	4		T70	7		T71	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3491

1

T69

29

T70

46

T71

30

auto[1]

3349

1

T69

31

T70

59

T71

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T69

19

T70

26

T71

13

auto[1]

5633

1

T69

41

T70

79

T71

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4042

1

T69

37

T70

68

T71

35

auto[1]

2798

1

T69

23

T70

37

T71

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	41	1			T69	1		T70	1		T71	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T69	1		T70	1		T71	1
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T70	3		T147	2		T39	2
all_values[0]	auto[0]	auto[1]	auto[1]	105	1			T69	1		T70	1		T71	1
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T69	1		T70	1		T71	1
all_values[0]	auto[1]	auto[1]	auto[1]	104	1			T139	1		T140	2		T175	3
all_values[1]	auto[0]	auto[0]	auto[0]	60	1			T69	1		T70	2		T71	2
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T70	3		T72	1		T175	2
all_values[1]	auto[0]	auto[1]	auto[0]	34	1			T69	1		T70	1		T71	2
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T69	1		T139	4		T140	1
all_values[1]	auto[1]	auto[0]	auto[1]	90	1			T69	1		T139	1		T140	1
all_values[1]	auto[1]	auto[1]	auto[1]	90	1			T70	1		T72	3		T139	2
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T140	1		T147	1		T213	2
all_values[2]	auto[0]	auto[0]	auto[1]	105	1			T70	3		T71	2		T72	1
all_values[2]	auto[0]	auto[1]	auto[0]	35	1			T69	1		T70	3		T146	3
all_values[2]	auto[0]	auto[1]	auto[1]	98	1			T69	1		T72	1		T140	2
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T69	2		T70	1		T139	1
all_values[2]	auto[1]	auto[1]	auto[1]	94	1			T71	2		T72	2		T139	1
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T69	2		T71	2		T139	1
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T70	2		T71	1		T139	3
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T69	2		T70	1		T153	4
all_values[3]	auto[0]	auto[1]	auto[1]	97	1			T70	1		T72	2		T139	1
all_values[3]	auto[1]	auto[0]	auto[1]	111	1			T70	1		T72	2		T139	2
all_values[3]	auto[1]	auto[1]	auto[1]	86	1			T70	2		T71	1		T175	2
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T70	1		T175	1		T146	1
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T70	2		T139	2		T140	2
all_values[4]	auto[0]	auto[1]	auto[0]	54	1			T69	2		T70	1		T72	2
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T69	1		T70	1		T71	1
all_values[4]	auto[1]	auto[0]	auto[1]	96	1			T71	3		T72	1		T139	3
all_values[4]	auto[1]	auto[1]	auto[1]	84	1			T69	1		T70	2		T139	1
all_values[5]	auto[0]	auto[0]	auto[0]	58	1			T71	3		T140	2		T151	1
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T69	2		T70	1		T72	2
all_values[5]	auto[0]	auto[1]	auto[0]	29	1			T71	1		T139	1		T140	2
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T70	1		T72	1		T139	3
all_values[5]	auto[1]	auto[0]	auto[1]	90	1			T69	1		T70	3		T139	1
all_values[5]	auto[1]	auto[1]	auto[1]	111	1			T69	1		T70	2		T72	1
all_values[6]	auto[0]	auto[0]	auto[0]	39	1			T146	2		T151	1		T153	2
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T69	1		T70	1		T71	1
all_values[6]	auto[0]	auto[1]	auto[0]	37	1			T71	1		T146	1		T151	1
all_values[6]	auto[0]	auto[1]	auto[1]	102	1			T69	1		T70	3		T71	1
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T69	1		T70	1		T72	1
all_values[6]	auto[1]	auto[1]	auto[1]	94	1			T69	1		T70	2		T71	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T70	3		T72	1		T140	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T69	1		T71	1		T146	1
all_values[7]	auto[0]	auto[1]	auto[0]	49	1			T70	4		T72	3		T175	2
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T69	1		T139	3		T140	2
all_values[7]	auto[1]	auto[0]	auto[1]	96	1			T69	2		T71	1		T139	2
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T71	2		T139	2		T146	1
all_values[8]	auto[0]	auto[0]	auto[0]	44	1			T72	3		T139	1		T140	1
all_values[8]	auto[0]	auto[0]	auto[1]	98	1			T70	3		T139	1		T140	2
all_values[8]	auto[0]	auto[1]	auto[0]	35	1			T70	1		T72	1		T139	1
all_values[8]	auto[0]	auto[1]	auto[1]	92	1			T69	1		T70	1		T71	1
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T69	3		T70	1		T71	1
all_values[8]	auto[1]	auto[1]	auto[1]	97	1			T70	1		T71	2		T139	2
all_values[9]	auto[0]	auto[0]	auto[0]	40	1			T146	3		T147	1		T171	1
all_values[9]	auto[0]	auto[0]	auto[1]	117	1			T69	2		T70	3		T71	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T171	1		T214	2		T215	1
all_values[9]	auto[0]	auto[1]	auto[1]	100	1			T70	1		T71	1		T139	2
all_values[9]	auto[1]	auto[0]	auto[1]	97	1			T69	1		T71	2		T72	1
all_values[9]	auto[1]	auto[1]	auto[1]	75	1			T69	1		T70	3		T72	1
all_values[10]	auto[0]	auto[0]	auto[0]	50	1			T72	2		T139	1		T213	2
all_values[10]	auto[0]	auto[0]	auto[1]	91	1			T70	1		T71	2		T72	1
all_values[10]	auto[0]	auto[1]	auto[0]	30	1			T69	4		T70	1		T151	1
all_values[10]	auto[0]	auto[1]	auto[1]	98	1			T70	2		T139	4		T175	1
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T140	1		T175	3		T147	2
all_values[10]	auto[1]	auto[1]	auto[1]	95	1			T70	3		T71	2		T72	1
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T72	2		T175	1		T147	4
all_values[11]	auto[0]	auto[0]	auto[1]	70	1			T139	1		T175	1		T146	2
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T69	1		T70	1		T139	1
all_values[11]	auto[0]	auto[1]	auto[1]	114	1			T69	1		T70	2		T71	2
all_values[11]	auto[1]	auto[0]	auto[1]	100	1			T70	2		T72	1		T139	2
all_values[11]	auto[1]	auto[1]	auto[1]	98	1			T69	2		T70	2		T71	2
all_values[12]	auto[0]	auto[0]	auto[0]	54	1			T69	4		T139	2		T147	1
all_values[12]	auto[0]	auto[0]	auto[1]	94	1			T71	1		T72	2		T140	1
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T70	1		T139	3		T140	1
all_values[12]	auto[0]	auto[1]	auto[1]	97	1			T70	4		T71	2		T139	1
all_values[12]	auto[1]	auto[0]	auto[1]	94	1			T70	2		T72	1		T140	1
all_values[12]	auto[1]	auto[1]	auto[1]	86	1			T71	1		T72	1		T139	1
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T146	1		T147	1		T216	2
all_values[13]	auto[0]	auto[0]	auto[1]	110	1			T69	1		T71	1		T72	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T70	1		T140	4		T146	3
all_values[13]	auto[0]	auto[1]	auto[1]	84	1			T69	1		T70	2		T72	1
all_values[13]	auto[1]	auto[0]	auto[1]	108	1			T70	2		T71	2		T175	1
all_values[13]	auto[1]	auto[1]	auto[1]	76	1			T69	2		T70	2		T71	1
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T72	1		T147	4		T151	1
all_values[14]	auto[0]	auto[0]	auto[1]	102	1			T69	1		T70	3		T71	1
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T70	1		T71	1		T140	1
all_values[14]	auto[0]	auto[1]	auto[1]	96	1			T71	1		T139	5		T175	1
all_values[14]	auto[1]	auto[0]	auto[1]	96	1			T70	2		T72	1		T139	1
all_values[14]	auto[1]	auto[1]	auto[1]	92	1			T69	3		T70	1		T71	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal