Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.94 98.90 96.41 100.00 93.91 97.64 100.00 91.70


Total test records in report: 1376
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T132 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3684128845 Mar 12 12:42:59 PM PDT 24 Mar 12 12:43:00 PM PDT 24 38424387 ps
T87 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3559014944 Mar 12 12:42:06 PM PDT 24 Mar 12 12:42:07 PM PDT 24 63305673 ps
T143 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3205558505 Mar 12 12:42:26 PM PDT 24 Mar 12 12:42:28 PM PDT 24 83949444 ps
T133 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2994672222 Mar 12 12:42:48 PM PDT 24 Mar 12 12:42:49 PM PDT 24 82411752 ps
T1281 /workspace/coverage/cover_reg_top/40.i2c_intr_test.1451978254 Mar 12 12:43:14 PM PDT 24 Mar 12 12:43:15 PM PDT 24 15673715 ps
T1282 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2382696916 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 43287814 ps
T134 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3433589022 Mar 12 12:42:38 PM PDT 24 Mar 12 12:42:38 PM PDT 24 16239437 ps
T89 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.698952818 Mar 12 12:42:45 PM PDT 24 Mar 12 12:42:47 PM PDT 24 64724574 ps
T98 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1053299834 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 264172906 ps
T128 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1138435315 Mar 12 12:42:08 PM PDT 24 Mar 12 12:42:14 PM PDT 24 954226861 ps
T1283 /workspace/coverage/cover_reg_top/45.i2c_intr_test.4013877464 Mar 12 12:43:17 PM PDT 24 Mar 12 12:43:18 PM PDT 24 14765782 ps
T135 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4264525645 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 18645740 ps
T1284 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3770383137 Mar 12 12:43:00 PM PDT 24 Mar 12 12:43:01 PM PDT 24 174484484 ps
T1285 /workspace/coverage/cover_reg_top/7.i2c_intr_test.529602393 Mar 12 12:42:36 PM PDT 24 Mar 12 12:42:37 PM PDT 24 43013662 ps
T136 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2142273873 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 58651781 ps
T1286 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1579870191 Mar 12 12:42:27 PM PDT 24 Mar 12 12:42:28 PM PDT 24 35365750 ps
T137 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2659558966 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 35114277 ps
T1287 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2684495715 Mar 12 12:42:47 PM PDT 24 Mar 12 12:42:48 PM PDT 24 17653415 ps
T138 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2574391768 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 21423665 ps
T1288 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1096719760 Mar 12 12:42:37 PM PDT 24 Mar 12 12:42:38 PM PDT 24 27420893 ps
T1289 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2396048984 Mar 12 12:43:14 PM PDT 24 Mar 12 12:43:15 PM PDT 24 41605549 ps
T1290 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4182700717 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 21360004 ps
T1291 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3015493973 Mar 12 12:42:46 PM PDT 24 Mar 12 12:42:48 PM PDT 24 170693931 ps
T1292 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2526525479 Mar 12 12:43:07 PM PDT 24 Mar 12 12:43:08 PM PDT 24 65949907 ps
T1293 /workspace/coverage/cover_reg_top/8.i2c_intr_test.297342744 Mar 12 12:42:46 PM PDT 24 Mar 12 12:42:46 PM PDT 24 31173704 ps
T1294 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2336077151 Mar 12 12:42:56 PM PDT 24 Mar 12 12:42:57 PM PDT 24 26360998 ps
T1295 /workspace/coverage/cover_reg_top/15.i2c_intr_test.4101657956 Mar 12 12:42:55 PM PDT 24 Mar 12 12:42:56 PM PDT 24 15548692 ps
T1296 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4204328865 Mar 12 12:42:49 PM PDT 24 Mar 12 12:42:50 PM PDT 24 102753681 ps
T1297 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3447517688 Mar 12 12:43:15 PM PDT 24 Mar 12 12:43:15 PM PDT 24 17238284 ps
T1298 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3040394150 Mar 12 12:42:37 PM PDT 24 Mar 12 12:42:38 PM PDT 24 39036100 ps
T97 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.82863840 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:18 PM PDT 24 58314433 ps
T118 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1159687295 Mar 12 12:42:57 PM PDT 24 Mar 12 12:42:58 PM PDT 24 31090684 ps
T99 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.296478915 Mar 12 12:42:46 PM PDT 24 Mar 12 12:42:48 PM PDT 24 138446092 ps
T1299 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1673886681 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:18 PM PDT 24 19381757 ps
T1300 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1677735721 Mar 12 12:43:07 PM PDT 24 Mar 12 12:43:07 PM PDT 24 18488587 ps
T1301 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.573671018 Mar 12 12:42:48 PM PDT 24 Mar 12 12:42:49 PM PDT 24 86615388 ps
T1302 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3392180326 Mar 12 12:43:08 PM PDT 24 Mar 12 12:43:09 PM PDT 24 58178154 ps
T197 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.172048892 Mar 12 12:42:27 PM PDT 24 Mar 12 12:42:29 PM PDT 24 921093579 ps
T1303 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3784201746 Mar 12 12:42:28 PM PDT 24 Mar 12 12:42:29 PM PDT 24 40539276 ps
T1304 /workspace/coverage/cover_reg_top/49.i2c_intr_test.289715351 Mar 12 12:43:16 PM PDT 24 Mar 12 12:43:18 PM PDT 24 24800559 ps
T90 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1273205991 Mar 12 12:42:35 PM PDT 24 Mar 12 12:42:38 PM PDT 24 273430206 ps
T1305 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4261019556 Mar 12 12:42:19 PM PDT 24 Mar 12 12:42:19 PM PDT 24 25577946 ps
T1306 /workspace/coverage/cover_reg_top/14.i2c_intr_test.4152644965 Mar 12 12:43:12 PM PDT 24 Mar 12 12:43:13 PM PDT 24 15784178 ps
T119 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4064822098 Mar 12 12:42:26 PM PDT 24 Mar 12 12:42:27 PM PDT 24 31245480 ps
T1307 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2198139824 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 126841855 ps
T1308 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4054647156 Mar 12 12:42:47 PM PDT 24 Mar 12 12:42:48 PM PDT 24 947592763 ps
T198 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1184743456 Mar 12 12:42:59 PM PDT 24 Mar 12 12:43:00 PM PDT 24 49964087 ps
T120 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1399900911 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 30418463 ps
T1309 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1569845682 Mar 12 12:42:58 PM PDT 24 Mar 12 12:43:00 PM PDT 24 756190769 ps
T1310 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1716754713 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:08 PM PDT 24 195645195 ps
T1311 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2756840212 Mar 12 12:42:26 PM PDT 24 Mar 12 12:42:28 PM PDT 24 82873577 ps
T121 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1250779227 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:18 PM PDT 24 24865732 ps
T122 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3184018175 Mar 12 12:42:07 PM PDT 24 Mar 12 12:42:08 PM PDT 24 29751803 ps
T1312 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.580760662 Mar 12 12:42:50 PM PDT 24 Mar 12 12:42:51 PM PDT 24 25425100 ps
T1313 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2013312623 Mar 12 12:42:19 PM PDT 24 Mar 12 12:42:20 PM PDT 24 45843869 ps
T1314 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3529614742 Mar 12 12:42:57 PM PDT 24 Mar 12 12:42:58 PM PDT 24 129345326 ps
T1315 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3337734606 Mar 12 12:42:08 PM PDT 24 Mar 12 12:42:09 PM PDT 24 30623965 ps
T1316 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1617918894 Mar 12 12:42:25 PM PDT 24 Mar 12 12:42:26 PM PDT 24 82538876 ps
T199 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1049152177 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 68775452 ps
T1317 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2934374106 Mar 12 12:42:35 PM PDT 24 Mar 12 12:42:36 PM PDT 24 41681681 ps
T1318 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2125890047 Mar 12 12:42:08 PM PDT 24 Mar 12 12:42:10 PM PDT 24 24129626 ps
T1319 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.346424637 Mar 12 12:42:18 PM PDT 24 Mar 12 12:42:19 PM PDT 24 22017023 ps
T1320 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2581356235 Mar 12 12:42:28 PM PDT 24 Mar 12 12:42:30 PM PDT 24 228656395 ps
T1321 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1589186717 Mar 12 12:43:15 PM PDT 24 Mar 12 12:43:15 PM PDT 24 31859670 ps
T1322 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.4122379847 Mar 12 12:43:12 PM PDT 24 Mar 12 12:43:14 PM PDT 24 41499633 ps
T1323 /workspace/coverage/cover_reg_top/0.i2c_intr_test.527768769 Mar 12 12:42:06 PM PDT 24 Mar 12 12:42:07 PM PDT 24 22704478 ps
T1324 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1715011970 Mar 12 12:42:10 PM PDT 24 Mar 12 12:42:11 PM PDT 24 23806228 ps
T1325 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2819992531 Mar 12 12:42:48 PM PDT 24 Mar 12 12:42:48 PM PDT 24 48329835 ps
T1326 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3650169682 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 16268530 ps
T1327 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1417593135 Mar 12 12:42:19 PM PDT 24 Mar 12 12:42:20 PM PDT 24 37543314 ps
T1328 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2169624858 Mar 12 12:42:35 PM PDT 24 Mar 12 12:42:37 PM PDT 24 94821783 ps
T1329 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2200818688 Mar 12 12:42:31 PM PDT 24 Mar 12 12:42:32 PM PDT 24 20775173 ps
T1330 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2233169466 Mar 12 12:43:04 PM PDT 24 Mar 12 12:43:05 PM PDT 24 21620607 ps
T1331 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2356846288 Mar 12 12:43:04 PM PDT 24 Mar 12 12:43:05 PM PDT 24 30598266 ps
T1332 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2886199584 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 48839818 ps
T1333 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3152792796 Mar 12 12:43:17 PM PDT 24 Mar 12 12:43:18 PM PDT 24 16933003 ps
T1334 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3053026659 Mar 12 12:43:14 PM PDT 24 Mar 12 12:43:14 PM PDT 24 210063622 ps
T123 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2259059923 Mar 12 12:42:19 PM PDT 24 Mar 12 12:42:21 PM PDT 24 137685359 ps
T1335 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1272928152 Mar 12 12:42:57 PM PDT 24 Mar 12 12:42:59 PM PDT 24 404627371 ps
T1336 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2366834906 Mar 12 12:42:28 PM PDT 24 Mar 12 12:42:28 PM PDT 24 18723158 ps
T1337 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3979822265 Mar 12 12:42:27 PM PDT 24 Mar 12 12:42:28 PM PDT 24 71488840 ps
T1338 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2720094951 Mar 12 12:43:07 PM PDT 24 Mar 12 12:43:07 PM PDT 24 40486061 ps
T101 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2969309908 Mar 12 12:43:12 PM PDT 24 Mar 12 12:43:14 PM PDT 24 49687508 ps
T1339 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.417079027 Mar 12 12:42:58 PM PDT 24 Mar 12 12:43:00 PM PDT 24 361509885 ps
T1340 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3163989652 Mar 12 12:42:56 PM PDT 24 Mar 12 12:42:57 PM PDT 24 38710318 ps
T1341 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.253926988 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:18 PM PDT 24 22699339 ps
T1342 /workspace/coverage/cover_reg_top/2.i2c_intr_test.938872401 Mar 12 12:42:18 PM PDT 24 Mar 12 12:42:19 PM PDT 24 57426059 ps
T124 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3052428177 Mar 12 12:42:18 PM PDT 24 Mar 12 12:42:22 PM PDT 24 503011311 ps
T1343 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.669177433 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 85466885 ps
T1344 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.492180957 Mar 12 12:43:06 PM PDT 24 Mar 12 12:43:07 PM PDT 24 53846899 ps
T1345 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2033611985 Mar 12 12:43:04 PM PDT 24 Mar 12 12:43:06 PM PDT 24 17484359 ps
T1346 /workspace/coverage/cover_reg_top/17.i2c_intr_test.939515895 Mar 12 12:42:57 PM PDT 24 Mar 12 12:42:58 PM PDT 24 15583417 ps
T1347 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3976218249 Mar 12 12:43:03 PM PDT 24 Mar 12 12:43:05 PM PDT 24 46064470 ps
T1348 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2273111291 Mar 12 12:42:50 PM PDT 24 Mar 12 12:42:51 PM PDT 24 75514582 ps
T1349 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2396476755 Mar 12 12:43:05 PM PDT 24 Mar 12 12:43:06 PM PDT 24 27882774 ps
T1350 /workspace/coverage/cover_reg_top/24.i2c_intr_test.191374947 Mar 12 12:43:04 PM PDT 24 Mar 12 12:43:05 PM PDT 24 44127356 ps
T1351 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1655539996 Mar 12 12:42:58 PM PDT 24 Mar 12 12:42:59 PM PDT 24 32195887 ps
T125 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.598034852 Mar 12 12:42:27 PM PDT 24 Mar 12 12:42:28 PM PDT 24 144427107 ps
T1352 /workspace/coverage/cover_reg_top/46.i2c_intr_test.180487507 Mar 12 12:43:15 PM PDT 24 Mar 12 12:43:17 PM PDT 24 16977255 ps
T1353 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1948077307 Mar 12 12:42:57 PM PDT 24 Mar 12 12:42:58 PM PDT 24 575216372 ps
T1354 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.737104664 Mar 12 12:42:35 PM PDT 24 Mar 12 12:42:37 PM PDT 24 288402654 ps
T1355 /workspace/coverage/cover_reg_top/5.i2c_intr_test.913710572 Mar 12 12:42:26 PM PDT 24 Mar 12 12:42:27 PM PDT 24 18276808 ps
T1356 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3197183120 Mar 12 12:42:38 PM PDT 24 Mar 12 12:42:40 PM PDT 24 84644593 ps
T1357 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4131892386 Mar 12 12:43:06 PM PDT 24 Mar 12 12:43:07 PM PDT 24 66865096 ps
T1358 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2503953286 Mar 12 12:42:19 PM PDT 24 Mar 12 12:42:21 PM PDT 24 187369505 ps
T1359 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.666567497 Mar 12 12:42:37 PM PDT 24 Mar 12 12:42:38 PM PDT 24 348376294 ps
T126 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.33585531 Mar 12 12:42:05 PM PDT 24 Mar 12 12:42:06 PM PDT 24 77140298 ps
T1360 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.792748006 Mar 12 12:43:12 PM PDT 24 Mar 12 12:43:14 PM PDT 24 32362196 ps
T1361 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1588693366 Mar 12 12:43:03 PM PDT 24 Mar 12 12:43:05 PM PDT 24 51607006 ps
T1362 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1696589913 Mar 12 12:42:50 PM PDT 24 Mar 12 12:42:51 PM PDT 24 53313763 ps
T1363 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3660991885 Mar 12 12:43:12 PM PDT 24 Mar 12 12:43:13 PM PDT 24 14770710 ps
T1364 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2139818242 Mar 12 12:42:59 PM PDT 24 Mar 12 12:43:00 PM PDT 24 206799234 ps
T1365 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1523902333 Mar 12 12:42:29 PM PDT 24 Mar 12 12:42:33 PM PDT 24 103804502 ps
T1366 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.263163633 Mar 12 12:42:47 PM PDT 24 Mar 12 12:42:49 PM PDT 24 144778164 ps
T1367 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2408443114 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:18 PM PDT 24 38079940 ps
T1368 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1525949315 Mar 12 12:42:59 PM PDT 24 Mar 12 12:43:00 PM PDT 24 19728694 ps
T1369 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3271419396 Mar 12 12:42:47 PM PDT 24 Mar 12 12:42:48 PM PDT 24 370422348 ps
T1370 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.500177946 Mar 12 12:42:17 PM PDT 24 Mar 12 12:42:20 PM PDT 24 650763030 ps
T129 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.649002259 Mar 12 12:42:27 PM PDT 24 Mar 12 12:42:31 PM PDT 24 204739805 ps
T103 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1538454748 Mar 12 12:42:07 PM PDT 24 Mar 12 12:42:09 PM PDT 24 146371178 ps
T1371 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1725719799 Mar 12 12:43:17 PM PDT 24 Mar 12 12:43:18 PM PDT 24 40114288 ps
T1372 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1245541859 Mar 12 12:42:36 PM PDT 24 Mar 12 12:42:37 PM PDT 24 40161902 ps
T1373 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.394515659 Mar 12 12:42:50 PM PDT 24 Mar 12 12:42:50 PM PDT 24 72306429 ps
T1374 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3363753703 Mar 12 12:43:06 PM PDT 24 Mar 12 12:43:08 PM PDT 24 201715338 ps
T1375 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2788517882 Mar 12 12:42:28 PM PDT 24 Mar 12 12:42:29 PM PDT 24 22117906 ps
T1376 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3947057285 Mar 12 12:42:59 PM PDT 24 Mar 12 12:43:00 PM PDT 24 42334105 ps

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1029940351
Short name T12
Test name
Test status
Simulation time 28961970332 ps
CPU time 140.32 seconds
Started Mar 12 02:38:23 PM PDT 24
Finished Mar 12 02:40:44 PM PDT 24
Peak memory 1498976 kb
Host smart-806d0c39-6994-44f3-bbde-f066144de136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029940351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1029940351
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3290248213
Short name T33
Test name
Test status
Simulation time 3164744855 ps
CPU time 4.36 seconds
Started Mar 12 02:33:07 PM PDT 24
Finished Mar 12 02:33:12 PM PDT 24
Peak memory 203576 kb
Host smart-2640b9ee-abee-46fd-8061-fc02403e6190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290248213 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3290248213
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3839504
Short name T29
Test name
Test status
Simulation time 2991056362 ps
CPU time 11.62 seconds
Started Mar 12 02:31:56 PM PDT 24
Finished Mar 12 02:32:08 PM PDT 24
Peak memory 203816 kb
Host smart-731cb144-dd79-45c9-91e8-a84bf152cc99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3839504
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2093541766
Short name T69
Test name
Test status
Simulation time 41287221438 ps
CPU time 1792.8 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 03:04:05 PM PDT 24
Peak memory 1462068 kb
Host smart-3f4d1779-734a-4b00-84be-cbace5ef5354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093541766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2093541766
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.170282430
Short name T91
Test name
Test status
Simulation time 160017125 ps
CPU time 2.75 seconds
Started Mar 12 12:42:07 PM PDT 24
Finished Mar 12 12:42:10 PM PDT 24
Peak memory 202580 kb
Host smart-0767813b-b4e8-4d2e-bdb9-7cc399b1f8a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170282430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.170282430
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2051238016
Short name T139
Test name
Test status
Simulation time 21250666256 ps
CPU time 449.76 seconds
Started Mar 12 02:37:03 PM PDT 24
Finished Mar 12 02:44:33 PM PDT 24
Peak memory 1243108 kb
Host smart-0d438910-d102-41f4-88f0-f54c0df626ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051238016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2051238016
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_override.4238626236
Short name T162
Test name
Test status
Simulation time 19624234 ps
CPU time 0.67 seconds
Started Mar 12 02:41:28 PM PDT 24
Finished Mar 12 02:41:28 PM PDT 24
Peak memory 202536 kb
Host smart-83224048-2a0c-4354-83f9-08ea7c12833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238626236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.4238626236
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3662541997
Short name T7
Test name
Test status
Simulation time 10095795787 ps
CPU time 87.87 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:42:23 PM PDT 24
Peak memory 715536 kb
Host smart-65328b85-e662-45f5-8e96-9dd94bf3455c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662541997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3662541997
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2147406822
Short name T84
Test name
Test status
Simulation time 58380469 ps
CPU time 0.92 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:32:23 PM PDT 24
Peak memory 220832 kb
Host smart-bd495a99-f62d-4beb-90a3-067479614918
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147406822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2147406822
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.861572352
Short name T24
Test name
Test status
Simulation time 3787140546 ps
CPU time 74.22 seconds
Started Mar 12 02:34:16 PM PDT 24
Finished Mar 12 02:35:31 PM PDT 24
Peak memory 347808 kb
Host smart-6a622bc3-8770-4b27-8330-c9b05f36fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861572352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.861572352
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3747516217
Short name T147
Test name
Test status
Simulation time 64051947192 ps
CPU time 1322.69 seconds
Started Mar 12 02:40:23 PM PDT 24
Finished Mar 12 03:02:27 PM PDT 24
Peak memory 1992160 kb
Host smart-29e92a5a-a01d-49af-879d-f6c6cbee4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747516217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3747516217
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.3750671953
Short name T283
Test name
Test status
Simulation time 52622273286 ps
CPU time 45.67 seconds
Started Mar 12 02:39:45 PM PDT 24
Finished Mar 12 02:40:30 PM PDT 24
Peak memory 410932 kb
Host smart-42d9dbff-d717-4bc2-a3ad-e8084a57c78b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750671953 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.3750671953
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2938014722
Short name T117
Test name
Test status
Simulation time 32505360 ps
CPU time 1.32 seconds
Started Mar 12 12:42:11 PM PDT 24
Finished Mar 12 12:42:12 PM PDT 24
Peak memory 202444 kb
Host smart-c88a95c0-747f-4240-a9d4-7d4d1d167d87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938014722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2938014722
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.4290634127
Short name T40
Test name
Test status
Simulation time 41530777305 ps
CPU time 406.31 seconds
Started Mar 12 02:37:34 PM PDT 24
Finished Mar 12 02:44:23 PM PDT 24
Peak memory 2258816 kb
Host smart-02d73941-6143-437d-bd15-4e99caa41306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290634127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.4290634127
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_perf.4212736351
Short name T36
Test name
Test status
Simulation time 9698395740 ps
CPU time 20.54 seconds
Started Mar 12 02:40:27 PM PDT 24
Finished Mar 12 02:40:48 PM PDT 24
Peak memory 211644 kb
Host smart-25650f4c-0935-4c10-83a9-66f9dd150781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212736351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.4212736351
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.296478915
Short name T99
Test name
Test status
Simulation time 138446092 ps
CPU time 1.94 seconds
Started Mar 12 12:42:46 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202412 kb
Host smart-d1e7bed9-d66d-4d92-b0a2-b923967061c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296478915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.296478915
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3760886002
Short name T320
Test name
Test status
Simulation time 580547387 ps
CPU time 2.83 seconds
Started Mar 12 02:34:59 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 203628 kb
Host smart-43950fe1-f0e2-46ac-bfb0-ec8f12f1c91c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760886002 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3760886002
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3115054274
Short name T9
Test name
Test status
Simulation time 743105431 ps
CPU time 1.07 seconds
Started Mar 12 02:34:22 PM PDT 24
Finished Mar 12 02:34:25 PM PDT 24
Peak memory 203340 kb
Host smart-6cabcba4-1464-4ec1-8fba-4f244870fa04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115054274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3115054274
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.4264385390
Short name T1142
Test name
Test status
Simulation time 2708824277 ps
CPU time 3.05 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:52 PM PDT 24
Peak memory 203624 kb
Host smart-d5e73196-0bd7-4359-a9ff-9aaaae36b462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264385390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.4264385390
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2772745967
Short name T64
Test name
Test status
Simulation time 118594150 ps
CPU time 1.49 seconds
Started Mar 12 02:36:07 PM PDT 24
Finished Mar 12 02:36:08 PM PDT 24
Peak memory 215108 kb
Host smart-bc302912-bb96-4026-94d5-3ac8f9ec01dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772745967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2772745967
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1502830103
Short name T93
Test name
Test status
Simulation time 36959610 ps
CPU time 0.62 seconds
Started Mar 12 02:34:59 PM PDT 24
Finished Mar 12 02:34:59 PM PDT 24
Peak memory 202368 kb
Host smart-532baf37-35ad-4145-95c8-6a261c48795e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502830103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1502830103
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2689900557
Short name T158
Test name
Test status
Simulation time 535423775 ps
CPU time 3.63 seconds
Started Mar 12 02:35:54 PM PDT 24
Finished Mar 12 02:35:58 PM PDT 24
Peak memory 228328 kb
Host smart-9c7cd512-c26b-430c-93cd-419bf597abd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689900557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2689900557
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.168624054
Short name T200
Test name
Test status
Simulation time 8770760195 ps
CPU time 8.39 seconds
Started Mar 12 02:38:42 PM PDT 24
Finished Mar 12 02:38:50 PM PDT 24
Peak memory 203592 kb
Host smart-8c3943dc-cda1-439a-a813-e44a0b7f52ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168624054 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_unexp_stop.168624054
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3501861069
Short name T45
Test name
Test status
Simulation time 54278804545 ps
CPU time 1889.8 seconds
Started Mar 12 02:34:01 PM PDT 24
Finished Mar 12 03:05:31 PM PDT 24
Peak memory 2649112 kb
Host smart-26e026c7-22fc-4be7-9369-a81483f58725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501861069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3501861069
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4054647156
Short name T1308
Test name
Test status
Simulation time 947592763 ps
CPU time 1.73 seconds
Started Mar 12 12:42:47 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202524 kb
Host smart-614564b7-d3d9-4200-8744-f42f78ade82c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054647156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4054647156
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1703391714
Short name T177
Test name
Test status
Simulation time 10681886947 ps
CPU time 11.01 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 02:39:42 PM PDT 24
Peak memory 270240 kb
Host smart-c22c0479-5270-4735-bd6d-287a44d11982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703391714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1703391714
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_host_perf.944586190
Short name T172
Test name
Test status
Simulation time 1965432028 ps
CPU time 2.38 seconds
Started Mar 12 02:33:37 PM PDT 24
Finished Mar 12 02:33:39 PM PDT 24
Peak memory 211688 kb
Host smart-e1a9e639-b5eb-45d1-b65e-af51aa36d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944586190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.944586190
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.920869717
Short name T131
Test name
Test status
Simulation time 129331779 ps
CPU time 0.7 seconds
Started Mar 12 12:42:48 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 202092 kb
Host smart-ed0d180b-74b9-4c30-89e2-659fc2ac9dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920869717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.920869717
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2500899456
Short name T881
Test name
Test status
Simulation time 71012760446 ps
CPU time 2002.17 seconds
Started Mar 12 02:37:19 PM PDT 24
Finished Mar 12 03:10:42 PM PDT 24
Peak memory 1744564 kb
Host smart-535e15da-1389-44c0-92eb-2e99cf9d67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500899456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2500899456
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.4256604797
Short name T1049
Test name
Test status
Simulation time 10498532637 ps
CPU time 3.67 seconds
Started Mar 12 02:37:23 PM PDT 24
Finished Mar 12 02:37:27 PM PDT 24
Peak memory 216792 kb
Host smart-b5c3bee6-08e5-4689-be78-fd2fdcff3732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256604797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.4256604797
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.4102367337
Short name T183
Test name
Test status
Simulation time 82618620 ps
CPU time 0.8 seconds
Started Mar 12 02:39:37 PM PDT 24
Finished Mar 12 02:39:38 PM PDT 24
Peak memory 203256 kb
Host smart-86ab8478-6940-4933-934d-87595fc42f21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102367337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.4102367337
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1011498843
Short name T942
Test name
Test status
Simulation time 28987701294 ps
CPU time 1362.48 seconds
Started Mar 12 02:40:17 PM PDT 24
Finished Mar 12 03:03:01 PM PDT 24
Peak memory 2095820 kb
Host smart-8bea6473-01a2-4b29-89af-575a4a96895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011498843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1011498843
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3183823116
Short name T220
Test name
Test status
Simulation time 10192421416 ps
CPU time 26.14 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:40 PM PDT 24
Peak memory 360992 kb
Host smart-a56276be-5d21-48f9-84b8-ba3a7c84c0f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183823116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3183823116
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2679262538
Short name T70
Test name
Test status
Simulation time 74226256996 ps
CPU time 1564.24 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 03:00:33 PM PDT 24
Peak memory 2464208 kb
Host smart-78571f6e-88a2-4119-8f19-f143e4368c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679262538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2679262538
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1538454748
Short name T103
Test name
Test status
Simulation time 146371178 ps
CPU time 1.88 seconds
Started Mar 12 12:42:07 PM PDT 24
Finished Mar 12 12:42:09 PM PDT 24
Peak memory 202504 kb
Host smart-79bdd2f2-5652-4476-814e-d18ee2f043ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538454748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1538454748
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2969309908
Short name T101
Test name
Test status
Simulation time 49687508 ps
CPU time 1.18 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 202216 kb
Host smart-15a74a87-c2c7-4341-8235-cb87e8976ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969309908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2969309908
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1184743456
Short name T198
Test name
Test status
Simulation time 49964087 ps
CPU time 1.19 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202412 kb
Host smart-6ec99c00-820a-42c1-8e95-0d5816b6c421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184743456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1184743456
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3323630193
Short name T1278
Test name
Test status
Simulation time 15537985 ps
CPU time 0.65 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202180 kb
Host smart-c2f82d78-901c-4ccf-a7bc-f340bf3bf623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323630193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3323630193
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2662330833
Short name T212
Test name
Test status
Simulation time 7078475511 ps
CPU time 10.86 seconds
Started Mar 12 02:31:57 PM PDT 24
Finished Mar 12 02:32:08 PM PDT 24
Peak memory 218228 kb
Host smart-e3cce642-35ae-4d8e-8218-d8d3466800be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662330833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2662330833
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3857877470
Short name T814
Test name
Test status
Simulation time 1921668075 ps
CPU time 2.41 seconds
Started Mar 12 02:36:25 PM PDT 24
Finished Mar 12 02:36:28 PM PDT 24
Peak memory 203552 kb
Host smart-249ce5be-ce83-4c32-8fbe-8096b84d6322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857877470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3857877470
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3195754263
Short name T190
Test name
Test status
Simulation time 25507411655 ps
CPU time 661.71 seconds
Started Mar 12 02:36:23 PM PDT 24
Finished Mar 12 02:47:24 PM PDT 24
Peak memory 3590152 kb
Host smart-5f85fe68-1839-4da4-91aa-b73b6e48edde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195754263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3195754263
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1506159597
Short name T265
Test name
Test status
Simulation time 3532023593 ps
CPU time 39.09 seconds
Started Mar 12 02:36:38 PM PDT 24
Finished Mar 12 02:37:18 PM PDT 24
Peak memory 246184 kb
Host smart-a0b7e005-fa48-47de-acc8-f53c49746f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506159597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1506159597
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1654245735
Short name T210
Test name
Test status
Simulation time 3972549338 ps
CPU time 283.42 seconds
Started Mar 12 02:38:50 PM PDT 24
Finished Mar 12 02:43:34 PM PDT 24
Peak memory 1099508 kb
Host smart-66ffde92-b44b-4dc3-ba21-9aa08f084287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654245735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1654245735
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.817340409
Short name T66
Test name
Test status
Simulation time 1331195075 ps
CPU time 7.1 seconds
Started Mar 12 02:38:53 PM PDT 24
Finished Mar 12 02:39:00 PM PDT 24
Peak memory 212196 kb
Host smart-2e82ed68-38af-4d4e-adc3-ee8fe426a5f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817340409 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_unexp_stop.817340409
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3066632209
Short name T140
Test name
Test status
Simulation time 83096709430 ps
CPU time 481.66 seconds
Started Mar 12 02:39:54 PM PDT 24
Finished Mar 12 02:47:57 PM PDT 24
Peak memory 2123196 kb
Host smart-d2e454d5-f555-4313-9176-c3b9078edcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066632209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3066632209
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3559014944
Short name T87
Test name
Test status
Simulation time 63305673 ps
CPU time 1.27 seconds
Started Mar 12 12:42:06 PM PDT 24
Finished Mar 12 12:42:07 PM PDT 24
Peak memory 202404 kb
Host smart-6d4546f1-5ef7-4aa3-b881-64db8e485149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559014944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3559014944
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1053299834
Short name T98
Test name
Test status
Simulation time 264172906 ps
CPU time 1.26 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202600 kb
Host smart-10637d35-5076-4eae-befc-76773e7a5302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053299834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1053299834
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3650488428
Short name T75
Test name
Test status
Simulation time 10118906957 ps
CPU time 70.63 seconds
Started Mar 12 02:36:25 PM PDT 24
Finished Mar 12 02:37:36 PM PDT 24
Peak memory 575932 kb
Host smart-58df2cd0-a820-454b-828c-f472620a824b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650488428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3650488428
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3130639974
Short name T42
Test name
Test status
Simulation time 121249692 ps
CPU time 1.68 seconds
Started Mar 12 02:37:16 PM PDT 24
Finished Mar 12 02:37:18 PM PDT 24
Peak memory 211820 kb
Host smart-1a4817df-946b-4813-8bc5-a750e4063a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130639974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3130639974
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1138435315
Short name T128
Test name
Test status
Simulation time 954226861 ps
CPU time 4.49 seconds
Started Mar 12 12:42:08 PM PDT 24
Finished Mar 12 12:42:14 PM PDT 24
Peak memory 202328 kb
Host smart-56b4f719-22fb-46e8-9a78-626a9ddbaf03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138435315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1138435315
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.33585531
Short name T126
Test name
Test status
Simulation time 77140298 ps
CPU time 0.67 seconds
Started Mar 12 12:42:05 PM PDT 24
Finished Mar 12 12:42:06 PM PDT 24
Peak memory 201420 kb
Host smart-e8e1483b-3d9d-49da-b9f9-3f94fe063c20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.33585531
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1715011970
Short name T1324
Test name
Test status
Simulation time 23806228 ps
CPU time 0.93 seconds
Started Mar 12 12:42:10 PM PDT 24
Finished Mar 12 12:42:11 PM PDT 24
Peak memory 202324 kb
Host smart-d416afef-712d-45a0-bcb4-abfc43e616e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715011970 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1715011970
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2125890047
Short name T1318
Test name
Test status
Simulation time 24129626 ps
CPU time 0.68 seconds
Started Mar 12 12:42:08 PM PDT 24
Finished Mar 12 12:42:10 PM PDT 24
Peak memory 202128 kb
Host smart-b423677d-1388-485b-8aa9-c1237f27c3ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125890047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2125890047
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.527768769
Short name T1323
Test name
Test status
Simulation time 22704478 ps
CPU time 0.65 seconds
Started Mar 12 12:42:06 PM PDT 24
Finished Mar 12 12:42:07 PM PDT 24
Peak memory 202200 kb
Host smart-7c6b1e94-d059-4203-b877-392f51614287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527768769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.527768769
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2716282549
Short name T95
Test name
Test status
Simulation time 144010904 ps
CPU time 2.1 seconds
Started Mar 12 12:42:08 PM PDT 24
Finished Mar 12 12:42:11 PM PDT 24
Peak memory 202680 kb
Host smart-99995055-4611-4009-a144-9759edb91749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716282549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2716282549
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2013312623
Short name T1313
Test name
Test status
Simulation time 45843869 ps
CPU time 1 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202328 kb
Host smart-b540abf2-0630-4a99-8d49-302fc2e529f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013312623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2013312623
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.500177946
Short name T1370
Test name
Test status
Simulation time 650763030 ps
CPU time 2.55 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202436 kb
Host smart-9346298e-4401-457f-b3e9-5cdd248a699e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500177946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.500177946
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3184018175
Short name T122
Test name
Test status
Simulation time 29751803 ps
CPU time 0.68 seconds
Started Mar 12 12:42:07 PM PDT 24
Finished Mar 12 12:42:08 PM PDT 24
Peak memory 202076 kb
Host smart-d68eb8be-57fb-49f3-a00e-92a7c897f938
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184018175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3184018175
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1417593135
Short name T1327
Test name
Test status
Simulation time 37543314 ps
CPU time 0.98 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202264 kb
Host smart-f9757a70-059f-4514-8c76-31a5067ecaee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417593135 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1417593135
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2408443114
Short name T1367
Test name
Test status
Simulation time 38079940 ps
CPU time 0.7 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 202156 kb
Host smart-0582475d-dc20-4f76-90b3-76c3c20a82d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408443114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2408443114
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3337734606
Short name T1315
Test name
Test status
Simulation time 30623965 ps
CPU time 0.65 seconds
Started Mar 12 12:42:08 PM PDT 24
Finished Mar 12 12:42:09 PM PDT 24
Peak memory 202336 kb
Host smart-a707ea1c-8b47-4d53-ab09-578aa13d60d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337734606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3337734606
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.346424637
Short name T1319
Test name
Test status
Simulation time 22017023 ps
CPU time 0.76 seconds
Started Mar 12 12:42:18 PM PDT 24
Finished Mar 12 12:42:19 PM PDT 24
Peak memory 202136 kb
Host smart-a933023d-aff3-4f3a-a7c4-08eca5e3ac9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346424637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.346424637
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3271419396
Short name T1369
Test name
Test status
Simulation time 370422348 ps
CPU time 1.02 seconds
Started Mar 12 12:42:47 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202260 kb
Host smart-e141adf5-f583-4977-bf17-0891f6ad6520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271419396 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3271419396
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2819992531
Short name T1325
Test name
Test status
Simulation time 48329835 ps
CPU time 0.69 seconds
Started Mar 12 12:42:48 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202336 kb
Host smart-d4af9db5-7ae8-4480-8db5-ebcc6ffd377c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819992531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2819992531
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2994672222
Short name T133
Test name
Test status
Simulation time 82411752 ps
CPU time 0.97 seconds
Started Mar 12 12:42:48 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 202488 kb
Host smart-e71c3433-2295-40b0-b820-1a878b5cbbb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994672222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2994672222
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.263163633
Short name T1366
Test name
Test status
Simulation time 144778164 ps
CPU time 1.82 seconds
Started Mar 12 12:42:47 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 202476 kb
Host smart-fdee9030-6013-48dc-b437-ffbea6d73dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263163633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.263163633
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.792748006
Short name T1360
Test name
Test status
Simulation time 32362196 ps
CPU time 0.9 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 202040 kb
Host smart-7bd799ae-845e-46bc-9aaf-2c9dda5d8e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792748006 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.792748006
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1487936277
Short name T141
Test name
Test status
Simulation time 23842071 ps
CPU time 0.68 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202148 kb
Host smart-3d797646-cac8-44c2-bffd-1b9d367d19e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487936277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1487936277
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1525949315
Short name T1368
Test name
Test status
Simulation time 19728694 ps
CPU time 0.65 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202208 kb
Host smart-e0a30ba0-0465-492b-a21c-d0ae06f164a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525949315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1525949315
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2142273873
Short name T136
Test name
Test status
Simulation time 58651781 ps
CPU time 1.1 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202500 kb
Host smart-57dd3b29-2065-4f30-9ce5-bab73bab071e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142273873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2142273873
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1766720412
Short name T81
Test name
Test status
Simulation time 272727765 ps
CPU time 1.63 seconds
Started Mar 12 12:42:46 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202596 kb
Host smart-42976ac9-9b25-4982-a3d3-ae72ff3a966a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766720412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1766720412
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.698952818
Short name T89
Test name
Test status
Simulation time 64724574 ps
CPU time 1.31 seconds
Started Mar 12 12:42:45 PM PDT 24
Finished Mar 12 12:42:47 PM PDT 24
Peak memory 202520 kb
Host smart-fa9193bb-0490-4dac-b95c-57b41ee1e2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698952818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.698952818
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2382696916
Short name T1282
Test name
Test status
Simulation time 43287814 ps
CPU time 0.85 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202348 kb
Host smart-a27911c2-e9d7-431d-bd79-7f003dea6b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382696916 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2382696916
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1399900911
Short name T120
Test name
Test status
Simulation time 30418463 ps
CPU time 0.72 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 201632 kb
Host smart-911523da-4992-4efb-bbd0-bac975adb3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399900911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1399900911
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3660991885
Short name T1363
Test name
Test status
Simulation time 14770710 ps
CPU time 0.64 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:13 PM PDT 24
Peak memory 201916 kb
Host smart-87cc0ac5-a21c-419d-986f-63287581c908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660991885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3660991885
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2659558966
Short name T137
Test name
Test status
Simulation time 35114277 ps
CPU time 0.75 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202288 kb
Host smart-49c753c1-3bf5-4202-94fb-447066a6d1c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659558966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2659558966
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.799941722
Short name T96
Test name
Test status
Simulation time 296231905 ps
CPU time 1.67 seconds
Started Mar 12 12:42:56 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202624 kb
Host smart-fbe4af6b-a042-4c3d-b096-4ae07412f57f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799941722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.799941722
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3770383137
Short name T1284
Test name
Test status
Simulation time 174484484 ps
CPU time 0.95 seconds
Started Mar 12 12:43:00 PM PDT 24
Finished Mar 12 12:43:01 PM PDT 24
Peak memory 202288 kb
Host smart-63a13143-a0f7-486a-a356-9730c8dd09d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770383137 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3770383137
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2139818242
Short name T1364
Test name
Test status
Simulation time 206799234 ps
CPU time 0.63 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 201604 kb
Host smart-9f43581a-a579-44a9-9cee-df230b712143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139818242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2139818242
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3065682757
Short name T155
Test name
Test status
Simulation time 19454713 ps
CPU time 0.64 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202300 kb
Host smart-2e82ca45-50cf-4cf1-9128-37905883f267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065682757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3065682757
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1538004111
Short name T130
Test name
Test status
Simulation time 43446588 ps
CPU time 0.91 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202540 kb
Host smart-b610aa03-4172-49b7-802f-d617dd6298f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538004111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1538004111
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.4122379847
Short name T1322
Test name
Test status
Simulation time 41499633 ps
CPU time 1.11 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 202068 kb
Host smart-f7e09d7a-c747-4561-b05d-c4c15d6ff011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122379847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.4122379847
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1569845682
Short name T1309
Test name
Test status
Simulation time 756190769 ps
CPU time 1.93 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202516 kb
Host smart-03cda71c-c15a-4afa-931d-fbc1bd80be9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569845682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1569845682
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1031742161
Short name T142
Test name
Test status
Simulation time 81499334 ps
CPU time 0.73 seconds
Started Mar 12 12:43:00 PM PDT 24
Finished Mar 12 12:43:01 PM PDT 24
Peak memory 202256 kb
Host smart-60a2a6c9-7529-4c7c-bc18-c18416ffc952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031742161 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1031742161
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1159687295
Short name T118
Test name
Test status
Simulation time 31090684 ps
CPU time 0.69 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202128 kb
Host smart-9554b827-8be8-401a-9e8e-571c9c347d3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159687295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1159687295
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.4152644965
Short name T1306
Test name
Test status
Simulation time 15784178 ps
CPU time 0.66 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:13 PM PDT 24
Peak memory 201948 kb
Host smart-6fb9ec67-63f6-448a-bd8b-5f8369997450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152644965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4152644965
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1948077307
Short name T1353
Test name
Test status
Simulation time 575216372 ps
CPU time 1.02 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202372 kb
Host smart-9b94c33f-eeb3-4b22-a7a2-2c1bc19821e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948077307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1948077307
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.90995222
Short name T82
Test name
Test status
Simulation time 73591062 ps
CPU time 1.85 seconds
Started Mar 12 12:42:56 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202640 kb
Host smart-be7fb6ce-a949-4a30-89a7-edbaefc5e14a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90995222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.90995222
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3163989652
Short name T1340
Test name
Test status
Simulation time 38710318 ps
CPU time 0.9 seconds
Started Mar 12 12:42:56 PM PDT 24
Finished Mar 12 12:42:57 PM PDT 24
Peak memory 202264 kb
Host smart-1c080362-ed51-4750-8f1d-7c52d9bd3f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163989652 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3163989652
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4182700717
Short name T1290
Test name
Test status
Simulation time 21360004 ps
CPU time 0.66 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 201944 kb
Host smart-5b57431e-56f3-4c04-ba46-f99ab7717edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182700717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4182700717
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.4101657956
Short name T1295
Test name
Test status
Simulation time 15548692 ps
CPU time 0.62 seconds
Started Mar 12 12:42:55 PM PDT 24
Finished Mar 12 12:42:56 PM PDT 24
Peak memory 202316 kb
Host smart-638bd36e-0ce5-42f1-bdcc-5ba869fdbb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101657956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.4101657956
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3947057285
Short name T1376
Test name
Test status
Simulation time 42334105 ps
CPU time 0.95 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202200 kb
Host smart-241243c5-f891-4abd-b6e9-73d912625c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947057285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3947057285
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1272928152
Short name T1335
Test name
Test status
Simulation time 404627371 ps
CPU time 2.1 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202496 kb
Host smart-6da34521-1d6b-4b27-9033-28e27b26fca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272928152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1272928152
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.417079027
Short name T1339
Test name
Test status
Simulation time 361509885 ps
CPU time 1.24 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202428 kb
Host smart-d419faee-c916-427d-897e-03b5cd3cd0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417079027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.417079027
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1655539996
Short name T1351
Test name
Test status
Simulation time 32195887 ps
CPU time 0.88 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202256 kb
Host smart-1733efaf-9e76-434f-a65b-202ced73a286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655539996 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1655539996
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3529614742
Short name T1314
Test name
Test status
Simulation time 129345326 ps
CPU time 0.63 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 201540 kb
Host smart-5cd68927-ac5b-423b-bb0b-a52a9dce1f78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529614742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3529614742
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2336077151
Short name T1294
Test name
Test status
Simulation time 26360998 ps
CPU time 0.62 seconds
Started Mar 12 12:42:56 PM PDT 24
Finished Mar 12 12:42:57 PM PDT 24
Peak memory 202204 kb
Host smart-74ebb216-d47c-4923-b132-7d10264af0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336077151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2336077151
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3684128845
Short name T132
Test name
Test status
Simulation time 38424387 ps
CPU time 0.97 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202456 kb
Host smart-c345c0bb-30bd-4718-889c-745a580a7f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684128845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3684128845
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.604973895
Short name T88
Test name
Test status
Simulation time 110962118 ps
CPU time 1.5 seconds
Started Mar 12 12:42:59 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202612 kb
Host smart-df8bde44-560d-494d-962f-2ad8983e32af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604973895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.604973895
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3490243958
Short name T78
Test name
Test status
Simulation time 294635745 ps
CPU time 1.22 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 202160 kb
Host smart-541c9ff5-cf54-4abd-8c20-77acfe96bf9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490243958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3490243958
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2198139824
Short name T1307
Test name
Test status
Simulation time 126841855 ps
CPU time 0.87 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202232 kb
Host smart-769bb073-1597-4c2b-87bd-75273499c606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198139824 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2198139824
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2574391768
Short name T138
Test name
Test status
Simulation time 21423665 ps
CPU time 0.66 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 201812 kb
Host smart-72a9aba2-ff9c-48db-b2e4-3bc5ae251f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574391768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2574391768
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.939515895
Short name T1346
Test name
Test status
Simulation time 15583417 ps
CPU time 0.62 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 202212 kb
Host smart-393a8c79-9500-4616-a837-c2122ef8c9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939515895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.939515895
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.669177433
Short name T1343
Test name
Test status
Simulation time 85466885 ps
CPU time 0.78 seconds
Started Mar 12 12:42:58 PM PDT 24
Finished Mar 12 12:42:59 PM PDT 24
Peak memory 202204 kb
Host smart-3488d324-85cc-435c-8efc-cf18b70099e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669177433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.669177433
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1812595037
Short name T102
Test name
Test status
Simulation time 168371105 ps
CPU time 2.36 seconds
Started Mar 12 12:42:57 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 202544 kb
Host smart-533b4895-750e-456c-9468-53ad9d464413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812595037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1812595037
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2396476755
Short name T1349
Test name
Test status
Simulation time 27882774 ps
CPU time 0.73 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202352 kb
Host smart-891c802f-b36c-4f57-9860-b4889e69f122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396476755 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2396476755
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.592190857
Short name T1271
Test name
Test status
Simulation time 18317418 ps
CPU time 0.64 seconds
Started Mar 12 12:43:08 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 201308 kb
Host smart-5652a749-4471-46ed-9fd0-8cd4a4744eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592190857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.592190857
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2886199584
Short name T1332
Test name
Test status
Simulation time 48839818 ps
CPU time 0.64 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202180 kb
Host smart-ff1cab08-2e87-436c-9dbe-3995a6229d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886199584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2886199584
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3363753703
Short name T1374
Test name
Test status
Simulation time 201715338 ps
CPU time 1.73 seconds
Started Mar 12 12:43:06 PM PDT 24
Finished Mar 12 12:43:08 PM PDT 24
Peak memory 202576 kb
Host smart-0394ab56-b4ac-414e-a972-218b6e12cda1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363753703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3363753703
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1716754713
Short name T1310
Test name
Test status
Simulation time 195645195 ps
CPU time 1.98 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:08 PM PDT 24
Peak memory 202396 kb
Host smart-1940fbdc-bdb8-4e07-999f-ab2e00c489a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716754713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1716754713
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4134050690
Short name T115
Test name
Test status
Simulation time 148995948 ps
CPU time 0.79 seconds
Started Mar 12 12:43:06 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202260 kb
Host smart-0ea07a17-6388-4002-b2fa-e4b962e3ff51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134050690 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4134050690
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.492180957
Short name T1344
Test name
Test status
Simulation time 53846899 ps
CPU time 0.63 seconds
Started Mar 12 12:43:06 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202080 kb
Host smart-b1820556-8215-44fc-8a41-4389f8de1eba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492180957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.492180957
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1588693366
Short name T1361
Test name
Test status
Simulation time 51607006 ps
CPU time 0.59 seconds
Started Mar 12 12:43:03 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 202320 kb
Host smart-8e427ba5-96a4-464a-b828-7e89c72c6c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588693366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1588693366
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4264525645
Short name T135
Test name
Test status
Simulation time 18645740 ps
CPU time 0.72 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202180 kb
Host smart-dacc59f5-7af5-4bce-be4a-96b1d583f54a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264525645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.4264525645
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2526525479
Short name T1292
Test name
Test status
Simulation time 65949907 ps
CPU time 1.42 seconds
Started Mar 12 12:43:07 PM PDT 24
Finished Mar 12 12:43:08 PM PDT 24
Peak memory 202580 kb
Host smart-185c755f-c567-45be-a4fa-3e7a23afcf41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526525479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2526525479
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1049152177
Short name T199
Test name
Test status
Simulation time 68775452 ps
CPU time 1.34 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202544 kb
Host smart-061ce87f-3d85-44bb-a956-525d824a6fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049152177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1049152177
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2259059923
Short name T123
Test name
Test status
Simulation time 137685359 ps
CPU time 1.46 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:21 PM PDT 24
Peak memory 202348 kb
Host smart-f693c094-7b5c-4038-a6bb-3e43fd36d8e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259059923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2259059923
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3052428177
Short name T124
Test name
Test status
Simulation time 503011311 ps
CPU time 3.77 seconds
Started Mar 12 12:42:18 PM PDT 24
Finished Mar 12 12:42:22 PM PDT 24
Peak memory 202488 kb
Host smart-ac74b553-e314-4ddc-8362-31852df8484f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052428177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3052428177
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4261019556
Short name T1305
Test name
Test status
Simulation time 25577946 ps
CPU time 0.62 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:19 PM PDT 24
Peak memory 201168 kb
Host smart-88d59748-76dd-42fa-8666-f46a6bce6a4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261019556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4261019556
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.21046561
Short name T116
Test name
Test status
Simulation time 35616050 ps
CPU time 0.92 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202272 kb
Host smart-b84bb100-025d-4a8e-b2a3-c141ba67ad94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046561 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.21046561
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.253926988
Short name T1341
Test name
Test status
Simulation time 22699339 ps
CPU time 0.69 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 202120 kb
Host smart-a8e01213-d600-4e93-a165-c2e0b34798d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253926988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.253926988
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.938872401
Short name T1342
Test name
Test status
Simulation time 57426059 ps
CPU time 0.63 seconds
Started Mar 12 12:42:18 PM PDT 24
Finished Mar 12 12:42:19 PM PDT 24
Peak memory 202324 kb
Host smart-12177a88-ae95-4245-ab9a-f5acc7dbd320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938872401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.938872401
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2503953286
Short name T1358
Test name
Test status
Simulation time 187369505 ps
CPU time 2.46 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:21 PM PDT 24
Peak memory 202480 kb
Host smart-26f83358-2b33-4b3d-a66e-dc7abbf96636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503953286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2503953286
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.82863840
Short name T97
Test name
Test status
Simulation time 58314433 ps
CPU time 1.2 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 202404 kb
Host smart-f379be42-2a0f-4f39-8e8a-c1c4a55aa997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82863840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.82863840
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2356846288
Short name T1331
Test name
Test status
Simulation time 30598266 ps
CPU time 0.62 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 202280 kb
Host smart-ce2d321b-4d52-4c33-9d46-83d710bd25a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356846288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2356846288
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2233169466
Short name T1330
Test name
Test status
Simulation time 21620607 ps
CPU time 0.66 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 202280 kb
Host smart-7750c350-1e44-401d-866d-7a34e3c1263d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233169466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2233169466
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4131892386
Short name T1357
Test name
Test status
Simulation time 66865096 ps
CPU time 0.66 seconds
Started Mar 12 12:43:06 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202356 kb
Host smart-e502586a-f82b-40fd-8a06-62d62235f2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131892386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4131892386
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2788284794
Short name T1275
Test name
Test status
Simulation time 48400551 ps
CPU time 0.63 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202260 kb
Host smart-234c24ad-2704-42cd-a600-5f22cab72a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788284794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2788284794
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.191374947
Short name T1350
Test name
Test status
Simulation time 44127356 ps
CPU time 0.61 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 202224 kb
Host smart-6232a7fc-0b7b-4d0a-b7c2-ddbd02d74bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191374947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.191374947
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3650169682
Short name T1326
Test name
Test status
Simulation time 16268530 ps
CPU time 0.69 seconds
Started Mar 12 12:43:05 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202216 kb
Host smart-213dc873-133a-4096-8d39-cbd45cb416b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650169682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3650169682
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2720094951
Short name T1338
Test name
Test status
Simulation time 40486061 ps
CPU time 0.63 seconds
Started Mar 12 12:43:07 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202196 kb
Host smart-7c9c2aa4-59e6-4832-b3b2-4357e53f69d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720094951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2720094951
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3392180326
Short name T1302
Test name
Test status
Simulation time 58178154 ps
CPU time 0.67 seconds
Started Mar 12 12:43:08 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 202204 kb
Host smart-0b2cd74a-6570-4e43-a285-f9d150b4bc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392180326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3392180326
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2777677723
Short name T1274
Test name
Test status
Simulation time 71145342 ps
CPU time 0.66 seconds
Started Mar 12 12:43:08 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 202188 kb
Host smart-4c61cbfc-6010-4baf-a62d-9d9c0cdb6d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777677723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2777677723
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1617918894
Short name T1316
Test name
Test status
Simulation time 82538876 ps
CPU time 1.02 seconds
Started Mar 12 12:42:25 PM PDT 24
Finished Mar 12 12:42:26 PM PDT 24
Peak memory 202344 kb
Host smart-d0782060-b1fc-49d4-9e79-90e40b1430cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617918894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1617918894
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.649002259
Short name T129
Test name
Test status
Simulation time 204739805 ps
CPU time 3.94 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:31 PM PDT 24
Peak memory 202460 kb
Host smart-ccc5d901-64a7-475c-9b0b-9441a88d8ee1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649002259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.649002259
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1250779227
Short name T121
Test name
Test status
Simulation time 24865732 ps
CPU time 0.69 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 202176 kb
Host smart-9cce8585-f901-4182-a94c-dddc37f390a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250779227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1250779227
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2788517882
Short name T1375
Test name
Test status
Simulation time 22117906 ps
CPU time 0.87 seconds
Started Mar 12 12:42:28 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 202268 kb
Host smart-473cc68b-46a8-485b-88d8-415ff15ee826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788517882 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2788517882
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2200818688
Short name T1329
Test name
Test status
Simulation time 20775173 ps
CPU time 0.73 seconds
Started Mar 12 12:42:31 PM PDT 24
Finished Mar 12 12:42:32 PM PDT 24
Peak memory 202232 kb
Host smart-e2c40b57-b480-4ee6-8a0d-36b3ed78fcad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200818688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2200818688
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1673886681
Short name T1299
Test name
Test status
Simulation time 19381757 ps
CPU time 0.67 seconds
Started Mar 12 12:42:17 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 202164 kb
Host smart-d1d6c363-846b-4a67-a4ae-8be14b9bf557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673886681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1673886681
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1033834275
Short name T79
Test name
Test status
Simulation time 335845037 ps
CPU time 1.29 seconds
Started Mar 12 12:42:19 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202532 kb
Host smart-9d3b6eea-1cfc-4757-bbbf-5ea346273868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033834275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1033834275
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2340693866
Short name T86
Test name
Test status
Simulation time 189541260 ps
CPU time 1.21 seconds
Started Mar 12 12:42:18 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 202484 kb
Host smart-ab964cf8-f32c-4ead-b80d-33e370d95118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340693866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2340693866
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1677735721
Short name T1300
Test name
Test status
Simulation time 18488587 ps
CPU time 0.67 seconds
Started Mar 12 12:43:07 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202196 kb
Host smart-4d93bc1f-9b7c-444d-bdd8-8a6cb816d018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677735721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1677735721
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2827106352
Short name T1270
Test name
Test status
Simulation time 60722835 ps
CPU time 0.65 seconds
Started Mar 12 12:43:06 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 202188 kb
Host smart-c24c317b-d132-4f2b-88b8-8dab31bcbe72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827106352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2827106352
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3930505738
Short name T1276
Test name
Test status
Simulation time 17591020 ps
CPU time 0.61 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202176 kb
Host smart-67018186-b82b-4d52-9530-3719cb6d89d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930505738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3930505738
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2033611985
Short name T1345
Test name
Test status
Simulation time 17484359 ps
CPU time 0.61 seconds
Started Mar 12 12:43:04 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 202268 kb
Host smart-4beebe7e-5e14-4ef5-b9e5-fc09b4d3b534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033611985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2033611985
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2098335684
Short name T1273
Test name
Test status
Simulation time 18187044 ps
CPU time 0.65 seconds
Started Mar 12 12:43:08 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 202192 kb
Host smart-5b764cea-4dfe-480a-b4ca-e98e38d944cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098335684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2098335684
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3976218249
Short name T1347
Test name
Test status
Simulation time 46064470 ps
CPU time 0.66 seconds
Started Mar 12 12:43:03 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 202292 kb
Host smart-fadefb70-b516-4ea7-a5d3-15725ecee666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976218249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3976218249
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2396048984
Short name T1289
Test name
Test status
Simulation time 41605549 ps
CPU time 0.69 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 202244 kb
Host smart-7ef04e42-ae72-47c0-bee4-4e7aa2f846e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396048984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2396048984
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3447517688
Short name T1297
Test name
Test status
Simulation time 17238284 ps
CPU time 0.64 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 202324 kb
Host smart-adc2cc9a-9019-4789-92fe-0a4d5cfe78ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447517688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3447517688
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3053026659
Short name T1334
Test name
Test status
Simulation time 210063622 ps
CPU time 0.6 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 202232 kb
Host smart-644243cf-4a2b-471b-97ae-cb712d6edfe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053026659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3053026659
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.404028365
Short name T1272
Test name
Test status
Simulation time 57860086 ps
CPU time 0.64 seconds
Started Mar 12 12:43:17 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 202152 kb
Host smart-3aa6a9b9-b682-45db-a828-5a45fb98a0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404028365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.404028365
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.598034852
Short name T125
Test name
Test status
Simulation time 144427107 ps
CPU time 1.05 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202396 kb
Host smart-6dbc31d7-b35e-439d-9500-a33e59b1035c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598034852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.598034852
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1523902333
Short name T1365
Test name
Test status
Simulation time 103804502 ps
CPU time 3.8 seconds
Started Mar 12 12:42:29 PM PDT 24
Finished Mar 12 12:42:33 PM PDT 24
Peak memory 202404 kb
Host smart-09d88365-cc91-4b4b-ae5c-6240ff2ac5e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523902333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1523902333
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1579870191
Short name T1286
Test name
Test status
Simulation time 35365750 ps
CPU time 0.66 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202128 kb
Host smart-5fb62023-6797-4ef1-9b1a-d0dd5c423e3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579870191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1579870191
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2366834906
Short name T1336
Test name
Test status
Simulation time 18723158 ps
CPU time 0.78 seconds
Started Mar 12 12:42:28 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202444 kb
Host smart-147c97f6-1b8d-4f8e-b61f-e1484eba3bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366834906 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2366834906
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.38991582
Short name T127
Test name
Test status
Simulation time 35190555 ps
CPU time 0.69 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202212 kb
Host smart-623d2345-7e9b-47f0-961f-10abd326c844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.38991582
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1427049600
Short name T1277
Test name
Test status
Simulation time 22045030 ps
CPU time 0.69 seconds
Started Mar 12 12:42:28 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 202104 kb
Host smart-4e5569e6-0b01-4cdc-a725-d848cd645e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427049600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1427049600
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3784201746
Short name T1303
Test name
Test status
Simulation time 40539276 ps
CPU time 0.72 seconds
Started Mar 12 12:42:28 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 202220 kb
Host smart-4dfbb6f2-f850-442e-8b9b-b79d0ee62544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784201746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3784201746
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3205558505
Short name T143
Test name
Test status
Simulation time 83949444 ps
CPU time 1.52 seconds
Started Mar 12 12:42:26 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202596 kb
Host smart-3ad378f2-ee5d-445e-bb7a-f9fd033b263a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205558505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3205558505
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.172048892
Short name T197
Test name
Test status
Simulation time 921093579 ps
CPU time 1.22 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 202580 kb
Host smart-5cce4183-305d-46c1-bf74-cf35046d7401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172048892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.172048892
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1451978254
Short name T1281
Test name
Test status
Simulation time 15673715 ps
CPU time 0.62 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 202256 kb
Host smart-f0405e8c-99d4-4f9a-9001-e672313f3f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451978254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1451978254
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1237387677
Short name T154
Test name
Test status
Simulation time 26815937 ps
CPU time 0.61 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:16 PM PDT 24
Peak memory 202328 kb
Host smart-4df856a4-a862-464e-9142-3fd3e1095621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237387677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1237387677
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1503620083
Short name T156
Test name
Test status
Simulation time 21969141 ps
CPU time 0.67 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:17 PM PDT 24
Peak memory 202328 kb
Host smart-20c0fab1-18df-4958-ad52-a9f080568e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503620083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1503620083
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.490424826
Short name T1279
Test name
Test status
Simulation time 52419506 ps
CPU time 0.63 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 202176 kb
Host smart-1260f8e7-2242-4395-a95d-54b213766237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490424826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.490424826
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1725719799
Short name T1371
Test name
Test status
Simulation time 40114288 ps
CPU time 0.65 seconds
Started Mar 12 12:43:17 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 202196 kb
Host smart-0375fb3a-dd54-4917-b5cf-6125c8c89465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725719799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1725719799
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.4013877464
Short name T1283
Test name
Test status
Simulation time 14765782 ps
CPU time 0.62 seconds
Started Mar 12 12:43:17 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 202328 kb
Host smart-340de05d-5fb5-469d-8eb4-06ea2803a576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013877464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.4013877464
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.180487507
Short name T1352
Test name
Test status
Simulation time 16977255 ps
CPU time 0.64 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:17 PM PDT 24
Peak memory 202176 kb
Host smart-d1485d8a-0e97-4e34-b339-a3a1bbb11429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180487507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.180487507
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1589186717
Short name T1321
Test name
Test status
Simulation time 31859670 ps
CPU time 0.62 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 202240 kb
Host smart-4aac93ec-b9d8-492b-be26-5536f8a2d6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589186717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1589186717
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3152792796
Short name T1333
Test name
Test status
Simulation time 16933003 ps
CPU time 0.64 seconds
Started Mar 12 12:43:17 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 202280 kb
Host smart-a9c978bf-9dd2-4b4d-b05e-06297a94da5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152792796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3152792796
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.289715351
Short name T1304
Test name
Test status
Simulation time 24800559 ps
CPU time 0.64 seconds
Started Mar 12 12:43:16 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 202188 kb
Host smart-56a1aa43-3c96-408c-a5a9-3cf92f308437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289715351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.289715351
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2169624858
Short name T1328
Test name
Test status
Simulation time 94821783 ps
CPU time 1.23 seconds
Started Mar 12 12:42:35 PM PDT 24
Finished Mar 12 12:42:37 PM PDT 24
Peak memory 202628 kb
Host smart-e0f9e16e-9727-4b7b-854b-7ebbd87903ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169624858 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2169624858
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4064822098
Short name T119
Test name
Test status
Simulation time 31245480 ps
CPU time 0.63 seconds
Started Mar 12 12:42:26 PM PDT 24
Finished Mar 12 12:42:27 PM PDT 24
Peak memory 201800 kb
Host smart-71af753c-b3d3-4c3d-a980-f022cc86ac94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064822098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4064822098
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.913710572
Short name T1355
Test name
Test status
Simulation time 18276808 ps
CPU time 0.63 seconds
Started Mar 12 12:42:26 PM PDT 24
Finished Mar 12 12:42:27 PM PDT 24
Peak memory 202168 kb
Host smart-6a7c1bff-5e09-4719-8e92-cb5431fed512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913710572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.913710572
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3979822265
Short name T1337
Test name
Test status
Simulation time 71488840 ps
CPU time 1.08 seconds
Started Mar 12 12:42:27 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202440 kb
Host smart-51c08180-6daa-4865-a5f9-3f1ae9693aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979822265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3979822265
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2756840212
Short name T1311
Test name
Test status
Simulation time 82873577 ps
CPU time 1.93 seconds
Started Mar 12 12:42:26 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 202664 kb
Host smart-fe6076ee-9f9b-4cc9-bc6a-e023ee5c9644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756840212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2756840212
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2581356235
Short name T1320
Test name
Test status
Simulation time 228656395 ps
CPU time 1.17 seconds
Started Mar 12 12:42:28 PM PDT 24
Finished Mar 12 12:42:30 PM PDT 24
Peak memory 202384 kb
Host smart-1a28e3ed-f947-41dc-974b-f9a73337d5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581356235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2581356235
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3040394150
Short name T1298
Test name
Test status
Simulation time 39036100 ps
CPU time 1.01 seconds
Started Mar 12 12:42:37 PM PDT 24
Finished Mar 12 12:42:38 PM PDT 24
Peak memory 202372 kb
Host smart-1eeb44c7-7296-4cdc-881c-1466d6bcf1d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040394150 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3040394150
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3433589022
Short name T134
Test name
Test status
Simulation time 16239437 ps
CPU time 0.64 seconds
Started Mar 12 12:42:38 PM PDT 24
Finished Mar 12 12:42:38 PM PDT 24
Peak memory 202068 kb
Host smart-a356ca1d-aece-4cdc-ac0a-c8ccdb463297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433589022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3433589022
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2934374106
Short name T1317
Test name
Test status
Simulation time 41681681 ps
CPU time 0.7 seconds
Started Mar 12 12:42:35 PM PDT 24
Finished Mar 12 12:42:36 PM PDT 24
Peak memory 202244 kb
Host smart-b1c0dfd7-5a2e-4d70-aefb-d664df80638b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934374106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2934374106
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.666567497
Short name T1359
Test name
Test status
Simulation time 348376294 ps
CPU time 1.33 seconds
Started Mar 12 12:42:37 PM PDT 24
Finished Mar 12 12:42:38 PM PDT 24
Peak memory 202524 kb
Host smart-27b70260-0674-4104-8117-28c5c7bea14b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666567497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.666567497
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.737104664
Short name T1354
Test name
Test status
Simulation time 288402654 ps
CPU time 1.84 seconds
Started Mar 12 12:42:35 PM PDT 24
Finished Mar 12 12:42:37 PM PDT 24
Peak memory 202536 kb
Host smart-2a2c8dd7-61e5-4c72-b7c3-dd6688ba9a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737104664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.737104664
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1771148990
Short name T80
Test name
Test status
Simulation time 576473344 ps
CPU time 0.87 seconds
Started Mar 12 12:42:47 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202376 kb
Host smart-8c97d7ea-a4e0-4f5c-a858-1d64b11709d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771148990 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1771148990
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1245541859
Short name T1372
Test name
Test status
Simulation time 40161902 ps
CPU time 0.68 seconds
Started Mar 12 12:42:36 PM PDT 24
Finished Mar 12 12:42:37 PM PDT 24
Peak memory 202240 kb
Host smart-7ebb41a3-7266-4089-889f-5a540fd1f8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245541859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1245541859
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.529602393
Short name T1285
Test name
Test status
Simulation time 43013662 ps
CPU time 0.62 seconds
Started Mar 12 12:42:36 PM PDT 24
Finished Mar 12 12:42:37 PM PDT 24
Peak memory 202156 kb
Host smart-32b75e6d-a098-40e2-b487-4cd84371cb0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529602393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.529602393
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1096719760
Short name T1288
Test name
Test status
Simulation time 27420893 ps
CPU time 1.03 seconds
Started Mar 12 12:42:37 PM PDT 24
Finished Mar 12 12:42:38 PM PDT 24
Peak memory 202456 kb
Host smart-5c2a26ab-51b4-458f-b59c-4f752af81708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096719760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1096719760
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1273205991
Short name T90
Test name
Test status
Simulation time 273430206 ps
CPU time 2.54 seconds
Started Mar 12 12:42:35 PM PDT 24
Finished Mar 12 12:42:38 PM PDT 24
Peak memory 202696 kb
Host smart-76455e01-fdda-4666-8aa9-d3075b234510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273205991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1273205991
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3197183120
Short name T1356
Test name
Test status
Simulation time 84644593 ps
CPU time 1.39 seconds
Started Mar 12 12:42:38 PM PDT 24
Finished Mar 12 12:42:40 PM PDT 24
Peak memory 202512 kb
Host smart-af477b87-8cdf-4a6e-ab1e-356172cc2af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197183120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3197183120
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.580760662
Short name T1312
Test name
Test status
Simulation time 25425100 ps
CPU time 0.82 seconds
Started Mar 12 12:42:50 PM PDT 24
Finished Mar 12 12:42:51 PM PDT 24
Peak memory 202236 kb
Host smart-b46d1c41-daaf-4550-b014-c1aeb48e4f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580760662 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.580760662
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.394515659
Short name T1373
Test name
Test status
Simulation time 72306429 ps
CPU time 0.68 seconds
Started Mar 12 12:42:50 PM PDT 24
Finished Mar 12 12:42:50 PM PDT 24
Peak memory 202080 kb
Host smart-0f24e531-7efd-4b94-8962-09dacb2101fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394515659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.394515659
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.297342744
Short name T1293
Test name
Test status
Simulation time 31173704 ps
CPU time 0.61 seconds
Started Mar 12 12:42:46 PM PDT 24
Finished Mar 12 12:42:46 PM PDT 24
Peak memory 202152 kb
Host smart-3da241d9-c995-4494-862c-7b1044d6354a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297342744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.297342744
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1696589913
Short name T1362
Test name
Test status
Simulation time 53313763 ps
CPU time 1.02 seconds
Started Mar 12 12:42:50 PM PDT 24
Finished Mar 12 12:42:51 PM PDT 24
Peak memory 202336 kb
Host smart-5fd0dd4c-0cbb-4749-82dc-acc8e2ced04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696589913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1696589913
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3015493973
Short name T1291
Test name
Test status
Simulation time 170693931 ps
CPU time 2.24 seconds
Started Mar 12 12:42:46 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202604 kb
Host smart-d499a9f8-b9d3-469a-9cfa-a7c22d7907cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015493973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3015493973
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.912399830
Short name T77
Test name
Test status
Simulation time 25869601 ps
CPU time 1.01 seconds
Started Mar 12 12:42:49 PM PDT 24
Finished Mar 12 12:42:50 PM PDT 24
Peak memory 202412 kb
Host smart-217fbb48-305b-408a-91dc-ff74ab9b562d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912399830 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.912399830
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2684495715
Short name T1287
Test name
Test status
Simulation time 17653415 ps
CPU time 0.66 seconds
Started Mar 12 12:42:47 PM PDT 24
Finished Mar 12 12:42:48 PM PDT 24
Peak memory 202060 kb
Host smart-0fc2f743-d4db-4034-9abe-f7ff67bc1bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684495715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2684495715
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.848264253
Short name T1280
Test name
Test status
Simulation time 24561898 ps
CPU time 0.61 seconds
Started Mar 12 12:42:49 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 202316 kb
Host smart-bba8533c-651c-4b76-abe3-31f4bbe49507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848264253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.848264253
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4204328865
Short name T1296
Test name
Test status
Simulation time 102753681 ps
CPU time 0.76 seconds
Started Mar 12 12:42:49 PM PDT 24
Finished Mar 12 12:42:50 PM PDT 24
Peak memory 202180 kb
Host smart-88195650-2ed5-454b-a824-a6dcf3f5cc67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204328865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4204328865
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2273111291
Short name T1348
Test name
Test status
Simulation time 75514582 ps
CPU time 1.54 seconds
Started Mar 12 12:42:50 PM PDT 24
Finished Mar 12 12:42:51 PM PDT 24
Peak memory 202524 kb
Host smart-2cb17580-1b6b-4385-8cd2-d183195dbacc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273111291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2273111291
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.573671018
Short name T1301
Test name
Test status
Simulation time 86615388 ps
CPU time 1.19 seconds
Started Mar 12 12:42:48 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 202492 kb
Host smart-9372b4fe-941b-4617-9f6f-0d06d1d6058e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573671018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.573671018
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1379871714
Short name T1218
Test name
Test status
Simulation time 32181190 ps
CPU time 0.6 seconds
Started Mar 12 02:32:24 PM PDT 24
Finished Mar 12 02:32:24 PM PDT 24
Peak memory 202376 kb
Host smart-bb90a5df-8393-4143-8bb6-753ab6b9970e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379871714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1379871714
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1828156766
Short name T59
Test name
Test status
Simulation time 240812362 ps
CPU time 1.63 seconds
Started Mar 12 02:31:56 PM PDT 24
Finished Mar 12 02:31:58 PM PDT 24
Peak memory 211712 kb
Host smart-bd16bc06-5609-43dc-b501-e5c3a955352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828156766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1828156766
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2061798062
Short name T1005
Test name
Test status
Simulation time 300482215 ps
CPU time 14.11 seconds
Started Mar 12 02:31:56 PM PDT 24
Finished Mar 12 02:32:10 PM PDT 24
Peak memory 229092 kb
Host smart-8c21eecb-eaca-49d3-ba4e-5ebef036245d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061798062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2061798062
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1457466795
Short name T607
Test name
Test status
Simulation time 4071632981 ps
CPU time 54.31 seconds
Started Mar 12 02:31:58 PM PDT 24
Finished Mar 12 02:32:52 PM PDT 24
Peak memory 589008 kb
Host smart-9a1924ff-113d-4c91-802f-f0c4608165fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457466795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1457466795
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3469727434
Short name T1047
Test name
Test status
Simulation time 7665413175 ps
CPU time 138.95 seconds
Started Mar 12 02:31:47 PM PDT 24
Finished Mar 12 02:34:06 PM PDT 24
Peak memory 633260 kb
Host smart-ea6d3bab-786b-4682-b1cf-ffbc24a8c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469727434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3469727434
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.143321867
Short name T627
Test name
Test status
Simulation time 94337573 ps
CPU time 0.91 seconds
Started Mar 12 02:31:50 PM PDT 24
Finished Mar 12 02:31:51 PM PDT 24
Peak memory 203344 kb
Host smart-0704c72c-dc3d-4c27-8336-3f821495be37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143321867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.143321867
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.72331743
Short name T795
Test name
Test status
Simulation time 567570930 ps
CPU time 7.91 seconds
Started Mar 12 02:31:57 PM PDT 24
Finished Mar 12 02:32:05 PM PDT 24
Peak memory 203552 kb
Host smart-3f3eeafa-187f-4e56-a566-7d5e135f6f89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72331743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.72331743
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.968774938
Short name T637
Test name
Test status
Simulation time 13646604539 ps
CPU time 198.88 seconds
Started Mar 12 02:31:48 PM PDT 24
Finished Mar 12 02:35:07 PM PDT 24
Peak memory 786768 kb
Host smart-e89ca74e-36c8-4798-9093-31243f799990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968774938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.968774938
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3649019068
Short name T412
Test name
Test status
Simulation time 2234082331 ps
CPU time 50.52 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:33:12 PM PDT 24
Peak memory 268576 kb
Host smart-c9662947-bc6d-4a35-a28b-47524f52acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649019068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3649019068
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.4080576928
Short name T1073
Test name
Test status
Simulation time 18051955 ps
CPU time 0.65 seconds
Started Mar 12 02:31:47 PM PDT 24
Finished Mar 12 02:31:48 PM PDT 24
Peak memory 202552 kb
Host smart-3f097888-bf10-4213-bfb4-8d9d0434020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080576928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4080576928
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1790218626
Short name T493
Test name
Test status
Simulation time 7641482806 ps
CPU time 62.23 seconds
Started Mar 12 02:31:55 PM PDT 24
Finished Mar 12 02:32:57 PM PDT 24
Peak memory 214500 kb
Host smart-1e284b37-5aaf-42ae-9219-4310a424b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790218626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1790218626
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.264552125
Short name T606
Test name
Test status
Simulation time 8710223602 ps
CPU time 65.16 seconds
Started Mar 12 02:31:50 PM PDT 24
Finished Mar 12 02:32:55 PM PDT 24
Peak memory 297640 kb
Host smart-3437b0b5-a07e-4ab9-914f-62eb148350cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264552125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.264552125
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2109403164
Short name T1032
Test name
Test status
Simulation time 12909538108 ps
CPU time 677.74 seconds
Started Mar 12 02:31:59 PM PDT 24
Finished Mar 12 02:43:17 PM PDT 24
Peak memory 2516420 kb
Host smart-fa61f03f-d008-44f4-b05b-d3afb36a2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109403164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2109403164
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3135002614
Short name T535
Test name
Test status
Simulation time 10274352643 ps
CPU time 15.24 seconds
Started Mar 12 02:32:13 PM PDT 24
Finished Mar 12 02:32:28 PM PDT 24
Peak memory 333992 kb
Host smart-cacfe10e-1fec-4f98-a8f0-63b55a0261f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135002614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3135002614
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2387063301
Short name T697
Test name
Test status
Simulation time 10122949015 ps
CPU time 81.6 seconds
Started Mar 12 02:32:14 PM PDT 24
Finished Mar 12 02:33:36 PM PDT 24
Peak memory 726048 kb
Host smart-7751a477-b069-4323-b65b-15cb6e317af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387063301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2387063301
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1678830820
Short name T343
Test name
Test status
Simulation time 428359287 ps
CPU time 2.42 seconds
Started Mar 12 02:32:12 PM PDT 24
Finished Mar 12 02:32:15 PM PDT 24
Peak memory 203588 kb
Host smart-39f826e9-3a5c-41e3-867e-f14dbfff6926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678830820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1678830820
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3346322490
Short name T1115
Test name
Test status
Simulation time 5195509209 ps
CPU time 3.46 seconds
Started Mar 12 02:32:11 PM PDT 24
Finished Mar 12 02:32:15 PM PDT 24
Peak memory 204024 kb
Host smart-b40b63d7-e91e-487d-8c6c-7a62db19aede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346322490 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3346322490
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1044763323
Short name T522
Test name
Test status
Simulation time 25825719989 ps
CPU time 9.48 seconds
Started Mar 12 02:32:08 PM PDT 24
Finished Mar 12 02:32:18 PM PDT 24
Peak memory 203588 kb
Host smart-81393582-dc31-4c7d-bc40-d4865067ea6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044763323 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1044763323
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.3722186927
Short name T454
Test name
Test status
Simulation time 1634917819 ps
CPU time 2.63 seconds
Started Mar 12 02:32:12 PM PDT 24
Finished Mar 12 02:32:15 PM PDT 24
Peak memory 203588 kb
Host smart-58b998df-2457-4c33-be7c-00ba2e5cd69b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722186927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.3722186927
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.292839370
Short name T1207
Test name
Test status
Simulation time 5567489860 ps
CPU time 41.08 seconds
Started Mar 12 02:31:56 PM PDT 24
Finished Mar 12 02:32:38 PM PDT 24
Peak memory 203700 kb
Host smart-84282208-04af-4cca-ad13-12144fbc7aa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292839370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.292839370
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3494516606
Short name T397
Test name
Test status
Simulation time 8303979780 ps
CPU time 49.88 seconds
Started Mar 12 02:31:57 PM PDT 24
Finished Mar 12 02:32:47 PM PDT 24
Peak memory 203528 kb
Host smart-67be8392-f4ec-4f7b-b6b9-50a98aaf6456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494516606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3494516606
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.4185283725
Short name T943
Test name
Test status
Simulation time 39529210283 ps
CPU time 187.07 seconds
Started Mar 12 02:31:59 PM PDT 24
Finished Mar 12 02:35:06 PM PDT 24
Peak memory 2516168 kb
Host smart-e0c779da-c661-457a-a0b6-a674b2e4db8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185283725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.4185283725
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.4136458598
Short name T1139
Test name
Test status
Simulation time 19424067776 ps
CPU time 89.81 seconds
Started Mar 12 02:31:57 PM PDT 24
Finished Mar 12 02:33:27 PM PDT 24
Peak memory 1089524 kb
Host smart-4ba9f170-629a-4db6-9a9a-9946f27754a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136458598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.4136458598
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.225436641
Short name T482
Test name
Test status
Simulation time 7133365630 ps
CPU time 8.17 seconds
Started Mar 12 02:32:12 PM PDT 24
Finished Mar 12 02:32:20 PM PDT 24
Peak memory 215924 kb
Host smart-b1e264f1-18cf-4a26-8028-aee24a8a30fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225436641 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.225436641
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.492947442
Short name T290
Test name
Test status
Simulation time 3449533706 ps
CPU time 4.84 seconds
Started Mar 12 02:32:12 PM PDT 24
Finished Mar 12 02:32:17 PM PDT 24
Peak memory 203628 kb
Host smart-cb3476c6-915a-440e-bee3-2cadf8bf4456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492947442 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_unexp_stop.492947442
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2026271042
Short name T718
Test name
Test status
Simulation time 66400123 ps
CPU time 0.59 seconds
Started Mar 12 02:32:40 PM PDT 24
Finished Mar 12 02:32:41 PM PDT 24
Peak memory 202328 kb
Host smart-08d057e2-f7ef-49dc-81d8-9c2d3efb9d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026271042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2026271042
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3324189181
Short name T625
Test name
Test status
Simulation time 53965093 ps
CPU time 1.27 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:32:24 PM PDT 24
Peak memory 203572 kb
Host smart-f8968ce5-37d7-4d23-b79c-14da2773525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324189181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3324189181
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3217060304
Short name T303
Test name
Test status
Simulation time 796752669 ps
CPU time 22.72 seconds
Started Mar 12 02:32:23 PM PDT 24
Finished Mar 12 02:32:46 PM PDT 24
Peak memory 293040 kb
Host smart-1b9dd2cd-4182-4f6c-8feb-f2045bbe0266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217060304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3217060304
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1561074370
Short name T853
Test name
Test status
Simulation time 11273292271 ps
CPU time 108.34 seconds
Started Mar 12 02:32:20 PM PDT 24
Finished Mar 12 02:34:09 PM PDT 24
Peak memory 878856 kb
Host smart-9579e279-d96a-4bc4-9a90-241be968f112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561074370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1561074370
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.943616633
Short name T310
Test name
Test status
Simulation time 1546951920 ps
CPU time 50.28 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:33:12 PM PDT 24
Peak memory 586868 kb
Host smart-f7c9ab27-48f1-4842-a38a-a8b337da2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943616633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.943616633
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2193286838
Short name T723
Test name
Test status
Simulation time 237815908 ps
CPU time 0.88 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:32:23 PM PDT 24
Peak memory 203288 kb
Host smart-e0a496a7-4b32-48be-bc38-d4e323d4cc22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193286838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2193286838
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1538594524
Short name T1189
Test name
Test status
Simulation time 566919170 ps
CPU time 6.51 seconds
Started Mar 12 02:32:23 PM PDT 24
Finished Mar 12 02:32:29 PM PDT 24
Peak memory 257664 kb
Host smart-b15c3aa5-5f40-4da7-b965-f1341067fb78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538594524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1538594524
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2127574011
Short name T877
Test name
Test status
Simulation time 4661100556 ps
CPU time 149.63 seconds
Started Mar 12 02:32:24 PM PDT 24
Finished Mar 12 02:34:54 PM PDT 24
Peak memory 1327904 kb
Host smart-7c3b930c-dbab-42fb-bb6c-e226ee8b094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127574011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2127574011
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2089598448
Short name T41
Test name
Test status
Simulation time 5073899986 ps
CPU time 91.78 seconds
Started Mar 12 02:32:32 PM PDT 24
Finished Mar 12 02:34:04 PM PDT 24
Peak memory 245668 kb
Host smart-7299887d-b1fc-4280-966c-c3fb9204f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089598448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2089598448
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.176237910
Short name T510
Test name
Test status
Simulation time 20149103 ps
CPU time 0.65 seconds
Started Mar 12 02:32:23 PM PDT 24
Finished Mar 12 02:32:24 PM PDT 24
Peak memory 203216 kb
Host smart-a6e7b3c6-08b5-48ba-bef6-8452dfacb5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176237910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.176237910
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2146838452
Short name T21
Test name
Test status
Simulation time 2879552778 ps
CPU time 86.78 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:33:49 PM PDT 24
Peak memory 252140 kb
Host smart-2c18e7b8-e005-441c-ae6d-4da0e0640440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146838452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2146838452
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4203024319
Short name T495
Test name
Test status
Simulation time 28104827815 ps
CPU time 74.36 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:33:36 PM PDT 24
Peak memory 297348 kb
Host smart-789ad332-aee4-4443-bb1a-b34f703b7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203024319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4203024319
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1617731225
Short name T1091
Test name
Test status
Simulation time 918347330 ps
CPU time 9.31 seconds
Started Mar 12 02:32:22 PM PDT 24
Finished Mar 12 02:32:32 PM PDT 24
Peak memory 219972 kb
Host smart-6a06dacb-82e2-42c5-98e1-f201dd7e9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617731225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1617731225
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3508624648
Short name T85
Test name
Test status
Simulation time 138156528 ps
CPU time 0.94 seconds
Started Mar 12 02:32:38 PM PDT 24
Finished Mar 12 02:32:39 PM PDT 24
Peak memory 220572 kb
Host smart-4f4464d7-68fa-4f20-8ac5-c450f28cdb3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508624648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3508624648
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.421341683
Short name T699
Test name
Test status
Simulation time 1890467415 ps
CPU time 4.3 seconds
Started Mar 12 02:32:32 PM PDT 24
Finished Mar 12 02:32:37 PM PDT 24
Peak memory 203564 kb
Host smart-501be3af-d267-4395-9019-181e1e4749a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421341683 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.421341683
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.885424552
Short name T740
Test name
Test status
Simulation time 10047394832 ps
CPU time 74.55 seconds
Started Mar 12 02:32:29 PM PDT 24
Finished Mar 12 02:33:44 PM PDT 24
Peak memory 607248 kb
Host smart-1e09a1d5-ddf7-4018-9303-76372e63ac15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885424552 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.885424552
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.4112813763
Short name T705
Test name
Test status
Simulation time 10065349430 ps
CPU time 89.41 seconds
Started Mar 12 02:32:29 PM PDT 24
Finished Mar 12 02:33:59 PM PDT 24
Peak memory 665888 kb
Host smart-b446599e-618c-46e7-8209-43789fdb2fb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112813763 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.4112813763
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3167329663
Short name T49
Test name
Test status
Simulation time 10930370723 ps
CPU time 12.85 seconds
Started Mar 12 02:32:29 PM PDT 24
Finished Mar 12 02:32:42 PM PDT 24
Peak memory 203884 kb
Host smart-72a7cd29-f8a3-4ac9-a78d-4bc3ed563055
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167329663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3167329663
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2865228850
Short name T647
Test name
Test status
Simulation time 547621801 ps
CPU time 2.6 seconds
Started Mar 12 02:32:32 PM PDT 24
Finished Mar 12 02:32:35 PM PDT 24
Peak memory 203588 kb
Host smart-de32e202-7405-4ce8-9d96-91a470a174f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865228850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2865228850
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3008821352
Short name T525
Test name
Test status
Simulation time 6546631594 ps
CPU time 6.11 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 02:32:34 PM PDT 24
Peak memory 207792 kb
Host smart-3300b6e9-4eda-4a56-8c43-466c719355a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008821352 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3008821352
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_perf.4067456737
Short name T401
Test name
Test status
Simulation time 1560962747 ps
CPU time 2.7 seconds
Started Mar 12 02:32:29 PM PDT 24
Finished Mar 12 02:32:32 PM PDT 24
Peak memory 203560 kb
Host smart-0ef05e4c-d530-4776-a650-91c7ec888a55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067456737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.4067456737
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.3377712865
Short name T671
Test name
Test status
Simulation time 67171718408 ps
CPU time 1104.17 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 02:50:52 PM PDT 24
Peak memory 4521636 kb
Host smart-01fdaa0d-325a-42c1-bd78-9c4bcc250ee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377712865 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.3377712865
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.928770884
Short name T371
Test name
Test status
Simulation time 691899638 ps
CPU time 4.42 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 02:32:34 PM PDT 24
Peak memory 203580 kb
Host smart-02328d4b-b38c-441f-83fb-c90741bccd21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928770884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.928770884
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3142766057
Short name T313
Test name
Test status
Simulation time 15903877779 ps
CPU time 2179.32 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 3779172 kb
Host smart-153b0024-9c8a-4541-b551-da04e96df43d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142766057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3142766057
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1704376798
Short name T18
Test name
Test status
Simulation time 6658403859 ps
CPU time 7.54 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 02:32:35 PM PDT 24
Peak memory 203596 kb
Host smart-eac1e4f1-d90d-49ff-8731-24396070d705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704376798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1704376798
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.3507133690
Short name T974
Test name
Test status
Simulation time 3807234818 ps
CPU time 6.14 seconds
Started Mar 12 02:32:28 PM PDT 24
Finished Mar 12 02:32:35 PM PDT 24
Peak memory 211836 kb
Host smart-01586a05-6f73-4a12-954e-75744025ea66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507133690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.3507133690
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2949738817
Short name T1063
Test name
Test status
Simulation time 41041673 ps
CPU time 1.12 seconds
Started Mar 12 02:34:53 PM PDT 24
Finished Mar 12 02:34:56 PM PDT 24
Peak memory 219868 kb
Host smart-f7c3be8f-a3f1-4c72-9181-df3245496815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949738817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2949738817
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.322339458
Short name T1221
Test name
Test status
Simulation time 695144740 ps
CPU time 39.13 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:37 PM PDT 24
Peak memory 357352 kb
Host smart-e1f70cac-dd78-4995-951a-915ba888bb2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322339458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.322339458
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1657085043
Short name T113
Test name
Test status
Simulation time 6192169186 ps
CPU time 94.14 seconds
Started Mar 12 02:34:53 PM PDT 24
Finished Mar 12 02:36:29 PM PDT 24
Peak memory 860300 kb
Host smart-d63bb9e7-783c-43ac-b6f7-84d291ffeb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657085043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1657085043
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1418006103
Short name T938
Test name
Test status
Simulation time 5536334007 ps
CPU time 221.79 seconds
Started Mar 12 02:34:52 PM PDT 24
Finished Mar 12 02:38:34 PM PDT 24
Peak memory 826244 kb
Host smart-56b65843-16f8-4b78-b1fe-57e112ed5954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418006103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1418006103
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1097661433
Short name T1098
Test name
Test status
Simulation time 275395588 ps
CPU time 0.89 seconds
Started Mar 12 02:34:53 PM PDT 24
Finished Mar 12 02:34:56 PM PDT 24
Peak memory 203332 kb
Host smart-2af1d859-56be-4f35-ada3-d764eaf6aa3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097661433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1097661433
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1315880284
Short name T333
Test name
Test status
Simulation time 173046109 ps
CPU time 3.57 seconds
Started Mar 12 02:34:56 PM PDT 24
Finished Mar 12 02:34:59 PM PDT 24
Peak memory 203556 kb
Host smart-68e5f93c-b027-475b-b48e-e31082a58c7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315880284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1315880284
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3981069060
Short name T380
Test name
Test status
Simulation time 6676003947 ps
CPU time 85.42 seconds
Started Mar 12 02:35:00 PM PDT 24
Finished Mar 12 02:36:26 PM PDT 24
Peak memory 235292 kb
Host smart-b46844e1-e657-492c-81d8-8b1df30609ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981069060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3981069060
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3505753824
Short name T289
Test name
Test status
Simulation time 43125782 ps
CPU time 0.61 seconds
Started Mar 12 02:34:52 PM PDT 24
Finished Mar 12 02:34:53 PM PDT 24
Peak memory 202508 kb
Host smart-017e0226-613c-4456-b135-6f27c7db46bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505753824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3505753824
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2873989544
Short name T889
Test name
Test status
Simulation time 7315564579 ps
CPU time 72.99 seconds
Started Mar 12 02:34:55 PM PDT 24
Finished Mar 12 02:36:08 PM PDT 24
Peak memory 370808 kb
Host smart-f84da41a-5897-4225-b1c2-8c486154b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873989544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2873989544
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3662785469
Short name T986
Test name
Test status
Simulation time 2334315968 ps
CPU time 49.44 seconds
Started Mar 12 02:34:53 PM PDT 24
Finished Mar 12 02:35:45 PM PDT 24
Peak memory 247608 kb
Host smart-b3f0656d-bce0-404e-afad-d18fe00de797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662785469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3662785469
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2903374320
Short name T1022
Test name
Test status
Simulation time 56665485460 ps
CPU time 2098.46 seconds
Started Mar 12 02:34:56 PM PDT 24
Finished Mar 12 03:09:56 PM PDT 24
Peak memory 3443348 kb
Host smart-e0e0d96f-6230-4125-8418-800fa5aa68af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903374320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2903374320
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2401249860
Short name T620
Test name
Test status
Simulation time 3623743758 ps
CPU time 16.34 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:14 PM PDT 24
Peak memory 217712 kb
Host smart-5526778d-1b26-469c-85a5-28c799a4df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401249860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2401249860
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.4180010745
Short name T279
Test name
Test status
Simulation time 10208805367 ps
CPU time 14.07 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:12 PM PDT 24
Peak memory 283668 kb
Host smart-c4d799eb-b488-469d-8a52-54c49f34d24d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180010745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.4180010745
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1423308476
Short name T702
Test name
Test status
Simulation time 10042469825 ps
CPU time 80.44 seconds
Started Mar 12 02:35:00 PM PDT 24
Finished Mar 12 02:36:21 PM PDT 24
Peak memory 653540 kb
Host smart-7de523c1-71ac-4501-afac-8d44a042cced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423308476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1423308476
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1900268053
Short name T1094
Test name
Test status
Simulation time 2177556052 ps
CPU time 2.2 seconds
Started Mar 12 02:35:00 PM PDT 24
Finished Mar 12 02:35:03 PM PDT 24
Peak memory 203608 kb
Host smart-e62d8c61-e388-410b-a646-5a34bdfd1c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900268053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1900268053
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1543174824
Short name T159
Test name
Test status
Simulation time 5813190972 ps
CPU time 6.45 seconds
Started Mar 12 02:34:56 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 206620 kb
Host smart-379d39bd-9ddc-4562-aaec-7a9f7a796fb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543174824 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1543174824
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.949686752
Short name T515
Test name
Test status
Simulation time 11603873407 ps
CPU time 28.2 seconds
Started Mar 12 02:34:55 PM PDT 24
Finished Mar 12 02:35:24 PM PDT 24
Peak memory 671444 kb
Host smart-4360e72e-b4ac-48c2-944e-6b6df5d164a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949686752 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.949686752
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.3341016633
Short name T298
Test name
Test status
Simulation time 393315171 ps
CPU time 2.58 seconds
Started Mar 12 02:34:59 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 203612 kb
Host smart-9a8513ad-a9e8-471f-80e5-1c11834eeb09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341016633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.3341016633
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2388515662
Short name T775
Test name
Test status
Simulation time 5366149110 ps
CPU time 33.87 seconds
Started Mar 12 02:34:52 PM PDT 24
Finished Mar 12 02:35:27 PM PDT 24
Peak memory 203688 kb
Host smart-aba08ab8-ad01-4c26-9973-174e02a6aff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388515662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2388515662
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.2212823547
Short name T1050
Test name
Test status
Simulation time 63380684010 ps
CPU time 2260.51 seconds
Started Mar 12 02:35:02 PM PDT 24
Finished Mar 12 03:12:44 PM PDT 24
Peak memory 7098500 kb
Host smart-d75de6b3-16e2-4059-88bb-129548524813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212823547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.2212823547
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3648059060
Short name T475
Test name
Test status
Simulation time 1362071474 ps
CPU time 12.55 seconds
Started Mar 12 02:34:56 PM PDT 24
Finished Mar 12 02:35:08 PM PDT 24
Peak memory 207244 kb
Host smart-5562334f-8aed-4328-bda4-0f944f0bf673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648059060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3648059060
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1788128692
Short name T250
Test name
Test status
Simulation time 33317246508 ps
CPU time 281.12 seconds
Started Mar 12 02:34:54 PM PDT 24
Finished Mar 12 02:39:37 PM PDT 24
Peak memory 3355884 kb
Host smart-5c5d5468-a49c-49a8-83db-087d51369900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788128692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1788128692
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.205398277
Short name T964
Test name
Test status
Simulation time 3412090705 ps
CPU time 7.36 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:05 PM PDT 24
Peak memory 203460 kb
Host smart-3bd5f227-6cde-4668-865a-1915f742b204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205398277 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.205398277
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.2133473899
Short name T931
Test name
Test status
Simulation time 1090514652 ps
CPU time 7.25 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:05 PM PDT 24
Peak memory 203556 kb
Host smart-74ef5981-6dca-4b9e-b169-1a27d5203119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133473899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.2133473899
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.4145036229
Short name T1111
Test name
Test status
Simulation time 41999709 ps
CPU time 0.62 seconds
Started Mar 12 02:35:16 PM PDT 24
Finished Mar 12 02:35:17 PM PDT 24
Peak memory 202344 kb
Host smart-877f2194-a58f-4989-b58f-6ac9fb4c3380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145036229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.4145036229
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2245205945
Short name T908
Test name
Test status
Simulation time 36070350 ps
CPU time 1.63 seconds
Started Mar 12 02:35:09 PM PDT 24
Finished Mar 12 02:35:11 PM PDT 24
Peak memory 211764 kb
Host smart-12ce94f3-b927-4a37-89de-a360a3e501f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245205945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2245205945
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.4243005500
Short name T368
Test name
Test status
Simulation time 567078609 ps
CPU time 12.39 seconds
Started Mar 12 02:35:04 PM PDT 24
Finished Mar 12 02:35:17 PM PDT 24
Peak memory 329368 kb
Host smart-c80a42fa-8862-49bb-bc3f-99a484dda852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243005500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.4243005500
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2744535371
Short name T411
Test name
Test status
Simulation time 7430759369 ps
CPU time 42.85 seconds
Started Mar 12 02:35:06 PM PDT 24
Finished Mar 12 02:35:49 PM PDT 24
Peak memory 472236 kb
Host smart-0c58e3d9-1238-43fa-9169-d502e26d1aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744535371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2744535371
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.659434181
Short name T287
Test name
Test status
Simulation time 10276775300 ps
CPU time 83.91 seconds
Started Mar 12 02:34:59 PM PDT 24
Finished Mar 12 02:36:23 PM PDT 24
Peak memory 741016 kb
Host smart-b9cd53b7-a7e6-41c9-a1f4-d6b3131c2fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659434181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.659434181
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3735910198
Short name T676
Test name
Test status
Simulation time 72090528 ps
CPU time 0.76 seconds
Started Mar 12 02:35:04 PM PDT 24
Finished Mar 12 02:35:05 PM PDT 24
Peak memory 202608 kb
Host smart-c2fc0d2f-d190-4679-b1a1-b2db1619042d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735910198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3735910198
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3840330664
Short name T1195
Test name
Test status
Simulation time 1132992692 ps
CPU time 4.01 seconds
Started Mar 12 02:35:05 PM PDT 24
Finished Mar 12 02:35:09 PM PDT 24
Peak memory 203520 kb
Host smart-fc1a9286-59f4-4a1e-a933-cbcb369ed253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840330664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3840330664
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.136026978
Short name T778
Test name
Test status
Simulation time 18425267031 ps
CPU time 160.77 seconds
Started Mar 12 02:35:00 PM PDT 24
Finished Mar 12 02:37:42 PM PDT 24
Peak memory 1543232 kb
Host smart-f2f19174-de88-4dbc-83a0-7346c041515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136026978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.136026978
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3132799493
Short name T1070
Test name
Test status
Simulation time 9619115138 ps
CPU time 85.95 seconds
Started Mar 12 02:35:15 PM PDT 24
Finished Mar 12 02:36:41 PM PDT 24
Peak memory 333156 kb
Host smart-31cf52fb-6067-44de-92a9-249c652448f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132799493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3132799493
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2089579974
Short name T1201
Test name
Test status
Simulation time 77025641 ps
CPU time 0.65 seconds
Started Mar 12 02:35:01 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 203228 kb
Host smart-21d27fd2-54ff-4165-b99c-046dcb207465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089579974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2089579974
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3977919234
Short name T868
Test name
Test status
Simulation time 1411158562 ps
CPU time 70.31 seconds
Started Mar 12 02:35:13 PM PDT 24
Finished Mar 12 02:36:24 PM PDT 24
Peak memory 203528 kb
Host smart-cd28d890-9ea8-4713-9ca9-c3ad0ba0039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977919234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3977919234
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2616585073
Short name T965
Test name
Test status
Simulation time 1689198993 ps
CPU time 42.47 seconds
Started Mar 12 02:34:58 PM PDT 24
Finished Mar 12 02:35:40 PM PDT 24
Peak memory 251772 kb
Host smart-f780f781-1bba-4256-9a10-0d83be3c16d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616585073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2616585073
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2584029750
Short name T151
Test name
Test status
Simulation time 30861494321 ps
CPU time 948.33 seconds
Started Mar 12 02:35:13 PM PDT 24
Finished Mar 12 02:51:01 PM PDT 24
Peak memory 955452 kb
Host smart-27c1e030-488e-49a2-a5d2-61bc965f7b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584029750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2584029750
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2093757391
Short name T1080
Test name
Test status
Simulation time 586954195 ps
CPU time 25.43 seconds
Started Mar 12 02:35:09 PM PDT 24
Finished Mar 12 02:35:35 PM PDT 24
Peak memory 211720 kb
Host smart-422de5f6-815e-4b40-96d5-92d56b48cdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093757391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2093757391
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.498577355
Short name T1019
Test name
Test status
Simulation time 5150493181 ps
CPU time 5.45 seconds
Started Mar 12 02:35:16 PM PDT 24
Finished Mar 12 02:35:22 PM PDT 24
Peak memory 205668 kb
Host smart-176e45fb-d95d-48b0-a149-f2dbc5243ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498577355 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.498577355
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1765417073
Short name T1133
Test name
Test status
Simulation time 10053197393 ps
CPU time 25.81 seconds
Started Mar 12 02:35:15 PM PDT 24
Finished Mar 12 02:35:41 PM PDT 24
Peak memory 367940 kb
Host smart-c1407002-2539-4893-bff7-7e093bd278e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765417073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1765417073
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2104221613
Short name T254
Test name
Test status
Simulation time 10166952955 ps
CPU time 13.04 seconds
Started Mar 12 02:35:15 PM PDT 24
Finished Mar 12 02:35:28 PM PDT 24
Peak memory 303344 kb
Host smart-218209b7-957d-4d59-aad4-916d9ae63b6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104221613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2104221613
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.765185608
Short name T1127
Test name
Test status
Simulation time 12174796596 ps
CPU time 12.67 seconds
Started Mar 12 02:35:11 PM PDT 24
Finished Mar 12 02:35:24 PM PDT 24
Peak memory 374048 kb
Host smart-4e89d0b5-9957-4b63-8567-aa679430af40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765185608 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.765185608
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.1001710570
Short name T1042
Test name
Test status
Simulation time 1441828267 ps
CPU time 5.06 seconds
Started Mar 12 02:35:15 PM PDT 24
Finished Mar 12 02:35:21 PM PDT 24
Peak memory 207844 kb
Host smart-195ec8f0-1d8b-4e4e-90a3-f92a424c992e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001710570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.1001710570
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1574656815
Short name T948
Test name
Test status
Simulation time 1896523983 ps
CPU time 13.68 seconds
Started Mar 12 02:35:12 PM PDT 24
Finished Mar 12 02:35:26 PM PDT 24
Peak memory 203500 kb
Host smart-50e3fd6d-735a-485e-94f0-e70153c95f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574656815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1574656815
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1303822462
Short name T248
Test name
Test status
Simulation time 13288714376 ps
CPU time 5.27 seconds
Started Mar 12 02:35:10 PM PDT 24
Finished Mar 12 02:35:16 PM PDT 24
Peak memory 203692 kb
Host smart-71e148d8-a1ee-4ca7-a987-4e50367e2673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303822462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1303822462
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1036351893
Short name T572
Test name
Test status
Simulation time 3764254608 ps
CPU time 8.6 seconds
Started Mar 12 02:35:12 PM PDT 24
Finished Mar 12 02:35:20 PM PDT 24
Peak memory 216184 kb
Host smart-fe801be7-1a84-4870-854f-af15302cce22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036351893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1036351893
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.611493706
Short name T995
Test name
Test status
Simulation time 5516266687 ps
CPU time 6.62 seconds
Started Mar 12 02:35:16 PM PDT 24
Finished Mar 12 02:35:23 PM PDT 24
Peak memory 203708 kb
Host smart-5e3d9980-0288-4ed7-b2c8-541da5f66fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611493706 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_unexp_stop.611493706
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3882826526
Short name T656
Test name
Test status
Simulation time 85972106 ps
CPU time 0.61 seconds
Started Mar 12 02:35:34 PM PDT 24
Finished Mar 12 02:35:35 PM PDT 24
Peak memory 202324 kb
Host smart-a03392fb-d8ae-44d3-95f9-29755d3442d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882826526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3882826526
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3970225482
Short name T519
Test name
Test status
Simulation time 45968918 ps
CPU time 1.86 seconds
Started Mar 12 02:35:29 PM PDT 24
Finished Mar 12 02:35:32 PM PDT 24
Peak memory 211776 kb
Host smart-eb7fdd12-bff6-4cc2-b23d-b436a1730750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970225482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3970225482
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2087023718
Short name T915
Test name
Test status
Simulation time 3620780900 ps
CPU time 7.8 seconds
Started Mar 12 02:35:22 PM PDT 24
Finished Mar 12 02:35:30 PM PDT 24
Peak memory 298160 kb
Host smart-9b35fef9-1233-4bfb-a465-03e804fd353b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087023718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2087023718
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3490766134
Short name T277
Test name
Test status
Simulation time 15832780984 ps
CPU time 53.53 seconds
Started Mar 12 02:35:29 PM PDT 24
Finished Mar 12 02:36:24 PM PDT 24
Peak memory 638216 kb
Host smart-703d20b3-929c-4029-9c04-c181d1e0f1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490766134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3490766134
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1980463783
Short name T1045
Test name
Test status
Simulation time 2953321495 ps
CPU time 108.35 seconds
Started Mar 12 02:35:22 PM PDT 24
Finished Mar 12 02:37:11 PM PDT 24
Peak memory 924996 kb
Host smart-8b8e71aa-059d-4c80-a01e-adb1c8c38689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980463783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1980463783
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2705937391
Short name T1053
Test name
Test status
Simulation time 96983416 ps
CPU time 0.91 seconds
Started Mar 12 02:35:22 PM PDT 24
Finished Mar 12 02:35:23 PM PDT 24
Peak memory 203232 kb
Host smart-ca6493fe-fc3c-4f46-a09c-be40fd8bc8cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705937391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2705937391
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.868982349
Short name T700
Test name
Test status
Simulation time 213323107 ps
CPU time 5.28 seconds
Started Mar 12 02:35:30 PM PDT 24
Finished Mar 12 02:35:36 PM PDT 24
Peak memory 244392 kb
Host smart-7d7752d9-e52b-4632-987b-bbcccb4e8a3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868982349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
868982349
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3610754665
Short name T950
Test name
Test status
Simulation time 25767754544 ps
CPU time 426.64 seconds
Started Mar 12 02:35:22 PM PDT 24
Finished Mar 12 02:42:29 PM PDT 24
Peak memory 1482356 kb
Host smart-a263cce9-1888-472f-bbc8-37290b5f2501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610754665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3610754665
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.677073397
Short name T593
Test name
Test status
Simulation time 8897505078 ps
CPU time 94.1 seconds
Started Mar 12 02:35:34 PM PDT 24
Finished Mar 12 02:37:09 PM PDT 24
Peak memory 217812 kb
Host smart-1495b09b-54e0-4c48-96d9-122ef72a1c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677073397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.677073397
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.772216408
Short name T1026
Test name
Test status
Simulation time 18230001 ps
CPU time 0.65 seconds
Started Mar 12 02:35:23 PM PDT 24
Finished Mar 12 02:35:24 PM PDT 24
Peak memory 202540 kb
Host smart-f2c8250a-5e8d-40a2-805f-6c66f3c8cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772216408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.772216408
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2562647106
Short name T314
Test name
Test status
Simulation time 862127777 ps
CPU time 6.02 seconds
Started Mar 12 02:35:29 PM PDT 24
Finished Mar 12 02:35:36 PM PDT 24
Peak memory 219640 kb
Host smart-5d1b79b5-5e73-4e6a-8f47-4bc89e0894f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562647106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2562647106
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1701308967
Short name T891
Test name
Test status
Simulation time 8518826174 ps
CPU time 77.41 seconds
Started Mar 12 02:35:15 PM PDT 24
Finished Mar 12 02:36:32 PM PDT 24
Peak memory 349432 kb
Host smart-2a772cf9-7c94-407e-a4e3-de047dec9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701308967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1701308967
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3428783021
Short name T1222
Test name
Test status
Simulation time 911957925 ps
CPU time 14.43 seconds
Started Mar 12 02:35:28 PM PDT 24
Finished Mar 12 02:35:45 PM PDT 24
Peak memory 213968 kb
Host smart-3aa1c7fb-f7d2-48c5-903d-75b82479e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428783021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3428783021
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1296993464
Short name T50
Test name
Test status
Simulation time 1244664635 ps
CPU time 3 seconds
Started Mar 12 02:35:34 PM PDT 24
Finished Mar 12 02:35:38 PM PDT 24
Peak memory 203548 kb
Host smart-32e4043b-d822-424b-a261-1ff1819a390b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296993464 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1296993464
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2794764967
Short name T222
Test name
Test status
Simulation time 10367495977 ps
CPU time 26.39 seconds
Started Mar 12 02:35:29 PM PDT 24
Finished Mar 12 02:35:57 PM PDT 24
Peak memory 364880 kb
Host smart-3ff69855-d217-4386-a611-f51f95256d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794764967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2794764967
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3136904875
Short name T370
Test name
Test status
Simulation time 10031616697 ps
CPU time 77.38 seconds
Started Mar 12 02:35:27 PM PDT 24
Finished Mar 12 02:36:45 PM PDT 24
Peak memory 608232 kb
Host smart-ed0123ee-d72a-4d11-94cb-2ef9587f49b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136904875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3136904875
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3622407091
Short name T752
Test name
Test status
Simulation time 1891305964 ps
CPU time 2.52 seconds
Started Mar 12 02:35:37 PM PDT 24
Finished Mar 12 02:35:41 PM PDT 24
Peak memory 203572 kb
Host smart-7b659d2f-dc7a-433c-b8ec-71af1b7d066c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622407091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3622407091
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1284161488
Short name T667
Test name
Test status
Simulation time 5164723967 ps
CPU time 5.18 seconds
Started Mar 12 02:35:28 PM PDT 24
Finished Mar 12 02:35:35 PM PDT 24
Peak memory 203668 kb
Host smart-d0e2b19f-6930-47f9-a37f-191272796309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284161488 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1284161488
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.4035777284
Short name T762
Test name
Test status
Simulation time 4074733683 ps
CPU time 6.43 seconds
Started Mar 12 02:35:27 PM PDT 24
Finished Mar 12 02:35:34 PM PDT 24
Peak memory 203552 kb
Host smart-804284be-4a3e-4c9a-acc1-e524779cf782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035777284 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.4035777284
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.400702314
Short name T595
Test name
Test status
Simulation time 818483698 ps
CPU time 4.58 seconds
Started Mar 12 02:35:35 PM PDT 24
Finished Mar 12 02:35:40 PM PDT 24
Peak memory 203572 kb
Host smart-7461a24c-085b-42ae-8a80-f4ca6fc79de9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400702314 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_perf.400702314
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.1447103634
Short name T327
Test name
Test status
Simulation time 11399308216 ps
CPU time 51.19 seconds
Started Mar 12 02:35:35 PM PDT 24
Finished Mar 12 02:36:26 PM PDT 24
Peak memory 332220 kb
Host smart-63361303-0595-4763-857d-4d85c66bea5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447103634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.1447103634
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.413741300
Short name T834
Test name
Test status
Simulation time 29683723430 ps
CPU time 72.24 seconds
Started Mar 12 02:35:31 PM PDT 24
Finished Mar 12 02:36:44 PM PDT 24
Peak memory 1269056 kb
Host smart-63b3c380-6888-4eea-8bf9-538ebefccd06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413741300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.413741300
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1240428844
Short name T1003
Test name
Test status
Simulation time 28441138269 ps
CPU time 528.42 seconds
Started Mar 12 02:35:28 PM PDT 24
Finished Mar 12 02:44:18 PM PDT 24
Peak memory 3170524 kb
Host smart-3cd66a22-b22a-4257-89ad-a1801439f7e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240428844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1240428844
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2667506200
Short name T394
Test name
Test status
Simulation time 3066001401 ps
CPU time 7.51 seconds
Started Mar 12 02:35:31 PM PDT 24
Finished Mar 12 02:35:38 PM PDT 24
Peak memory 203692 kb
Host smart-3838757a-58f5-4fd2-92f9-f68c10031b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667506200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2667506200
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.1586499257
Short name T773
Test name
Test status
Simulation time 4469901483 ps
CPU time 4.61 seconds
Started Mar 12 02:35:31 PM PDT 24
Finished Mar 12 02:35:36 PM PDT 24
Peak memory 203696 kb
Host smart-351d1468-f113-484b-b507-8c49fdb695f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586499257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.1586499257
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.675486339
Short name T1099
Test name
Test status
Simulation time 19654860 ps
CPU time 0.61 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:50 PM PDT 24
Peak memory 202352 kb
Host smart-c238c9b9-248c-4fb5-881f-ea7b77d38c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675486339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.675486339
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2626921382
Short name T797
Test name
Test status
Simulation time 35301781 ps
CPU time 1.54 seconds
Started Mar 12 02:35:47 PM PDT 24
Finished Mar 12 02:35:49 PM PDT 24
Peak memory 211740 kb
Host smart-1f8feebf-2dc4-4c1b-ab35-cf29f4df4ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626921382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2626921382
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3555755991
Short name T229
Test name
Test status
Simulation time 510802954 ps
CPU time 9 seconds
Started Mar 12 02:35:44 PM PDT 24
Finished Mar 12 02:35:53 PM PDT 24
Peak memory 318504 kb
Host smart-c0599b40-642d-49f2-b79e-1be74d7d0f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555755991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3555755991
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.315450091
Short name T1213
Test name
Test status
Simulation time 11682093052 ps
CPU time 223.34 seconds
Started Mar 12 02:35:47 PM PDT 24
Finished Mar 12 02:39:31 PM PDT 24
Peak memory 851228 kb
Host smart-dfffa237-0190-4b04-93d5-5e32be8d7df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315450091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.315450091
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1260708091
Short name T1180
Test name
Test status
Simulation time 2523157923 ps
CPU time 84.81 seconds
Started Mar 12 02:35:36 PM PDT 24
Finished Mar 12 02:37:01 PM PDT 24
Peak memory 812604 kb
Host smart-078d77aa-9019-4f79-83f6-fb0c636b9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260708091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1260708091
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.245797119
Short name T854
Test name
Test status
Simulation time 98563357 ps
CPU time 0.9 seconds
Started Mar 12 02:35:43 PM PDT 24
Finished Mar 12 02:35:44 PM PDT 24
Peak memory 203276 kb
Host smart-fcda5e70-3983-4c70-8ec7-a533bdbfbe66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245797119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fm
t.245797119
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2509792541
Short name T528
Test name
Test status
Simulation time 795794420 ps
CPU time 4.44 seconds
Started Mar 12 02:35:42 PM PDT 24
Finished Mar 12 02:35:47 PM PDT 24
Peak memory 203520 kb
Host smart-91b41a05-a56c-4674-967d-ad2d428ee5a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509792541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2509792541
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2311095002
Short name T1138
Test name
Test status
Simulation time 3684181552 ps
CPU time 210.99 seconds
Started Mar 12 02:35:37 PM PDT 24
Finished Mar 12 02:39:10 PM PDT 24
Peak memory 919336 kb
Host smart-176f0621-f9da-4832-b807-7a4271ff88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311095002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2311095002
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.591170901
Short name T1163
Test name
Test status
Simulation time 10346984751 ps
CPU time 116.91 seconds
Started Mar 12 02:35:49 PM PDT 24
Finished Mar 12 02:37:47 PM PDT 24
Peak memory 369464 kb
Host smart-1b8d89f4-1b3c-47de-a2e0-2db6001abcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591170901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.591170901
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1495320470
Short name T369
Test name
Test status
Simulation time 15479319 ps
CPU time 0.63 seconds
Started Mar 12 02:35:36 PM PDT 24
Finished Mar 12 02:35:37 PM PDT 24
Peak memory 202588 kb
Host smart-3dd76b57-ba61-4964-9a7b-cf438257c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495320470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1495320470
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.150825462
Short name T174
Test name
Test status
Simulation time 27406083259 ps
CPU time 292.69 seconds
Started Mar 12 02:35:43 PM PDT 24
Finished Mar 12 02:40:36 PM PDT 24
Peak memory 211852 kb
Host smart-e7ee0554-6551-4d97-99ee-008ae5d6629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150825462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.150825462
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2136589051
Short name T499
Test name
Test status
Simulation time 10314928026 ps
CPU time 65.58 seconds
Started Mar 12 02:35:36 PM PDT 24
Finished Mar 12 02:36:42 PM PDT 24
Peak memory 287640 kb
Host smart-5b477fcc-b42f-49b5-b6e2-bb858b03dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136589051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2136589051
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.68181128
Short name T72
Test name
Test status
Simulation time 97340362176 ps
CPU time 3131.19 seconds
Started Mar 12 02:35:46 PM PDT 24
Finished Mar 12 03:27:59 PM PDT 24
Peak memory 2573380 kb
Host smart-1866c365-4b68-467d-b8d0-09ff1538e4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68181128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.68181128
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3893609262
Short name T573
Test name
Test status
Simulation time 641902503 ps
CPU time 10 seconds
Started Mar 12 02:35:49 PM PDT 24
Finished Mar 12 02:36:00 PM PDT 24
Peak memory 214964 kb
Host smart-382c095b-96de-478f-9d69-957c4892fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893609262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3893609262
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3816399292
Short name T906
Test name
Test status
Simulation time 4208025606 ps
CPU time 4.34 seconds
Started Mar 12 02:35:53 PM PDT 24
Finished Mar 12 02:35:58 PM PDT 24
Peak memory 203644 kb
Host smart-2836fbd3-0a2c-4427-a317-b43a3c30758b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816399292 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3816399292
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.352588906
Short name T1059
Test name
Test status
Simulation time 10032242564 ps
CPU time 98.18 seconds
Started Mar 12 02:35:53 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 673336 kb
Host smart-97cf11ff-195f-4360-8469-299d3d55a63d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352588906 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.352588906
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3019709370
Short name T618
Test name
Test status
Simulation time 1376844952 ps
CPU time 6.47 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:56 PM PDT 24
Peak memory 212568 kb
Host smart-52f25ebc-0689-490c-aecb-68e071e429c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019709370 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3019709370
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.671395800
Short name T345
Test name
Test status
Simulation time 3187691385 ps
CPU time 7.57 seconds
Started Mar 12 02:35:50 PM PDT 24
Finished Mar 12 02:35:58 PM PDT 24
Peak memory 203548 kb
Host smart-bdb27acb-6c85-4a6e-95e4-bb7e4521dd1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671395800 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.671395800
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.2289012966
Short name T844
Test name
Test status
Simulation time 831062344 ps
CPU time 4.3 seconds
Started Mar 12 02:35:53 PM PDT 24
Finished Mar 12 02:35:58 PM PDT 24
Peak memory 203620 kb
Host smart-8508a645-ddf0-4bd9-972e-c28f547463ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289012966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.2289012966
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.1860414132
Short name T361
Test name
Test status
Simulation time 105796635234 ps
CPU time 52.82 seconds
Started Mar 12 02:35:57 PM PDT 24
Finished Mar 12 02:36:50 PM PDT 24
Peak memory 235352 kb
Host smart-3064449b-4faa-42bf-8e90-664cd79e14f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860414132 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.1860414132
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1344084651
Short name T807
Test name
Test status
Simulation time 28993646499 ps
CPU time 355.58 seconds
Started Mar 12 02:35:47 PM PDT 24
Finished Mar 12 02:41:43 PM PDT 24
Peak memory 2576448 kb
Host smart-6a1c9706-6ad2-4bc9-b2a4-a8babf658eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344084651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1344084651
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1056683606
Short name T1179
Test name
Test status
Simulation time 1555907695 ps
CPU time 6.7 seconds
Started Mar 12 02:35:42 PM PDT 24
Finished Mar 12 02:35:49 PM PDT 24
Peak memory 203552 kb
Host smart-ed7f8a5f-a861-4439-937e-b18ca4223df2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056683606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1056683606
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.120219120
Short name T1082
Test name
Test status
Simulation time 5946597725 ps
CPU time 7.7 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:56 PM PDT 24
Peak memory 211832 kb
Host smart-ef54ac95-9354-4a4a-a314-d0e380095bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120219120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_unexp_stop.120219120
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.834377506
Short name T1228
Test name
Test status
Simulation time 28362528 ps
CPU time 0.64 seconds
Started Mar 12 02:36:02 PM PDT 24
Finished Mar 12 02:36:03 PM PDT 24
Peak memory 203332 kb
Host smart-e23185ba-52bb-4efb-a510-5f74971c88e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834377506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.834377506
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.4262963183
Short name T429
Test name
Test status
Simulation time 133820525 ps
CPU time 1.39 seconds
Started Mar 12 02:35:56 PM PDT 24
Finished Mar 12 02:35:59 PM PDT 24
Peak memory 211816 kb
Host smart-69cd556e-ad32-40c2-83c2-3efcf5f82f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262963183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.4262963183
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.4179637179
Short name T973
Test name
Test status
Simulation time 1961513899 ps
CPU time 10.73 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:59 PM PDT 24
Peak memory 315820 kb
Host smart-14a43562-06b9-4f1c-b5b4-54bfd63a8aef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179637179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.4179637179
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.391589631
Short name T436
Test name
Test status
Simulation time 6026837424 ps
CPU time 39.81 seconds
Started Mar 12 02:36:00 PM PDT 24
Finished Mar 12 02:36:40 PM PDT 24
Peak memory 505864 kb
Host smart-5a8e7f87-316a-4dcb-9ff6-7b36bbacf1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391589631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.391589631
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2729683353
Short name T252
Test name
Test status
Simulation time 28484062641 ps
CPU time 68.95 seconds
Started Mar 12 02:35:57 PM PDT 24
Finished Mar 12 02:37:06 PM PDT 24
Peak memory 700380 kb
Host smart-977c3ccb-6987-40cd-b7a2-7ec85009415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729683353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2729683353
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.4039918298
Short name T748
Test name
Test status
Simulation time 833862631 ps
CPU time 0.85 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:35:49 PM PDT 24
Peak memory 203244 kb
Host smart-c78bda88-a5fb-405e-8957-9bc0cc89ed9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039918298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.4039918298
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2143713980
Short name T496
Test name
Test status
Simulation time 16385714356 ps
CPU time 285.31 seconds
Started Mar 12 02:35:49 PM PDT 24
Finished Mar 12 02:40:35 PM PDT 24
Peak memory 1141648 kb
Host smart-e01c6034-038f-4114-b880-c5d443b7cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143713980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2143713980
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2218443266
Short name T1203
Test name
Test status
Simulation time 1422970218 ps
CPU time 34.81 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:36:36 PM PDT 24
Peak memory 263284 kb
Host smart-94a936ce-904c-488a-ac5c-4f0c2f7fbcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218443266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2218443266
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3649930460
Short name T5
Test name
Test status
Simulation time 17232519 ps
CPU time 0.66 seconds
Started Mar 12 02:35:50 PM PDT 24
Finished Mar 12 02:35:51 PM PDT 24
Peak memory 202480 kb
Host smart-43cab169-567e-47c4-90fa-a50a2e184bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649930460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3649930460
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.816648113
Short name T648
Test name
Test status
Simulation time 71654566859 ps
CPU time 318.06 seconds
Started Mar 12 02:35:57 PM PDT 24
Finished Mar 12 02:41:16 PM PDT 24
Peak memory 211760 kb
Host smart-913f1793-6ded-42e9-9795-8856b094cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816648113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.816648113
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2971427817
Short name T738
Test name
Test status
Simulation time 7263944472 ps
CPU time 124.68 seconds
Started Mar 12 02:35:48 PM PDT 24
Finished Mar 12 02:37:54 PM PDT 24
Peak memory 260496 kb
Host smart-381d8dce-7adc-472b-817f-1f6cb3f1d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971427817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2971427817
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3972714739
Short name T216
Test name
Test status
Simulation time 108977540789 ps
CPU time 2433.29 seconds
Started Mar 12 02:35:56 PM PDT 24
Finished Mar 12 03:16:30 PM PDT 24
Peak memory 1472540 kb
Host smart-609c5bb4-9359-48cd-bdfd-23430f1ecf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972714739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3972714739
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3235890725
Short name T680
Test name
Test status
Simulation time 1037287940 ps
CPU time 15.66 seconds
Started Mar 12 02:35:58 PM PDT 24
Finished Mar 12 02:36:14 PM PDT 24
Peak memory 217700 kb
Host smart-88eb98c2-becd-478f-b2e3-fc92e433de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235890725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3235890725
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3313644849
Short name T437
Test name
Test status
Simulation time 2391050270 ps
CPU time 5.54 seconds
Started Mar 12 02:36:02 PM PDT 24
Finished Mar 12 02:36:08 PM PDT 24
Peak memory 203636 kb
Host smart-3fecad8d-3a24-471d-8ebf-b19285484470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313644849 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3313644849
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3502852633
Short name T180
Test name
Test status
Simulation time 10119392830 ps
CPU time 31.12 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:36:32 PM PDT 24
Peak memory 386672 kb
Host smart-bcda4f7d-2164-434a-8b87-f95dd412a820
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502852633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3502852633
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3756901009
Short name T809
Test name
Test status
Simulation time 10201859390 ps
CPU time 12.92 seconds
Started Mar 12 02:35:59 PM PDT 24
Finished Mar 12 02:36:12 PM PDT 24
Peak memory 308616 kb
Host smart-b311b26f-3fde-4b56-95fa-25f442e02792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756901009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3756901009
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1049154934
Short name T560
Test name
Test status
Simulation time 677737048 ps
CPU time 3.02 seconds
Started Mar 12 02:36:00 PM PDT 24
Finished Mar 12 02:36:04 PM PDT 24
Peak memory 203528 kb
Host smart-e2974468-375a-4c6a-a84e-4d7500ef9b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049154934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1049154934
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2118433397
Short name T707
Test name
Test status
Simulation time 3619931990 ps
CPU time 7.79 seconds
Started Mar 12 02:35:54 PM PDT 24
Finished Mar 12 02:36:02 PM PDT 24
Peak memory 203572 kb
Host smart-937c8af8-a88f-49f1-a997-86ce0cb457bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118433397 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2118433397
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1224561899
Short name T396
Test name
Test status
Simulation time 902757829 ps
CPU time 2.99 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:36:04 PM PDT 24
Peak memory 203536 kb
Host smart-ac2f0ce0-d722-4ed2-b5f9-7836eee2ff89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224561899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1224561899
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2099986533
Short name T53
Test name
Test status
Simulation time 59534783194 ps
CPU time 217.64 seconds
Started Mar 12 02:35:55 PM PDT 24
Finished Mar 12 02:39:33 PM PDT 24
Peak memory 2526400 kb
Host smart-949b0cbb-fa8c-44ba-abed-361f1cc7b4f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099986533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2099986533
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2337363592
Short name T263
Test name
Test status
Simulation time 8912517272 ps
CPU time 797.24 seconds
Started Mar 12 02:35:55 PM PDT 24
Finished Mar 12 02:49:12 PM PDT 24
Peak memory 2231696 kb
Host smart-ca8265a9-20eb-48b4-a888-4acf6721f945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337363592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2337363592
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.1703526041
Short name T1109
Test name
Test status
Simulation time 2616105219 ps
CPU time 8.14 seconds
Started Mar 12 02:35:57 PM PDT 24
Finished Mar 12 02:36:06 PM PDT 24
Peak memory 203612 kb
Host smart-dc7fc0e9-b291-4a83-bbf7-80d09840d843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703526041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.1703526041
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.626305345
Short name T662
Test name
Test status
Simulation time 46697169 ps
CPU time 0.61 seconds
Started Mar 12 02:36:11 PM PDT 24
Finished Mar 12 02:36:13 PM PDT 24
Peak memory 202392 kb
Host smart-a8d3ae49-b577-40bc-b3ad-d65e80f5c156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626305345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.626305345
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2338310994
Short name T779
Test name
Test status
Simulation time 986616882 ps
CPU time 8.16 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:36:10 PM PDT 24
Peak memory 277684 kb
Host smart-93fb573f-f2f7-4810-8a3c-6c65f650dca0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338310994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2338310994
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.830684348
Short name T415
Test name
Test status
Simulation time 7399554540 ps
CPU time 116.12 seconds
Started Mar 12 02:35:59 PM PDT 24
Finished Mar 12 02:37:56 PM PDT 24
Peak memory 569356 kb
Host smart-a3f6b6c2-f56f-4976-9b39-b0ab53d30793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830684348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.830684348
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3600866917
Short name T376
Test name
Test status
Simulation time 19025593922 ps
CPU time 48.11 seconds
Started Mar 12 02:36:00 PM PDT 24
Finished Mar 12 02:36:48 PM PDT 24
Peak memory 631188 kb
Host smart-3266211e-2fb4-441c-ad3d-e9ddf5bb9a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600866917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3600866917
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.57240663
Short name T840
Test name
Test status
Simulation time 88876673 ps
CPU time 0.72 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:36:02 PM PDT 24
Peak memory 202596 kb
Host smart-19bd296b-ca70-4597-812e-be3c599ffa9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57240663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt
.57240663
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1936708168
Short name T1039
Test name
Test status
Simulation time 276817641 ps
CPU time 3.12 seconds
Started Mar 12 02:36:02 PM PDT 24
Finished Mar 12 02:36:06 PM PDT 24
Peak memory 203472 kb
Host smart-5025f34c-127f-458a-aa61-59155030cc48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936708168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1936708168
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4049200209
Short name T556
Test name
Test status
Simulation time 5914991377 ps
CPU time 96.32 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:37:38 PM PDT 24
Peak memory 1027920 kb
Host smart-f24eafdc-f1fc-42f3-b841-119094e76d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049200209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4049200209
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1284060554
Short name T377
Test name
Test status
Simulation time 49482168702 ps
CPU time 88.58 seconds
Started Mar 12 02:36:11 PM PDT 24
Finished Mar 12 02:37:41 PM PDT 24
Peak memory 349164 kb
Host smart-28d7426e-27c1-47d9-9120-e318b0bbc9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284060554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1284060554
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1358242881
Short name T706
Test name
Test status
Simulation time 37895079 ps
CPU time 0.68 seconds
Started Mar 12 02:36:02 PM PDT 24
Finished Mar 12 02:36:03 PM PDT 24
Peak memory 202596 kb
Host smart-33070384-c3a5-4268-9183-cde7898abaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358242881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1358242881
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.4207217561
Short name T824
Test name
Test status
Simulation time 26160303391 ps
CPU time 123.27 seconds
Started Mar 12 02:36:01 PM PDT 24
Finished Mar 12 02:38:05 PM PDT 24
Peak memory 215908 kb
Host smart-0d8a445a-c75d-4aa3-af64-bd05e622fe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207217561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.4207217561
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2968670815
Short name T241
Test name
Test status
Simulation time 11665373455 ps
CPU time 110.11 seconds
Started Mar 12 02:36:02 PM PDT 24
Finished Mar 12 02:37:52 PM PDT 24
Peak memory 348880 kb
Host smart-0bea18ba-43b9-4d3d-a25e-d4265e4986db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968670815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2968670815
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1345491537
Short name T171
Test name
Test status
Simulation time 44805368840 ps
CPU time 3080.24 seconds
Started Mar 12 02:36:08 PM PDT 24
Finished Mar 12 03:27:30 PM PDT 24
Peak memory 2622020 kb
Host smart-f44170b4-39b7-4710-8061-3dcea0aff579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345491537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1345491537
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.705619114
Short name T1087
Test name
Test status
Simulation time 1514283651 ps
CPU time 32.69 seconds
Started Mar 12 02:36:07 PM PDT 24
Finished Mar 12 02:36:40 PM PDT 24
Peak memory 211688 kb
Host smart-75c2c681-0606-4365-90ef-5bbaafbd12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705619114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.705619114
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2126545184
Short name T441
Test name
Test status
Simulation time 468728636 ps
CPU time 2.45 seconds
Started Mar 12 02:36:11 PM PDT 24
Finished Mar 12 02:36:15 PM PDT 24
Peak memory 203592 kb
Host smart-27540d64-ec68-4374-87bc-47268d27a922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126545184 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2126545184
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.104535094
Short name T913
Test name
Test status
Simulation time 10553550984 ps
CPU time 3.41 seconds
Started Mar 12 02:36:12 PM PDT 24
Finished Mar 12 02:36:16 PM PDT 24
Peak memory 223888 kb
Host smart-154ecae2-1335-4163-ad26-0cdec48ce144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104535094 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.104535094
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4236011625
Short name T249
Test name
Test status
Simulation time 10041754212 ps
CPU time 29.72 seconds
Started Mar 12 02:36:11 PM PDT 24
Finished Mar 12 02:36:42 PM PDT 24
Peak memory 414972 kb
Host smart-06a2fb7f-85af-4757-a300-a221611ee71e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236011625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4236011625
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2255952706
Short name T871
Test name
Test status
Simulation time 1243016826 ps
CPU time 5.22 seconds
Started Mar 12 02:36:10 PM PDT 24
Finished Mar 12 02:36:15 PM PDT 24
Peak memory 204484 kb
Host smart-fc883b05-e1f3-43a4-bc1a-36538a5ccbf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255952706 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2255952706
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3727424289
Short name T1126
Test name
Test status
Simulation time 19287306690 ps
CPU time 296.51 seconds
Started Mar 12 02:36:07 PM PDT 24
Finished Mar 12 02:41:04 PM PDT 24
Peak memory 2956840 kb
Host smart-2a7fefe8-8ef0-48c1-bc6b-302514c48095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727424289 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3727424289
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.2681328111
Short name T1200
Test name
Test status
Simulation time 809769120 ps
CPU time 4.97 seconds
Started Mar 12 02:36:12 PM PDT 24
Finished Mar 12 02:36:18 PM PDT 24
Peak memory 207748 kb
Host smart-911014e6-e2d5-47bd-b383-6beabbdb3c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681328111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.2681328111
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3463121048
Short name T507
Test name
Test status
Simulation time 45724966647 ps
CPU time 859.99 seconds
Started Mar 12 02:36:06 PM PDT 24
Finished Mar 12 02:50:26 PM PDT 24
Peak memory 6508244 kb
Host smart-969221b2-0abe-4dfb-91d1-3da19403a1a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463121048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3463121048
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2486220612
Short name T1219
Test name
Test status
Simulation time 20250185792 ps
CPU time 248.8 seconds
Started Mar 12 02:36:06 PM PDT 24
Finished Mar 12 02:40:15 PM PDT 24
Peak memory 2188292 kb
Host smart-5b53265b-0721-4363-98a4-f51cd335bf89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486220612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2486220612
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2829144524
Short name T416
Test name
Test status
Simulation time 1961922095 ps
CPU time 7.68 seconds
Started Mar 12 02:36:06 PM PDT 24
Finished Mar 12 02:36:14 PM PDT 24
Peak memory 214948 kb
Host smart-86b08c6c-0ea2-4683-884b-952280b68770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829144524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2829144524
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.3401120450
Short name T971
Test name
Test status
Simulation time 1849408042 ps
CPU time 4.97 seconds
Started Mar 12 02:36:09 PM PDT 24
Finished Mar 12 02:36:15 PM PDT 24
Peak memory 203644 kb
Host smart-efbb783b-b018-4dca-a503-95a4a82a07eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401120450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.3401120450
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.479365905
Short name T476
Test name
Test status
Simulation time 16585283 ps
CPU time 0.62 seconds
Started Mar 12 02:36:29 PM PDT 24
Finished Mar 12 02:36:30 PM PDT 24
Peak memory 203360 kb
Host smart-7759063a-2991-45e6-9ea5-706d874574da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479365905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.479365905
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.43300951
Short name T1258
Test name
Test status
Simulation time 104185991 ps
CPU time 1.37 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:36:20 PM PDT 24
Peak memory 211716 kb
Host smart-30419b5b-5de0-4c92-a347-d4a12da4a0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43300951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.43300951
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.111674970
Short name T1137
Test name
Test status
Simulation time 1364699115 ps
CPU time 17.92 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:36:36 PM PDT 24
Peak memory 272216 kb
Host smart-67b3ed1d-930f-4f2d-854c-24072ad46579
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111674970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.111674970
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3769965663
Short name T759
Test name
Test status
Simulation time 3383645837 ps
CPU time 200.1 seconds
Started Mar 12 02:36:19 PM PDT 24
Finished Mar 12 02:39:39 PM PDT 24
Peak memory 800108 kb
Host smart-c8249d27-c4b8-4dbb-ab0f-adedbd853484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769965663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3769965663
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3566104469
Short name T639
Test name
Test status
Simulation time 7762005762 ps
CPU time 55.46 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:37:13 PM PDT 24
Peak memory 668304 kb
Host smart-82bd3f2f-aa2a-4dab-9305-29c87f0588c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566104469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3566104469
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1543168766
Short name T903
Test name
Test status
Simulation time 73622767 ps
CPU time 0.88 seconds
Started Mar 12 02:36:17 PM PDT 24
Finished Mar 12 02:36:18 PM PDT 24
Peak memory 203224 kb
Host smart-4e08f2a7-5301-438f-b3cb-79773a9e8ebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543168766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1543168766
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.4149008373
Short name T789
Test name
Test status
Simulation time 765054070 ps
CPU time 4.73 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:36:22 PM PDT 24
Peak memory 237228 kb
Host smart-a274c2a8-4cb3-42f1-8d3e-5f8381b686e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149008373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.4149008373
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2248121842
Short name T843
Test name
Test status
Simulation time 32704300366 ps
CPU time 169.69 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:39:08 PM PDT 24
Peak memory 1500052 kb
Host smart-0343c168-3ec6-44a1-931f-958b70eb383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248121842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2248121842
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3599378646
Short name T1116
Test name
Test status
Simulation time 2912856719 ps
CPU time 68.95 seconds
Started Mar 12 02:36:23 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 346288 kb
Host smart-eeb24b56-6e0c-4096-9681-dc068fa3e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599378646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3599378646
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.322264140
Short name T872
Test name
Test status
Simulation time 15866814 ps
CPU time 0.65 seconds
Started Mar 12 02:36:16 PM PDT 24
Finished Mar 12 02:36:17 PM PDT 24
Peak memory 202460 kb
Host smart-0d191dc3-9e01-4056-9718-c0e99f30c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322264140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.322264140
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1342979634
Short name T731
Test name
Test status
Simulation time 29219344180 ps
CPU time 933.45 seconds
Started Mar 12 02:36:18 PM PDT 24
Finished Mar 12 02:51:51 PM PDT 24
Peak memory 636872 kb
Host smart-e23b992b-347a-490f-be64-bf4cbd7a5f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342979634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1342979634
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3567840733
Short name T448
Test name
Test status
Simulation time 5502161700 ps
CPU time 72.85 seconds
Started Mar 12 02:36:11 PM PDT 24
Finished Mar 12 02:37:25 PM PDT 24
Peak memory 245820 kb
Host smart-dc8e3e65-5a66-4285-8cc3-f5c18f0167e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567840733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3567840733
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.136391028
Short name T247
Test name
Test status
Simulation time 1100527119 ps
CPU time 10.11 seconds
Started Mar 12 02:36:17 PM PDT 24
Finished Mar 12 02:36:27 PM PDT 24
Peak memory 216660 kb
Host smart-5402cc2b-3a99-4f1d-bdc4-776085215c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136391028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.136391028
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1492664643
Short name T1158
Test name
Test status
Simulation time 8151452592 ps
CPU time 4.93 seconds
Started Mar 12 02:36:21 PM PDT 24
Finished Mar 12 02:36:26 PM PDT 24
Peak memory 203576 kb
Host smart-fb42c5a6-fb18-4344-a371-ae5f80c72b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492664643 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1492664643
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1947164398
Short name T979
Test name
Test status
Simulation time 10918517172 ps
CPU time 6.92 seconds
Started Mar 12 02:36:23 PM PDT 24
Finished Mar 12 02:36:30 PM PDT 24
Peak memory 260392 kb
Host smart-c3fa95d5-caf4-424a-9b3b-e90dcb31f329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947164398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1947164398
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3669985944
Short name T643
Test name
Test status
Simulation time 7061681385 ps
CPU time 5.16 seconds
Started Mar 12 02:36:23 PM PDT 24
Finished Mar 12 02:36:28 PM PDT 24
Peak memory 206436 kb
Host smart-ea2a780e-529f-4dfe-bb56-58b3c9e9f224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669985944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3669985944
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2909554452
Short name T1171
Test name
Test status
Simulation time 3520277124 ps
CPU time 7.49 seconds
Started Mar 12 02:36:21 PM PDT 24
Finished Mar 12 02:36:28 PM PDT 24
Peak memory 203620 kb
Host smart-53d4a1b1-351a-49af-82e3-0e5739ba5a5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909554452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2909554452
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.3200046831
Short name T444
Test name
Test status
Simulation time 931495174 ps
CPU time 5.29 seconds
Started Mar 12 02:36:20 PM PDT 24
Finished Mar 12 02:36:26 PM PDT 24
Peak memory 203636 kb
Host smart-f6be0340-f996-414b-bcc8-13c1e77c7eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200046831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.3200046831
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1422150104
Short name T541
Test name
Test status
Simulation time 1990497271 ps
CPU time 68.58 seconds
Started Mar 12 02:36:25 PM PDT 24
Finished Mar 12 02:37:33 PM PDT 24
Peak memory 203604 kb
Host smart-33b10489-cfe5-46af-82c2-e092f5eefac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422150104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1422150104
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3810996083
Short name T353
Test name
Test status
Simulation time 23693068356 ps
CPU time 14.06 seconds
Started Mar 12 02:36:17 PM PDT 24
Finished Mar 12 02:36:31 PM PDT 24
Peak memory 267940 kb
Host smart-4e1b7676-bc5f-4e96-aab0-8b9b9bcc33d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810996083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3810996083
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.4266372683
Short name T745
Test name
Test status
Simulation time 3124660353 ps
CPU time 6.65 seconds
Started Mar 12 02:36:23 PM PDT 24
Finished Mar 12 02:36:30 PM PDT 24
Peak memory 207776 kb
Host smart-ab2ed00e-718f-4fad-84b6-061f15d09c25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266372683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.4266372683
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2450761635
Short name T497
Test name
Test status
Simulation time 16560893 ps
CPU time 0.63 seconds
Started Mar 12 02:36:41 PM PDT 24
Finished Mar 12 02:36:41 PM PDT 24
Peak memory 202340 kb
Host smart-c3f6846d-269e-41a7-9807-cc3560c07f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450761635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2450761635
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3076427564
Short name T855
Test name
Test status
Simulation time 33653745 ps
CPU time 1.42 seconds
Started Mar 12 02:36:35 PM PDT 24
Finished Mar 12 02:36:36 PM PDT 24
Peak memory 211704 kb
Host smart-6c28d369-7622-4b07-aaeb-387d13b54424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076427564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3076427564
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1186389813
Short name T1052
Test name
Test status
Simulation time 1597804106 ps
CPU time 8.19 seconds
Started Mar 12 02:36:29 PM PDT 24
Finished Mar 12 02:36:37 PM PDT 24
Peak memory 305664 kb
Host smart-fb5c669c-a79a-4c80-8875-58f41da2b3dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186389813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1186389813
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3254906118
Short name T1081
Test name
Test status
Simulation time 9571385721 ps
CPU time 180.65 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:39:34 PM PDT 24
Peak memory 762612 kb
Host smart-7ba10737-9670-4bb7-827b-bee269ff0c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254906118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3254906118
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.813315139
Short name T329
Test name
Test status
Simulation time 3145863286 ps
CPU time 115.25 seconds
Started Mar 12 02:36:29 PM PDT 24
Finished Mar 12 02:38:25 PM PDT 24
Peak memory 940332 kb
Host smart-5d794fec-3775-4051-be0d-860a3e5035e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813315139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.813315139
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3671968798
Short name T765
Test name
Test status
Simulation time 121523628 ps
CPU time 0.87 seconds
Started Mar 12 02:36:29 PM PDT 24
Finished Mar 12 02:36:30 PM PDT 24
Peak memory 203268 kb
Host smart-6c5cbeec-bf16-481e-b446-43e316fcc125
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671968798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3671968798
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3349105224
Short name T983
Test name
Test status
Simulation time 304164674 ps
CPU time 4.66 seconds
Started Mar 12 02:36:35 PM PDT 24
Finished Mar 12 02:36:40 PM PDT 24
Peak memory 231172 kb
Host smart-fef655f4-fa6f-47cc-9d92-305b24e8d0ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349105224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3349105224
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1648257267
Short name T145
Test name
Test status
Simulation time 3537476056 ps
CPU time 83.13 seconds
Started Mar 12 02:36:30 PM PDT 24
Finished Mar 12 02:37:53 PM PDT 24
Peak memory 1056420 kb
Host smart-a9c9d20a-a864-4edb-9ae4-4b7ab2ca185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648257267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1648257267
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.514623446
Short name T960
Test name
Test status
Simulation time 7036426217 ps
CPU time 39.14 seconds
Started Mar 12 02:36:39 PM PDT 24
Finished Mar 12 02:37:19 PM PDT 24
Peak memory 266792 kb
Host smart-da2559ae-1431-45ca-b737-263f26cd9c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514623446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.514623446
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1623272322
Short name T645
Test name
Test status
Simulation time 49132635 ps
CPU time 0.6 seconds
Started Mar 12 02:36:28 PM PDT 24
Finished Mar 12 02:36:29 PM PDT 24
Peak memory 202504 kb
Host smart-b6d5f57a-c649-4324-8e1f-7efe6cf61c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623272322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1623272322
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.324695620
Short name T1247
Test name
Test status
Simulation time 5794868708 ps
CPU time 257.35 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:40:51 PM PDT 24
Peak memory 541704 kb
Host smart-5811f475-8c1b-4afe-92f6-eb21f72fceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324695620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.324695620
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1397969279
Short name T787
Test name
Test status
Simulation time 13400654211 ps
CPU time 38.75 seconds
Started Mar 12 02:36:30 PM PDT 24
Finished Mar 12 02:37:09 PM PDT 24
Peak memory 284164 kb
Host smart-17704a71-ebda-4b5d-96b0-207e28214c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397969279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1397969279
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.658157586
Short name T790
Test name
Test status
Simulation time 18305142192 ps
CPU time 659.46 seconds
Started Mar 12 02:36:32 PM PDT 24
Finished Mar 12 02:47:32 PM PDT 24
Peak memory 2739652 kb
Host smart-4aca155c-02db-4a2c-ac91-f3d94bcae61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658157586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.658157586
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2692995305
Short name T1157
Test name
Test status
Simulation time 18848932256 ps
CPU time 50.55 seconds
Started Mar 12 02:36:32 PM PDT 24
Finished Mar 12 02:37:23 PM PDT 24
Peak memory 213676 kb
Host smart-08e5788c-e30f-4aa4-b7ab-21e7f4bf6cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692995305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2692995305
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.837440433
Short name T803
Test name
Test status
Simulation time 5707922195 ps
CPU time 3.63 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:36:38 PM PDT 24
Peak memory 203620 kb
Host smart-894d4766-6e3a-443c-9e4b-066357ffd88e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837440433 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.837440433
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2901110372
Short name T920
Test name
Test status
Simulation time 10226517057 ps
CPU time 32.01 seconds
Started Mar 12 02:36:36 PM PDT 24
Finished Mar 12 02:37:08 PM PDT 24
Peak memory 408272 kb
Host smart-45344adc-cb6f-49ed-aa84-44e480898298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901110372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2901110372
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3238579913
Short name T610
Test name
Test status
Simulation time 10111141343 ps
CPU time 16.32 seconds
Started Mar 12 02:36:33 PM PDT 24
Finished Mar 12 02:36:50 PM PDT 24
Peak memory 312884 kb
Host smart-09e15fc9-f639-4e33-b3c5-7e2a7e7abf37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238579913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3238579913
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.4013305448
Short name T1058
Test name
Test status
Simulation time 492149823 ps
CPU time 2.72 seconds
Started Mar 12 02:36:35 PM PDT 24
Finished Mar 12 02:36:37 PM PDT 24
Peak memory 203564 kb
Host smart-31744152-c01f-40ac-82fb-639e3be0bb82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013305448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.4013305448
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2711108931
Short name T360
Test name
Test status
Simulation time 1657486741 ps
CPU time 4.21 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:36:39 PM PDT 24
Peak memory 203548 kb
Host smart-ba03e93c-430a-4792-9462-a17f9f70ca52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711108931 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2711108931
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1976008501
Short name T111
Test name
Test status
Simulation time 14065829772 ps
CPU time 105.94 seconds
Started Mar 12 02:36:35 PM PDT 24
Finished Mar 12 02:38:21 PM PDT 24
Peak memory 1772760 kb
Host smart-aa91433d-4115-4d42-a793-947048de6587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976008501 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1976008501
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.1112582056
Short name T170
Test name
Test status
Simulation time 2777729531 ps
CPU time 3.41 seconds
Started Mar 12 02:36:32 PM PDT 24
Finished Mar 12 02:36:36 PM PDT 24
Peak memory 203548 kb
Host smart-77d396c4-0b14-483f-9056-64c89891b705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112582056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.1112582056
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.2071248952
Short name T832
Test name
Test status
Simulation time 59125157836 ps
CPU time 97.4 seconds
Started Mar 12 02:36:32 PM PDT 24
Finished Mar 12 02:38:09 PM PDT 24
Peak memory 881704 kb
Host smart-48eea28a-a7cc-464e-a942-11e4bfae144c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071248952 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.2071248952
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1862398695
Short name T782
Test name
Test status
Simulation time 1230664160 ps
CPU time 24.59 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:36:59 PM PDT 24
Peak memory 203588 kb
Host smart-7a97be40-800a-4c1b-8221-aef305c106b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862398695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1862398695
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1972466887
Short name T52
Test name
Test status
Simulation time 26246263091 ps
CPU time 112.01 seconds
Started Mar 12 02:36:33 PM PDT 24
Finished Mar 12 02:38:25 PM PDT 24
Peak memory 1635392 kb
Host smart-09248664-b903-4e83-a474-748ce3d44c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972466887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1972466887
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.526113837
Short name T503
Test name
Test status
Simulation time 27563552993 ps
CPU time 8.29 seconds
Started Mar 12 02:36:34 PM PDT 24
Finished Mar 12 02:36:43 PM PDT 24
Peak memory 216060 kb
Host smart-05c2080f-ff03-4b42-be90-c060be508049
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526113837 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_unexp_stop.526113837
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2460961416
Short name T864
Test name
Test status
Simulation time 42528581 ps
CPU time 0.62 seconds
Started Mar 12 02:36:56 PM PDT 24
Finished Mar 12 02:36:58 PM PDT 24
Peak memory 203308 kb
Host smart-260ad905-e3be-4f2d-b3ab-574d9055223a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460961416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2460961416
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3504671547
Short name T409
Test name
Test status
Simulation time 82084130 ps
CPU time 1.14 seconds
Started Mar 12 02:36:47 PM PDT 24
Finished Mar 12 02:36:49 PM PDT 24
Peak memory 203472 kb
Host smart-5487d869-83b1-469b-abdb-64440e180b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504671547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3504671547
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.689041898
Short name T446
Test name
Test status
Simulation time 412516647 ps
CPU time 10.26 seconds
Started Mar 12 02:36:41 PM PDT 24
Finished Mar 12 02:36:51 PM PDT 24
Peak memory 238328 kb
Host smart-95f81628-9a92-4b09-a601-7093a7209d06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689041898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.689041898
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.380062515
Short name T813
Test name
Test status
Simulation time 6812059922 ps
CPU time 98.12 seconds
Started Mar 12 02:36:41 PM PDT 24
Finished Mar 12 02:38:19 PM PDT 24
Peak memory 868288 kb
Host smart-f741e3c1-b30f-4426-93e1-2fe93817224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380062515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.380062515
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3303895560
Short name T899
Test name
Test status
Simulation time 10437440858 ps
CPU time 83.87 seconds
Started Mar 12 02:36:39 PM PDT 24
Finished Mar 12 02:38:03 PM PDT 24
Peak memory 828660 kb
Host smart-600d017b-8ffb-4aa6-985b-6d27788336e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303895560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3303895560
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.348704727
Short name T928
Test name
Test status
Simulation time 77062214 ps
CPU time 0.94 seconds
Started Mar 12 02:36:41 PM PDT 24
Finished Mar 12 02:36:42 PM PDT 24
Peak memory 203280 kb
Host smart-1180cb48-099b-43de-bc2b-991e6bab401e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348704727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.348704727
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1166728998
Short name T591
Test name
Test status
Simulation time 195676665 ps
CPU time 4.08 seconds
Started Mar 12 02:36:38 PM PDT 24
Finished Mar 12 02:36:43 PM PDT 24
Peak memory 203528 kb
Host smart-44185810-d71e-4197-b54c-8d7ea1914352
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166728998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1166728998
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2913099920
Short name T514
Test name
Test status
Simulation time 19691795504 ps
CPU time 157.2 seconds
Started Mar 12 02:36:48 PM PDT 24
Finished Mar 12 02:39:25 PM PDT 24
Peak memory 1389900 kb
Host smart-8d1edc2f-ae57-4ee4-9d7f-5ff16acb3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913099920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2913099920
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1635679293
Short name T911
Test name
Test status
Simulation time 5726901600 ps
CPU time 41.89 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:37:42 PM PDT 24
Peak memory 283476 kb
Host smart-4027cf89-33f2-4426-ab35-b7913d5fb85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635679293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1635679293
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2036761501
Short name T354
Test name
Test status
Simulation time 16225118 ps
CPU time 0.64 seconds
Started Mar 12 02:36:40 PM PDT 24
Finished Mar 12 02:36:41 PM PDT 24
Peak memory 202580 kb
Host smart-1f6abdfe-394a-45d4-a67c-104a2b73e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036761501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2036761501
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3284282168
Short name T828
Test name
Test status
Simulation time 15523596765 ps
CPU time 3355.01 seconds
Started Mar 12 02:36:44 PM PDT 24
Finished Mar 12 03:32:40 PM PDT 24
Peak memory 2787736 kb
Host smart-92009737-1d2b-4695-92c8-e9687e3cef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284282168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3284282168
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.4146319758
Short name T204
Test name
Test status
Simulation time 1639804868 ps
CPU time 12.81 seconds
Started Mar 12 02:36:48 PM PDT 24
Finished Mar 12 02:37:01 PM PDT 24
Peak memory 219412 kb
Host smart-c1f87f8c-318e-46e2-90e5-5464b5ca53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146319758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.4146319758
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1507373418
Short name T883
Test name
Test status
Simulation time 10182091046 ps
CPU time 12.47 seconds
Started Mar 12 02:36:48 PM PDT 24
Finished Mar 12 02:37:01 PM PDT 24
Peak memory 268936 kb
Host smart-2d1acd3c-f100-4fd3-8c33-fc264263813a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507373418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1507373418
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3882236460
Short name T245
Test name
Test status
Simulation time 10598842059 ps
CPU time 10.87 seconds
Started Mar 12 02:36:50 PM PDT 24
Finished Mar 12 02:37:01 PM PDT 24
Peak memory 298328 kb
Host smart-02d5ac18-8cdc-49f4-b8a3-8d3cac88979e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882236460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3882236460
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3296298077
Short name T255
Test name
Test status
Simulation time 1563574251 ps
CPU time 6.4 seconds
Started Mar 12 02:36:45 PM PDT 24
Finished Mar 12 02:36:52 PM PDT 24
Peak memory 207480 kb
Host smart-c6d283c7-6b79-47cb-b12d-8cb704fc5cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296298077 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3296298077
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3797320870
Short name T365
Test name
Test status
Simulation time 13850638991 ps
CPU time 125.56 seconds
Started Mar 12 02:36:45 PM PDT 24
Finished Mar 12 02:38:51 PM PDT 24
Peak memory 1811364 kb
Host smart-ad76291d-6595-4575-b8b6-0ed6d9bd8475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797320870 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3797320870
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3944115070
Short name T1125
Test name
Test status
Simulation time 8860374724 ps
CPU time 3.6 seconds
Started Mar 12 02:36:51 PM PDT 24
Finished Mar 12 02:36:55 PM PDT 24
Peak memory 203664 kb
Host smart-c75725a3-f46d-4695-9c4f-96a2437b7776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944115070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3944115070
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.2882659472
Short name T340
Test name
Test status
Simulation time 51395631017 ps
CPU time 59.26 seconds
Started Mar 12 02:36:49 PM PDT 24
Finished Mar 12 02:37:49 PM PDT 24
Peak memory 333504 kb
Host smart-fa624c1e-1cff-4687-96c7-3d5b4b088634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882659472 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.2882659472
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2360050950
Short name T750
Test name
Test status
Simulation time 520152334 ps
CPU time 6.73 seconds
Started Mar 12 02:36:46 PM PDT 24
Finished Mar 12 02:36:53 PM PDT 24
Peak memory 203600 kb
Host smart-6eb0a147-64a4-42d1-9185-abeacfbcab32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360050950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2360050950
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.518638487
Short name T1164
Test name
Test status
Simulation time 37082604237 ps
CPU time 153.03 seconds
Started Mar 12 02:36:44 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 2203068 kb
Host smart-66ae5b17-3da5-496a-b4f3-7875bacc839f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518638487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.518638487
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2705138415
Short name T280
Test name
Test status
Simulation time 21129766515 ps
CPU time 462.72 seconds
Started Mar 12 02:36:46 PM PDT 24
Finished Mar 12 02:44:29 PM PDT 24
Peak memory 2517180 kb
Host smart-f3233699-f122-4306-bb76-02839fe09c22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705138415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2705138415
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.3601131403
Short name T622
Test name
Test status
Simulation time 5098957439 ps
CPU time 6.66 seconds
Started Mar 12 02:36:48 PM PDT 24
Finished Mar 12 02:36:55 PM PDT 24
Peak memory 205376 kb
Host smart-d430570b-f5ba-4087-a56e-3d909e822c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601131403 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.3601131403
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2924999103
Short name T240
Test name
Test status
Simulation time 35200640 ps
CPU time 0.6 seconds
Started Mar 12 02:37:08 PM PDT 24
Finished Mar 12 02:37:10 PM PDT 24
Peak memory 203340 kb
Host smart-a2717e49-af66-4d9f-8d18-72401ea0c0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924999103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2924999103
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.227814366
Short name T1112
Test name
Test status
Simulation time 89239154 ps
CPU time 1.31 seconds
Started Mar 12 02:37:02 PM PDT 24
Finished Mar 12 02:37:03 PM PDT 24
Peak memory 211772 kb
Host smart-d630a1b5-ca1a-403b-8d61-c9979a86ab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227814366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.227814366
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3973627000
Short name T228
Test name
Test status
Simulation time 396352277 ps
CPU time 8.77 seconds
Started Mar 12 02:36:56 PM PDT 24
Finished Mar 12 02:37:05 PM PDT 24
Peak memory 288596 kb
Host smart-c1ba2c76-9d14-4567-992c-f43441adfffe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973627000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3973627000
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3899847425
Short name T466
Test name
Test status
Simulation time 8208561889 ps
CPU time 48.02 seconds
Started Mar 12 02:36:56 PM PDT 24
Finished Mar 12 02:37:45 PM PDT 24
Peak memory 528764 kb
Host smart-2e35afd8-9be5-4baf-874d-3f42e81f8c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899847425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3899847425
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.4045671818
Short name T1190
Test name
Test status
Simulation time 2418790928 ps
CPU time 189.68 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:40:10 PM PDT 24
Peak memory 786068 kb
Host smart-828fccdd-82c1-4ced-89b7-442da852f31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045671818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.4045671818
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2700016879
Short name T238
Test name
Test status
Simulation time 111116385 ps
CPU time 1.07 seconds
Started Mar 12 02:36:56 PM PDT 24
Finished Mar 12 02:36:58 PM PDT 24
Peak memory 203524 kb
Host smart-1eadcfd6-0455-4b9c-a8f3-d1000c3a9f8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700016879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2700016879
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3089213564
Short name T1143
Test name
Test status
Simulation time 1619698522 ps
CPU time 10.57 seconds
Started Mar 12 02:36:57 PM PDT 24
Finished Mar 12 02:37:08 PM PDT 24
Peak memory 234640 kb
Host smart-e9c32659-f042-4620-ac73-8485796ff632
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089213564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3089213564
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.754786315
Short name T150
Test name
Test status
Simulation time 12745605185 ps
CPU time 79.78 seconds
Started Mar 12 02:36:55 PM PDT 24
Finished Mar 12 02:38:16 PM PDT 24
Peak memory 964856 kb
Host smart-7cc7cf08-6a49-4d05-97f2-74e386a97490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754786315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.754786315
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2345076711
Short name T521
Test name
Test status
Simulation time 9052091752 ps
CPU time 134.85 seconds
Started Mar 12 02:37:08 PM PDT 24
Finished Mar 12 02:39:27 PM PDT 24
Peak memory 439220 kb
Host smart-e2698a09-1b14-4f46-be3d-b490c9bde6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345076711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2345076711
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1878819263
Short name T849
Test name
Test status
Simulation time 15332866 ps
CPU time 0.64 seconds
Started Mar 12 02:36:56 PM PDT 24
Finished Mar 12 02:36:57 PM PDT 24
Peak memory 202508 kb
Host smart-e127eb93-fdaa-4b99-8270-843b8549a7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878819263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1878819263
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3481465365
Short name T1269
Test name
Test status
Simulation time 3023049566 ps
CPU time 47.55 seconds
Started Mar 12 02:36:57 PM PDT 24
Finished Mar 12 02:37:45 PM PDT 24
Peak memory 223200 kb
Host smart-a80604bd-966b-4841-95c7-a96ff8ae9163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481465365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3481465365
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2184821957
Short name T1075
Test name
Test status
Simulation time 12936978807 ps
CPU time 36.79 seconds
Started Mar 12 02:36:55 PM PDT 24
Finished Mar 12 02:37:33 PM PDT 24
Peak memory 294172 kb
Host smart-630ecb57-37a5-4870-81c5-9c6cdac871c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184821957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2184821957
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1509298510
Short name T1266
Test name
Test status
Simulation time 3039041274 ps
CPU time 10.83 seconds
Started Mar 12 02:37:01 PM PDT 24
Finished Mar 12 02:37:12 PM PDT 24
Peak memory 219832 kb
Host smart-429d1118-5f2e-42f0-a960-e3c7a071004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509298510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1509298510
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2487104046
Short name T1134
Test name
Test status
Simulation time 3588677396 ps
CPU time 5.05 seconds
Started Mar 12 02:37:02 PM PDT 24
Finished Mar 12 02:37:08 PM PDT 24
Peak memory 203708 kb
Host smart-6e2eb25c-b8a7-488f-a034-2b46de4e497c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487104046 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2487104046
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3753377738
Short name T400
Test name
Test status
Simulation time 10215845107 ps
CPU time 12.38 seconds
Started Mar 12 02:37:02 PM PDT 24
Finished Mar 12 02:37:15 PM PDT 24
Peak memory 283832 kb
Host smart-1860af47-e312-472e-9cf9-78b3563fbead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753377738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3753377738
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3966377334
Short name T930
Test name
Test status
Simulation time 10059725237 ps
CPU time 39.96 seconds
Started Mar 12 02:37:01 PM PDT 24
Finished Mar 12 02:37:41 PM PDT 24
Peak memory 464220 kb
Host smart-c5d171bd-95e3-4aa0-ba7f-9789afcb8686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966377334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3966377334
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3995907214
Short name T56
Test name
Test status
Simulation time 590231990 ps
CPU time 2.95 seconds
Started Mar 12 02:37:06 PM PDT 24
Finished Mar 12 02:37:10 PM PDT 24
Peak memory 203652 kb
Host smart-5beb90d3-b957-4f81-af0a-1b1c36961ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995907214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3995907214
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2256195495
Short name T557
Test name
Test status
Simulation time 4750555833 ps
CPU time 5.68 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:37:06 PM PDT 24
Peak memory 203608 kb
Host smart-129d05ed-bea5-4631-a871-ac55632cb157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256195495 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2256195495
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3082860138
Short name T319
Test name
Test status
Simulation time 15965276101 ps
CPU time 186.87 seconds
Started Mar 12 02:37:02 PM PDT 24
Finished Mar 12 02:40:09 PM PDT 24
Peak memory 2295804 kb
Host smart-967b7c3a-4618-4f86-a823-930ff5859b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082860138 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3082860138
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.3477033270
Short name T384
Test name
Test status
Simulation time 3373994038 ps
CPU time 4.98 seconds
Started Mar 12 02:37:01 PM PDT 24
Finished Mar 12 02:37:06 PM PDT 24
Peak memory 203672 kb
Host smart-c4c88366-d99e-49d7-b512-0eac5adbdbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477033270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.3477033270
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.586998931
Short name T194
Test name
Test status
Simulation time 42458289104 ps
CPU time 40.28 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:37:41 PM PDT 24
Peak memory 263392 kb
Host smart-ded282ae-45df-42cd-ba9b-5a629e44c348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586998931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_target_stress_all.586998931
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2601597034
Short name T1074
Test name
Test status
Simulation time 13416414870 ps
CPU time 27.71 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:37:28 PM PDT 24
Peak memory 203616 kb
Host smart-281d55cb-7d17-4548-9ac6-eb1cfe529d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601597034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2601597034
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2285064742
Short name T364
Test name
Test status
Simulation time 30847820150 ps
CPU time 654.39 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:47:55 PM PDT 24
Peak memory 3684464 kb
Host smart-9025d009-b5c3-4e37-a359-1d3c84963d63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285064742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2285064742
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3255951065
Short name T958
Test name
Test status
Simulation time 6261452029 ps
CPU time 7.18 seconds
Started Mar 12 02:37:00 PM PDT 24
Finished Mar 12 02:37:08 PM PDT 24
Peak memory 212000 kb
Host smart-7d2e0c10-307d-43ef-a332-d24ee06943a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255951065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3255951065
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.5831777
Short name T730
Test name
Test status
Simulation time 902551281 ps
CPU time 4.91 seconds
Started Mar 12 02:37:03 PM PDT 24
Finished Mar 12 02:37:08 PM PDT 24
Peak memory 203640 kb
Host smart-000452b6-03b2-466e-b9b6-4d6f78bb23af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5831777 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_unexp_stop.5831777
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.917054856
Short name T332
Test name
Test status
Simulation time 17103115 ps
CPU time 0.63 seconds
Started Mar 12 02:32:56 PM PDT 24
Finished Mar 12 02:32:57 PM PDT 24
Peak memory 202392 kb
Host smart-d91dc1a1-4c6e-4cfd-a950-a872e51c02c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917054856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.917054856
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2559410390
Short name T498
Test name
Test status
Simulation time 71944791 ps
CPU time 1.16 seconds
Started Mar 12 02:32:50 PM PDT 24
Finished Mar 12 02:32:51 PM PDT 24
Peak memory 219896 kb
Host smart-08a63755-112e-444f-a0ae-71761259b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559410390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2559410390
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2323484530
Short name T901
Test name
Test status
Simulation time 357029329 ps
CPU time 6.62 seconds
Started Mar 12 02:32:40 PM PDT 24
Finished Mar 12 02:32:47 PM PDT 24
Peak memory 276516 kb
Host smart-807af650-75b2-4e11-a0a3-b8c37e280ba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323484530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2323484530
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.865952821
Short name T260
Test name
Test status
Simulation time 4081419032 ps
CPU time 144.41 seconds
Started Mar 12 02:32:45 PM PDT 24
Finished Mar 12 02:35:09 PM PDT 24
Peak memory 662644 kb
Host smart-1ffdde90-b9f8-4494-bbe8-b924c8cda218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865952821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.865952821
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3974709148
Short name T1146
Test name
Test status
Simulation time 5858943352 ps
CPU time 42.05 seconds
Started Mar 12 02:32:43 PM PDT 24
Finished Mar 12 02:33:25 PM PDT 24
Peak memory 555820 kb
Host smart-fee0c1e6-15fe-4fcf-a406-268f5e21b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974709148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3974709148
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2958295013
Short name T690
Test name
Test status
Simulation time 165189211 ps
CPU time 0.78 seconds
Started Mar 12 02:32:40 PM PDT 24
Finished Mar 12 02:32:41 PM PDT 24
Peak memory 203284 kb
Host smart-678f2a49-bdfe-4e53-ab4f-1fed34a855cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958295013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2958295013
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3610317937
Short name T2
Test name
Test status
Simulation time 157628371 ps
CPU time 3.31 seconds
Started Mar 12 02:32:45 PM PDT 24
Finished Mar 12 02:32:48 PM PDT 24
Peak memory 203516 kb
Host smart-9b9c406e-bea4-4627-8128-2cf87879add6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610317937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3610317937
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.624666774
Short name T746
Test name
Test status
Simulation time 21561899301 ps
CPU time 168.35 seconds
Started Mar 12 02:36:21 PM PDT 24
Finished Mar 12 02:39:10 PM PDT 24
Peak memory 1520908 kb
Host smart-c3ef9bf2-1d91-4212-8c50-853619e7259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624666774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.624666774
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3445155862
Short name T580
Test name
Test status
Simulation time 3012676908 ps
CPU time 36.45 seconds
Started Mar 12 02:32:58 PM PDT 24
Finished Mar 12 02:33:34 PM PDT 24
Peak memory 265912 kb
Host smart-3caaf609-c49a-437d-9a2b-0de41e8f9be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445155862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3445155862
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1550495410
Short name T167
Test name
Test status
Simulation time 97934051 ps
CPU time 0.64 seconds
Started Mar 12 02:32:42 PM PDT 24
Finished Mar 12 02:32:43 PM PDT 24
Peak memory 202516 kb
Host smart-95270adc-267c-4dc9-9970-a4d8010abc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550495410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1550495410
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.4149018870
Short name T1174
Test name
Test status
Simulation time 8268532159 ps
CPU time 42.99 seconds
Started Mar 12 02:32:44 PM PDT 24
Finished Mar 12 02:33:27 PM PDT 24
Peak memory 219900 kb
Host smart-97b722d7-86a3-44f8-9e30-024d169f0f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149018870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.4149018870
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4080332494
Short name T970
Test name
Test status
Simulation time 990049878 ps
CPU time 20.51 seconds
Started Mar 12 02:32:41 PM PDT 24
Finished Mar 12 02:33:02 PM PDT 24
Peak memory 252456 kb
Host smart-417ead37-d5ef-49d1-95f0-259bcc0687cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080332494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4080332494
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.422182224
Short name T211
Test name
Test status
Simulation time 3458151285 ps
CPU time 13.76 seconds
Started Mar 12 02:32:43 PM PDT 24
Finished Mar 12 02:32:56 PM PDT 24
Peak memory 211976 kb
Host smart-7125e4a4-d1ba-4fe2-bb6b-2d8b94bd2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422182224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.422182224
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2948986143
Short name T105
Test name
Test status
Simulation time 302078542 ps
CPU time 0.85 seconds
Started Mar 12 02:32:56 PM PDT 24
Finished Mar 12 02:32:56 PM PDT 24
Peak memory 220984 kb
Host smart-c4d64a56-19b3-4f93-84fc-628207473441
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948986143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2948986143
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1034557016
Short name T31
Test name
Test status
Simulation time 972903832 ps
CPU time 3.85 seconds
Started Mar 12 02:32:50 PM PDT 24
Finished Mar 12 02:32:54 PM PDT 24
Peak memory 203584 kb
Host smart-dd773b7f-f801-44be-88b8-da9c7dd73da8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034557016 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1034557016
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1569153348
Short name T713
Test name
Test status
Simulation time 10662443079 ps
CPU time 8.82 seconds
Started Mar 12 02:32:50 PM PDT 24
Finished Mar 12 02:32:59 PM PDT 24
Peak memory 274136 kb
Host smart-3c44821c-aa1d-45da-85b2-32b93a40ee95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569153348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1569153348
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3925903688
Short name T55
Test name
Test status
Simulation time 1152724035 ps
CPU time 2.42 seconds
Started Mar 12 02:32:51 PM PDT 24
Finished Mar 12 02:32:53 PM PDT 24
Peak memory 203612 kb
Host smart-d4975e09-8549-483b-920e-02614f58fde2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925903688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3925903688
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3272553446
Short name T434
Test name
Test status
Simulation time 1342074330 ps
CPU time 5.96 seconds
Started Mar 12 02:32:50 PM PDT 24
Finished Mar 12 02:32:56 PM PDT 24
Peak memory 209296 kb
Host smart-905f0ade-2048-43ef-bafc-3aa9f16df9bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272553446 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3272553446
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3808213845
Short name T564
Test name
Test status
Simulation time 24336087250 ps
CPU time 662.8 seconds
Started Mar 12 02:32:51 PM PDT 24
Finished Mar 12 02:43:54 PM PDT 24
Peak memory 4393312 kb
Host smart-7e9e5a70-4b37-4c46-bded-7f074e73c371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808213845 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3808213845
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2255185436
Short name T1131
Test name
Test status
Simulation time 725605814 ps
CPU time 3.67 seconds
Started Mar 12 02:32:53 PM PDT 24
Finished Mar 12 02:32:57 PM PDT 24
Peak memory 203592 kb
Host smart-818a34cc-bc90-4f8e-8304-8336a55ecad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255185436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2255185436
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3863908844
Short name T251
Test name
Test status
Simulation time 12271552322 ps
CPU time 7.42 seconds
Started Mar 12 02:32:45 PM PDT 24
Finished Mar 12 02:32:52 PM PDT 24
Peak memory 203684 kb
Host smart-87680e64-05fe-4675-ace4-6ac709f3214a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863908844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3863908844
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.929629142
Short name T569
Test name
Test status
Simulation time 10058648680 ps
CPU time 9.25 seconds
Started Mar 12 02:32:51 PM PDT 24
Finished Mar 12 02:33:01 PM PDT 24
Peak memory 208776 kb
Host smart-c64b38f0-4997-4124-bbdb-035e899b07d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929629142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.929629142
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.2928824983
Short name T623
Test name
Test status
Simulation time 1345255928 ps
CPU time 5.67 seconds
Started Mar 12 02:32:51 PM PDT 24
Finished Mar 12 02:32:56 PM PDT 24
Peak memory 210516 kb
Host smart-67e1b8dc-2e46-4698-9b98-ea10f77570a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928824983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.2928824983
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3267514559
Short name T739
Test name
Test status
Simulation time 59177060 ps
CPU time 0.6 seconds
Started Mar 12 02:37:18 PM PDT 24
Finished Mar 12 02:37:19 PM PDT 24
Peak memory 202356 kb
Host smart-ed0b57b6-489b-4b3e-9b7f-7fb6b20c0739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267514559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3267514559
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1165060472
Short name T244
Test name
Test status
Simulation time 844441154 ps
CPU time 4.13 seconds
Started Mar 12 02:37:06 PM PDT 24
Finished Mar 12 02:37:11 PM PDT 24
Peak memory 233476 kb
Host smart-5b1abd5e-2b90-49be-858a-5a9104abf161
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165060472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1165060472
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4209536778
Short name T837
Test name
Test status
Simulation time 5783318665 ps
CPU time 111.6 seconds
Started Mar 12 02:37:05 PM PDT 24
Finished Mar 12 02:38:57 PM PDT 24
Peak memory 881804 kb
Host smart-0ba28fec-ec64-4632-b7b5-81f0c4e6dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209536778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4209536778
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1745196510
Short name T1166
Test name
Test status
Simulation time 1845226346 ps
CPU time 54.9 seconds
Started Mar 12 02:37:05 PM PDT 24
Finished Mar 12 02:38:01 PM PDT 24
Peak memory 661792 kb
Host smart-378b2194-2e0e-414b-a8e6-e05b00d9f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745196510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1745196510
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3229972934
Short name T445
Test name
Test status
Simulation time 462432614 ps
CPU time 0.96 seconds
Started Mar 12 02:37:08 PM PDT 24
Finished Mar 12 02:37:10 PM PDT 24
Peak memory 203328 kb
Host smart-1a4b97cc-54fc-488d-b648-7ec3e3040103
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229972934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3229972934
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.427972339
Short name T179
Test name
Test status
Simulation time 613256515 ps
CPU time 3.81 seconds
Started Mar 12 02:37:06 PM PDT 24
Finished Mar 12 02:37:10 PM PDT 24
Peak memory 203556 kb
Host smart-c97f425b-d02a-4ac0-9ba6-dccd8392346f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427972339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
427972339
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1224741723
Short name T878
Test name
Test status
Simulation time 11044259358 ps
CPU time 76.31 seconds
Started Mar 12 02:37:07 PM PDT 24
Finished Mar 12 02:38:23 PM PDT 24
Peak memory 1000128 kb
Host smart-3aae9901-bcce-4965-ba88-dec2e2a0995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224741723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1224741723
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2251227230
Short name T417
Test name
Test status
Simulation time 6055769622 ps
CPU time 93.53 seconds
Started Mar 12 02:37:19 PM PDT 24
Finished Mar 12 02:38:53 PM PDT 24
Peak memory 268632 kb
Host smart-894b7a41-a6eb-4e29-b221-75d613a63ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251227230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2251227230
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3619471654
Short name T163
Test name
Test status
Simulation time 56977641 ps
CPU time 0.62 seconds
Started Mar 12 02:37:08 PM PDT 24
Finished Mar 12 02:37:10 PM PDT 24
Peak memory 202544 kb
Host smart-db635da7-c121-47c5-9993-42ddf509dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619471654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3619471654
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1466686109
Short name T1102
Test name
Test status
Simulation time 26521038825 ps
CPU time 164.22 seconds
Started Mar 12 02:37:05 PM PDT 24
Finished Mar 12 02:39:49 PM PDT 24
Peak memory 344360 kb
Host smart-8c511627-cc52-4aab-af03-eebb0c0b58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466686109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1466686109
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.248797373
Short name T459
Test name
Test status
Simulation time 1865972117 ps
CPU time 40.91 seconds
Started Mar 12 02:37:08 PM PDT 24
Finished Mar 12 02:37:53 PM PDT 24
Peak memory 261580 kb
Host smart-4a1ca3a8-3d0a-492f-a893-c94f2149e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248797373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.248797373
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3493335022
Short name T46
Test name
Test status
Simulation time 22446072472 ps
CPU time 1341.34 seconds
Started Mar 12 02:37:12 PM PDT 24
Finished Mar 12 02:59:34 PM PDT 24
Peak memory 1119908 kb
Host smart-661a41f3-ff4c-43c5-bb99-4204f2c59a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493335022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3493335022
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2481361069
Short name T207
Test name
Test status
Simulation time 682651740 ps
CPU time 12.28 seconds
Started Mar 12 02:37:17 PM PDT 24
Finished Mar 12 02:37:29 PM PDT 24
Peak memory 213212 kb
Host smart-fb2aee89-0e92-44b4-b646-dacfe56aba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481361069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2481361069
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3822294625
Short name T1205
Test name
Test status
Simulation time 4349101885 ps
CPU time 4.59 seconds
Started Mar 12 02:37:18 PM PDT 24
Finished Mar 12 02:37:22 PM PDT 24
Peak memory 203644 kb
Host smart-8aa3b45d-27a5-44b6-bbbc-186deea2210b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822294625 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3822294625
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.4265456482
Short name T558
Test name
Test status
Simulation time 10058916061 ps
CPU time 102.5 seconds
Started Mar 12 02:37:13 PM PDT 24
Finished Mar 12 02:38:55 PM PDT 24
Peak memory 766232 kb
Host smart-89f97c54-d9fc-4bd9-b240-0c6b6ffb87ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265456482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.4265456482
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2375980202
Short name T407
Test name
Test status
Simulation time 458813729 ps
CPU time 2.46 seconds
Started Mar 12 02:37:19 PM PDT 24
Finished Mar 12 02:37:22 PM PDT 24
Peak memory 203576 kb
Host smart-0499a194-e726-46f9-a0c6-847bebe99a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375980202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2375980202
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3014406263
Short name T1232
Test name
Test status
Simulation time 22128541295 ps
CPU time 60.17 seconds
Started Mar 12 02:37:11 PM PDT 24
Finished Mar 12 02:38:12 PM PDT 24
Peak memory 1002640 kb
Host smart-54f2191b-0331-4576-a09f-49f0e3522433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014406263 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3014406263
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.922362342
Short name T344
Test name
Test status
Simulation time 1493787301 ps
CPU time 5.38 seconds
Started Mar 12 02:37:13 PM PDT 24
Finished Mar 12 02:37:20 PM PDT 24
Peak memory 209404 kb
Host smart-5f792a7b-150a-4767-a216-d09e07d681ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922362342 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_perf.922362342
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2310832657
Short name T602
Test name
Test status
Simulation time 41106799773 ps
CPU time 710.42 seconds
Started Mar 12 02:37:11 PM PDT 24
Finished Mar 12 02:49:03 PM PDT 24
Peak memory 5184916 kb
Host smart-9e02b4a2-b541-4b21-899f-e00b9e32ff43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310832657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2310832657
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3037292677
Short name T529
Test name
Test status
Simulation time 2151399122 ps
CPU time 6.72 seconds
Started Mar 12 02:37:12 PM PDT 24
Finished Mar 12 02:37:19 PM PDT 24
Peak memory 207516 kb
Host smart-7b29ee77-c891-4e3f-986a-0dd936d87817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037292677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3037292677
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.693301197
Short name T629
Test name
Test status
Simulation time 1153888194 ps
CPU time 6.33 seconds
Started Mar 12 02:37:12 PM PDT 24
Finished Mar 12 02:37:18 PM PDT 24
Peak memory 203552 kb
Host smart-83d6be2f-fa79-434b-9459-f1dd80c2dba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693301197 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_unexp_stop.693301197
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3923477317
Short name T94
Test name
Test status
Simulation time 90415044 ps
CPU time 0.6 seconds
Started Mar 12 02:37:29 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 202392 kb
Host smart-5d682c33-4dd1-45b5-b5c2-ea60e8c994fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923477317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3923477317
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1189082165
Short name T395
Test name
Test status
Simulation time 42426098 ps
CPU time 1.25 seconds
Started Mar 12 02:37:17 PM PDT 24
Finished Mar 12 02:37:19 PM PDT 24
Peak memory 211696 kb
Host smart-9c1f7f55-6014-4ad5-87b4-e21be52f572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189082165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1189082165
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.601337143
Short name T846
Test name
Test status
Simulation time 726537209 ps
CPU time 3.67 seconds
Started Mar 12 02:37:21 PM PDT 24
Finished Mar 12 02:37:24 PM PDT 24
Peak memory 236764 kb
Host smart-fef80911-55f9-46e2-ac44-42004464c38e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601337143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.601337143
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.450803176
Short name T262
Test name
Test status
Simulation time 7606832999 ps
CPU time 118.18 seconds
Started Mar 12 02:37:20 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 557536 kb
Host smart-af11d30d-8314-4483-a5d7-8274b9260aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450803176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.450803176
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2458015788
Short name T295
Test name
Test status
Simulation time 12595985978 ps
CPU time 148.01 seconds
Started Mar 12 02:37:17 PM PDT 24
Finished Mar 12 02:39:46 PM PDT 24
Peak memory 670520 kb
Host smart-2dbedf9e-cd76-4d56-9a76-05618e17c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458015788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2458015788
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2309657539
Short name T181
Test name
Test status
Simulation time 542598245 ps
CPU time 1.06 seconds
Started Mar 12 02:37:20 PM PDT 24
Finished Mar 12 02:37:21 PM PDT 24
Peak memory 203556 kb
Host smart-8e8897e6-c468-4e35-84ed-46af93fa1031
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309657539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2309657539
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.110589143
Short name T682
Test name
Test status
Simulation time 761400665 ps
CPU time 9.9 seconds
Started Mar 12 02:37:18 PM PDT 24
Finished Mar 12 02:37:28 PM PDT 24
Peak memory 203556 kb
Host smart-2e45feaf-e7fd-4319-b886-aa15f4d62853
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110589143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
110589143
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.124124851
Short name T357
Test name
Test status
Simulation time 11284193591 ps
CPU time 83.27 seconds
Started Mar 12 02:37:29 PM PDT 24
Finished Mar 12 02:38:55 PM PDT 24
Peak memory 359256 kb
Host smart-0da98b2c-3b00-429f-89ce-38e43183da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124124851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.124124851
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2160709268
Short name T6
Test name
Test status
Simulation time 50176108 ps
CPU time 0.64 seconds
Started Mar 12 02:37:19 PM PDT 24
Finished Mar 12 02:37:20 PM PDT 24
Peak memory 203248 kb
Host smart-05db929a-637c-426b-a07c-072ea4ca56c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160709268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2160709268
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.441776617
Short name T961
Test name
Test status
Simulation time 52587498547 ps
CPU time 339.4 seconds
Started Mar 12 02:37:18 PM PDT 24
Finished Mar 12 02:42:58 PM PDT 24
Peak memory 211736 kb
Host smart-8a16d5d8-1d31-4038-88bb-d14dec9ccf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441776617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.441776617
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2382146577
Short name T978
Test name
Test status
Simulation time 2776825726 ps
CPU time 79.29 seconds
Started Mar 12 02:37:21 PM PDT 24
Finished Mar 12 02:38:41 PM PDT 24
Peak memory 228140 kb
Host smart-d651ba9b-460f-4edb-b42d-ad41d7dcf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382146577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2382146577
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3055173255
Short name T291
Test name
Test status
Simulation time 3211331522 ps
CPU time 9.37 seconds
Started Mar 12 02:37:18 PM PDT 24
Finished Mar 12 02:37:27 PM PDT 24
Peak memory 213252 kb
Host smart-de9d5f5a-584e-48a0-82c4-d4d94595227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055173255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3055173255
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2358908928
Short name T470
Test name
Test status
Simulation time 16081091970 ps
CPU time 3.7 seconds
Started Mar 12 02:37:32 PM PDT 24
Finished Mar 12 02:37:38 PM PDT 24
Peak memory 203648 kb
Host smart-32ab0476-17f0-41e3-aea0-799fc1e9d855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358908928 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2358908928
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.4188471082
Short name T909
Test name
Test status
Simulation time 10307042562 ps
CPU time 13.16 seconds
Started Mar 12 02:37:23 PM PDT 24
Finished Mar 12 02:37:37 PM PDT 24
Peak memory 316440 kb
Host smart-3fc3d907-ee78-4109-a5a9-ef0139d01f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188471082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.4188471082
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.630462935
Short name T673
Test name
Test status
Simulation time 1887760875 ps
CPU time 2.57 seconds
Started Mar 12 02:37:28 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 203592 kb
Host smart-52da5503-0578-4761-80dd-f15c261af192
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630462935 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.630462935
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1474796688
Short name T32
Test name
Test status
Simulation time 9727490373 ps
CPU time 9.07 seconds
Started Mar 12 02:37:23 PM PDT 24
Finished Mar 12 02:37:33 PM PDT 24
Peak memory 219820 kb
Host smart-429aece1-8a21-498c-b8ab-edf9898de0ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474796688 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1474796688
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1148932581
Short name T568
Test name
Test status
Simulation time 7690017746 ps
CPU time 9.08 seconds
Started Mar 12 02:37:25 PM PDT 24
Finished Mar 12 02:37:35 PM PDT 24
Peak memory 203612 kb
Host smart-e5d3b93b-b65b-4847-98de-ac9f6419e937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148932581 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1148932581
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.1801036871
Short name T981
Test name
Test status
Simulation time 4606384023 ps
CPU time 4.7 seconds
Started Mar 12 02:37:22 PM PDT 24
Finished Mar 12 02:37:27 PM PDT 24
Peak memory 203664 kb
Host smart-bf1daf9a-4d13-4637-994b-8afba73b1a92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801036871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.1801036871
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.820541362
Short name T638
Test name
Test status
Simulation time 9885456190 ps
CPU time 48.64 seconds
Started Mar 12 02:37:23 PM PDT 24
Finished Mar 12 02:38:12 PM PDT 24
Peak memory 228608 kb
Host smart-45c1c91b-86c0-4beb-a695-dd871d6dcc06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820541362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.820541362
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3236409927
Short name T801
Test name
Test status
Simulation time 23281143217 ps
CPU time 57.95 seconds
Started Mar 12 02:37:23 PM PDT 24
Finished Mar 12 02:38:21 PM PDT 24
Peak memory 205480 kb
Host smart-8c04a464-02ec-4155-a682-2d1c67a18b84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236409927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3236409927
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1402629514
Short name T1033
Test name
Test status
Simulation time 2838295101 ps
CPU time 48.78 seconds
Started Mar 12 02:37:24 PM PDT 24
Finished Mar 12 02:38:14 PM PDT 24
Peak memory 804964 kb
Host smart-679937dc-04c9-4663-98f1-cf65e4f82069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402629514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1402629514
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1100647060
Short name T910
Test name
Test status
Simulation time 1597624250 ps
CPU time 6.69 seconds
Started Mar 12 02:37:24 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 203620 kb
Host smart-5d3f456c-c8ef-4120-88e2-d9796adb18f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100647060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1100647060
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.1404693209
Short name T1025
Test name
Test status
Simulation time 1228939987 ps
CPU time 6.56 seconds
Started Mar 12 02:37:22 PM PDT 24
Finished Mar 12 02:37:28 PM PDT 24
Peak memory 203632 kb
Host smart-bef8ee18-592e-405f-89e2-fb1966c500f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404693209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.1404693209
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3056359527
Short name T655
Test name
Test status
Simulation time 24964407 ps
CPU time 0.6 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:37:43 PM PDT 24
Peak memory 202364 kb
Host smart-6c04fdce-2992-4921-ad72-4b1ab485e628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056359527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3056359527
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.746757578
Short name T60
Test name
Test status
Simulation time 109871111 ps
CPU time 1.63 seconds
Started Mar 12 02:37:36 PM PDT 24
Finished Mar 12 02:37:38 PM PDT 24
Peak memory 211780 kb
Host smart-d5dfc3e8-f505-48df-83a0-deaf4f56dac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746757578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.746757578
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2516664012
Short name T458
Test name
Test status
Simulation time 731478406 ps
CPU time 8.08 seconds
Started Mar 12 02:37:30 PM PDT 24
Finished Mar 12 02:37:41 PM PDT 24
Peak memory 280448 kb
Host smart-54119399-e238-451e-aae6-56369d67d9eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516664012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.2516664012
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.416608271
Short name T959
Test name
Test status
Simulation time 29813166127 ps
CPU time 144.52 seconds
Started Mar 12 02:37:37 PM PDT 24
Finished Mar 12 02:40:02 PM PDT 24
Peak memory 558580 kb
Host smart-d91fcadc-83b2-4e2a-a32a-8a86f521f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416608271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.416608271
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1662337346
Short name T1148
Test name
Test status
Simulation time 3093625635 ps
CPU time 103.6 seconds
Started Mar 12 02:37:32 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 502688 kb
Host smart-119097b9-a12f-464d-a82c-c82337095722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662337346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1662337346
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2108477872
Short name T736
Test name
Test status
Simulation time 263346384 ps
CPU time 0.95 seconds
Started Mar 12 02:37:29 PM PDT 24
Finished Mar 12 02:37:32 PM PDT 24
Peak memory 203120 kb
Host smart-3cd98d2f-612c-4a5b-a79a-a9a1d3417cb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108477872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2108477872
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1378764735
Short name T896
Test name
Test status
Simulation time 837134502 ps
CPU time 4.37 seconds
Started Mar 12 02:37:43 PM PDT 24
Finished Mar 12 02:37:48 PM PDT 24
Peak memory 203596 kb
Host smart-69b55551-c388-42d9-bcf8-5f7fe4feab63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378764735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1378764735
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2136129179
Short name T491
Test name
Test status
Simulation time 12071038913 ps
CPU time 199.63 seconds
Started Mar 12 02:37:28 PM PDT 24
Finished Mar 12 02:40:49 PM PDT 24
Peak memory 1675012 kb
Host smart-689bf769-cf42-4fa2-ba66-ddda8963121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136129179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2136129179
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2003868743
Short name T1006
Test name
Test status
Simulation time 41699855347 ps
CPU time 92.19 seconds
Started Mar 12 02:37:43 PM PDT 24
Finished Mar 12 02:39:16 PM PDT 24
Peak memory 324132 kb
Host smart-3fd0aaba-6edd-4983-975c-e74b87dd991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003868743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2003868743
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1117058555
Short name T1165
Test name
Test status
Simulation time 39493989 ps
CPU time 0.6 seconds
Started Mar 12 02:37:33 PM PDT 24
Finished Mar 12 02:37:37 PM PDT 24
Peak memory 202532 kb
Host smart-078067b9-d79c-4ea4-a30b-f8c516b281f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117058555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1117058555
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3231561566
Short name T107
Test name
Test status
Simulation time 639979509 ps
CPU time 11.07 seconds
Started Mar 12 02:37:35 PM PDT 24
Finished Mar 12 02:37:48 PM PDT 24
Peak memory 221304 kb
Host smart-22452bab-18d5-45ef-a83c-146ba553c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231561566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3231561566
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3606813514
Short name T860
Test name
Test status
Simulation time 10536875423 ps
CPU time 136.62 seconds
Started Mar 12 02:37:29 PM PDT 24
Finished Mar 12 02:39:48 PM PDT 24
Peak memory 279720 kb
Host smart-cc865c30-1edd-442b-abb8-a321e9286237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606813514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3606813514
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.809094397
Short name T234
Test name
Test status
Simulation time 2363653275 ps
CPU time 11.49 seconds
Started Mar 12 02:37:35 PM PDT 24
Finished Mar 12 02:37:48 PM PDT 24
Peak memory 214336 kb
Host smart-382aca28-ecaa-4209-8e3b-192335d4c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809094397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.809094397
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2280759485
Short name T1159
Test name
Test status
Simulation time 10118412535 ps
CPU time 55.72 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:38:38 PM PDT 24
Peak memory 526888 kb
Host smart-adce9fa9-ed7d-497b-a6b3-672443357608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280759485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2280759485
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.356725384
Short name T243
Test name
Test status
Simulation time 10461336067 ps
CPU time 10.46 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:37:52 PM PDT 24
Peak memory 282700 kb
Host smart-cf97ba7b-5f59-43fc-b7ff-2f39025e29c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356725384 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.356725384
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.116169751
Short name T758
Test name
Test status
Simulation time 1016010613 ps
CPU time 2.56 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:37:45 PM PDT 24
Peak memory 203608 kb
Host smart-03d5bba2-9787-4458-996d-65297acab823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116169751 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.116169751
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2176639760
Short name T848
Test name
Test status
Simulation time 18045360231 ps
CPU time 262.21 seconds
Started Mar 12 02:37:36 PM PDT 24
Finished Mar 12 02:41:59 PM PDT 24
Peak memory 2811440 kb
Host smart-b638b8af-d831-43f2-98a3-24e45ab66b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176639760 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2176639760
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.2779509375
Short name T1071
Test name
Test status
Simulation time 6450772493 ps
CPU time 5.07 seconds
Started Mar 12 02:37:45 PM PDT 24
Finished Mar 12 02:37:50 PM PDT 24
Peak memory 203584 kb
Host smart-d7fe6d05-c6ff-4f07-b898-ad5965474938
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779509375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.2779509375
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.678086903
Short name T688
Test name
Test status
Simulation time 1288901515 ps
CPU time 6.71 seconds
Started Mar 12 02:37:36 PM PDT 24
Finished Mar 12 02:37:43 PM PDT 24
Peak memory 203532 kb
Host smart-07f75888-0905-471a-a331-502b5e3cfc10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678086903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.678086903
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2014118073
Short name T358
Test name
Test status
Simulation time 39370941353 ps
CPU time 87.05 seconds
Started Mar 12 02:37:39 PM PDT 24
Finished Mar 12 02:39:07 PM PDT 24
Peak memory 1457432 kb
Host smart-97b26914-dca2-4c7c-b2f9-318e1f512a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014118073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2014118073
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3585589014
Short name T523
Test name
Test status
Simulation time 14107470101 ps
CPU time 517.7 seconds
Started Mar 12 02:37:38 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 1696472 kb
Host smart-b3fb5517-83f8-40ed-b471-e4a773c303c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585589014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3585589014
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3291808421
Short name T816
Test name
Test status
Simulation time 1800692660 ps
CPU time 8.09 seconds
Started Mar 12 02:37:36 PM PDT 24
Finished Mar 12 02:37:45 PM PDT 24
Peak memory 207532 kb
Host smart-3a2e04aa-6602-4706-91ce-12f0571d6056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291808421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3291808421
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.250667715
Short name T34
Test name
Test status
Simulation time 6390640594 ps
CPU time 6.34 seconds
Started Mar 12 02:37:36 PM PDT 24
Finished Mar 12 02:37:43 PM PDT 24
Peak memory 208628 kb
Host smart-5994d474-30be-451d-9db1-7092ccec2bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250667715 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_unexp_stop.250667715
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.321230148
Short name T450
Test name
Test status
Simulation time 25430425 ps
CPU time 0.58 seconds
Started Mar 12 02:37:59 PM PDT 24
Finished Mar 12 02:38:00 PM PDT 24
Peak memory 203392 kb
Host smart-ddbba974-b7b5-45de-abc5-ffc8b866c0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321230148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.321230148
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2606448047
Short name T1196
Test name
Test status
Simulation time 53256848 ps
CPU time 1.51 seconds
Started Mar 12 02:37:50 PM PDT 24
Finished Mar 12 02:37:52 PM PDT 24
Peak memory 211808 kb
Host smart-8934d394-626b-439b-8e58-4e394a64d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606448047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2606448047
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.675757317
Short name T373
Test name
Test status
Simulation time 517005326 ps
CPU time 8.22 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 02:37:59 PM PDT 24
Peak memory 290284 kb
Host smart-f428f311-05bf-458f-9296-4bc091eef489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675757317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.675757317
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3660985128
Short name T1256
Test name
Test status
Simulation time 2575999336 ps
CPU time 183.99 seconds
Started Mar 12 02:37:52 PM PDT 24
Finished Mar 12 02:40:57 PM PDT 24
Peak memory 818016 kb
Host smart-cbf651cc-5c8d-4304-8fe6-5468711f5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660985128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3660985128
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.208581611
Short name T791
Test name
Test status
Simulation time 3077814991 ps
CPU time 88.61 seconds
Started Mar 12 02:37:43 PM PDT 24
Finished Mar 12 02:39:12 PM PDT 24
Peak memory 846828 kb
Host smart-672e3ba4-f788-4412-a54f-1235161b6e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208581611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.208581611
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1182090277
Short name T815
Test name
Test status
Simulation time 131028280 ps
CPU time 1.14 seconds
Started Mar 12 02:37:52 PM PDT 24
Finished Mar 12 02:37:55 PM PDT 24
Peak memory 203576 kb
Host smart-57afc036-0e73-4853-9bd5-a37589b51f0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182090277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1182090277
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2090145138
Short name T922
Test name
Test status
Simulation time 537931809 ps
CPU time 7.6 seconds
Started Mar 12 02:37:52 PM PDT 24
Finished Mar 12 02:38:01 PM PDT 24
Peak memory 258264 kb
Host smart-81fea530-ac01-4ee9-a516-62fdadfd5730
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090145138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2090145138
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3003182726
Short name T148
Test name
Test status
Simulation time 14728843316 ps
CPU time 89.03 seconds
Started Mar 12 02:37:43 PM PDT 24
Finished Mar 12 02:39:13 PM PDT 24
Peak memory 1119808 kb
Host smart-607183a4-ca03-4507-92e0-f7551adbc6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003182726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3003182726
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2406345918
Short name T26
Test name
Test status
Simulation time 2928905946 ps
CPU time 78.38 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:39:16 PM PDT 24
Peak memory 228116 kb
Host smart-7d9ec925-fed7-487a-881e-08c1ac760575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406345918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2406345918
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.462424704
Short name T1150
Test name
Test status
Simulation time 31805227 ps
CPU time 0.64 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:37:43 PM PDT 24
Peak memory 202576 kb
Host smart-fbba7f72-916e-4e46-a02a-02c2444ffc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462424704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.462424704
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1116509238
Short name T1255
Test name
Test status
Simulation time 2639282470 ps
CPU time 53.27 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 02:38:45 PM PDT 24
Peak memory 268300 kb
Host smart-b7f2cef7-37dd-4fbb-b26b-f56b55804f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116509238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1116509238
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3154016451
Short name T513
Test name
Test status
Simulation time 1074949323 ps
CPU time 26.67 seconds
Started Mar 12 02:37:42 PM PDT 24
Finished Mar 12 02:38:09 PM PDT 24
Peak memory 266072 kb
Host smart-c7b34330-a013-4a02-ba1b-ef2f83734ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154016451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3154016451
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2968814304
Short name T504
Test name
Test status
Simulation time 570087472 ps
CPU time 10.05 seconds
Started Mar 12 02:37:53 PM PDT 24
Finished Mar 12 02:38:04 PM PDT 24
Peak memory 211772 kb
Host smart-2bd3deb9-940b-4646-ae13-6ca0a0019c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968814304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2968814304
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.41518268
Short name T678
Test name
Test status
Simulation time 840420515 ps
CPU time 4.25 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:38:01 PM PDT 24
Peak memory 203620 kb
Host smart-8d48a356-9faf-494d-bb69-a71bbdb8c59f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518268 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_bad_addr.41518268
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2190029906
Short name T264
Test name
Test status
Simulation time 10100187627 ps
CPU time 45.08 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:38:42 PM PDT 24
Peak memory 480560 kb
Host smart-2585fe2f-fd16-4e0a-9b70-6b163f1e0d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190029906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2190029906
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3113148682
Short name T266
Test name
Test status
Simulation time 10062884398 ps
CPU time 32.8 seconds
Started Mar 12 02:37:58 PM PDT 24
Finished Mar 12 02:38:31 PM PDT 24
Peak memory 442176 kb
Host smart-af957f9b-6f1b-446e-9ea3-acbce7393200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113148682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3113148682
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2583254898
Short name T693
Test name
Test status
Simulation time 11812725613 ps
CPU time 16.15 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 02:38:08 PM PDT 24
Peak memory 424788 kb
Host smart-bfd393da-66ed-4815-b0ab-ac8f6d587d37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583254898 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2583254898
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.2166581794
Short name T1092
Test name
Test status
Simulation time 657251937 ps
CPU time 4.2 seconds
Started Mar 12 02:37:59 PM PDT 24
Finished Mar 12 02:38:03 PM PDT 24
Peak memory 203632 kb
Host smart-4ffc4c40-1b54-4ecf-9d92-cddb8bb0f17d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166581794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.2166581794
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.4109761775
Short name T67
Test name
Test status
Simulation time 6722053197 ps
CPU time 45.54 seconds
Started Mar 12 02:37:52 PM PDT 24
Finished Mar 12 02:38:39 PM PDT 24
Peak memory 203568 kb
Host smart-04adaff1-5351-4aa6-a9e6-454d25a9c39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109761775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.4109761775
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2455935185
Short name T1014
Test name
Test status
Simulation time 2149398735 ps
CPU time 14.3 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 02:38:07 PM PDT 24
Peak memory 203624 kb
Host smart-7516de08-a965-42af-8927-9e6b8c046911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455935185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2455935185
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1510528911
Short name T305
Test name
Test status
Simulation time 30843433361 ps
CPU time 196.02 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 02:41:09 PM PDT 24
Peak memory 2644612 kb
Host smart-eaaf314b-cdc4-4328-b4f8-114253158e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510528911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1510528911
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2405141362
Short name T882
Test name
Test status
Simulation time 39543725682 ps
CPU time 3577.45 seconds
Started Mar 12 02:37:51 PM PDT 24
Finished Mar 12 03:37:29 PM PDT 24
Peak memory 8786884 kb
Host smart-da0c95c4-ba85-44ae-801e-5fd0c5d8e5a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405141362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2405141362
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.4190758554
Short name T808
Test name
Test status
Simulation time 9286550817 ps
CPU time 7.2 seconds
Started Mar 12 02:37:53 PM PDT 24
Finished Mar 12 02:38:01 PM PDT 24
Peak memory 213948 kb
Host smart-b6c1dec5-0aef-47f6-8c75-dd900ea4b92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190758554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.4190758554
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.177918499
Short name T894
Test name
Test status
Simulation time 38808621 ps
CPU time 0.62 seconds
Started Mar 12 02:38:07 PM PDT 24
Finished Mar 12 02:38:08 PM PDT 24
Peak memory 203304 kb
Host smart-fc89639a-a4df-4e16-b5ed-b61f4ca3a5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177918499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.177918499
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1261459503
Short name T438
Test name
Test status
Simulation time 167209663 ps
CPU time 1.5 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:37:59 PM PDT 24
Peak memory 211780 kb
Host smart-b9de8a69-ac37-4c96-a0a4-3f4f12ba4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261459503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1261459503
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3868740075
Short name T1251
Test name
Test status
Simulation time 473829056 ps
CPU time 9.19 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:38:07 PM PDT 24
Peak memory 271720 kb
Host smart-75d81329-23d7-4050-935c-d288ac941bd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868740075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3868740075
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2604156320
Short name T442
Test name
Test status
Simulation time 35313818050 ps
CPU time 79.1 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:39:17 PM PDT 24
Peak memory 778212 kb
Host smart-b04ebe82-1d7d-46d1-8987-34bdf0a639b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604156320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2604156320
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1450999709
Short name T520
Test name
Test status
Simulation time 2576870414 ps
CPU time 76.15 seconds
Started Mar 12 02:37:59 PM PDT 24
Finished Mar 12 02:39:16 PM PDT 24
Peak memory 786436 kb
Host smart-935280c8-05d4-417f-a918-03d9578b9ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450999709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1450999709
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1287910764
Short name T512
Test name
Test status
Simulation time 148008781 ps
CPU time 0.82 seconds
Started Mar 12 02:37:58 PM PDT 24
Finished Mar 12 02:37:59 PM PDT 24
Peak memory 203268 kb
Host smart-33938783-9912-480f-a7a2-859e7271d4ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287910764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1287910764
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.717741518
Short name T1009
Test name
Test status
Simulation time 645746101 ps
CPU time 8.81 seconds
Started Mar 12 02:37:56 PM PDT 24
Finished Mar 12 02:38:05 PM PDT 24
Peak memory 203584 kb
Host smart-94e81beb-3206-4d05-a93b-777ae70f17d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717741518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
717741518
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2763262528
Short name T205
Test name
Test status
Simulation time 23703721422 ps
CPU time 491.37 seconds
Started Mar 12 02:37:59 PM PDT 24
Finished Mar 12 02:46:10 PM PDT 24
Peak memory 1649024 kb
Host smart-c96e6316-571f-46b8-8ed2-dc882b073c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763262528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2763262528
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2879992236
Short name T545
Test name
Test status
Simulation time 36131237121 ps
CPU time 49.43 seconds
Started Mar 12 02:38:03 PM PDT 24
Finished Mar 12 02:38:53 PM PDT 24
Peak memory 291960 kb
Host smart-d9855439-6ab9-49ec-b3e3-615600912fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879992236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2879992236
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.850060961
Short name T186
Test name
Test status
Simulation time 16071524 ps
CPU time 0.66 seconds
Started Mar 12 02:37:57 PM PDT 24
Finished Mar 12 02:37:58 PM PDT 24
Peak memory 203248 kb
Host smart-395f5866-0be4-4f21-9404-bcc1e82ac54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850060961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.850060961
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3951157401
Short name T1160
Test name
Test status
Simulation time 3000251962 ps
CPU time 22.68 seconds
Started Mar 12 02:37:56 PM PDT 24
Finished Mar 12 02:38:18 PM PDT 24
Peak memory 211748 kb
Host smart-d4ebc5f5-6414-4cc3-ba75-2ba89976e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951157401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3951157401
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3323110520
Short name T492
Test name
Test status
Simulation time 12294728877 ps
CPU time 115.15 seconds
Started Mar 12 02:37:58 PM PDT 24
Finished Mar 12 02:39:53 PM PDT 24
Peak memory 267000 kb
Host smart-869a56e0-b0bc-40d3-baac-c59a73c8b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323110520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3323110520
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.20973644
Short name T1208
Test name
Test status
Simulation time 4775160037 ps
CPU time 49.38 seconds
Started Mar 12 02:38:00 PM PDT 24
Finished Mar 12 02:38:49 PM PDT 24
Peak memory 212772 kb
Host smart-6b7a9a9b-9c62-4213-833f-0e541150774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20973644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.20973644
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2919653420
Short name T764
Test name
Test status
Simulation time 1696492018 ps
CPU time 2.2 seconds
Started Mar 12 02:38:06 PM PDT 24
Finished Mar 12 02:38:08 PM PDT 24
Peak memory 203560 kb
Host smart-90483a16-b4c3-4271-ba79-cba2470c6dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919653420 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2919653420
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3733068560
Short name T755
Test name
Test status
Simulation time 10034963915 ps
CPU time 67.38 seconds
Started Mar 12 02:38:04 PM PDT 24
Finished Mar 12 02:39:12 PM PDT 24
Peak memory 543800 kb
Host smart-cee88965-fc69-4849-b346-6c12a2153739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733068560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3733068560
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1918299454
Short name T505
Test name
Test status
Simulation time 10324573071 ps
CPU time 13.64 seconds
Started Mar 12 02:38:06 PM PDT 24
Finished Mar 12 02:38:20 PM PDT 24
Peak memory 320024 kb
Host smart-286d9c7c-0065-47d0-853d-ed7203be49d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918299454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1918299454
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4119064497
Short name T917
Test name
Test status
Simulation time 867802497 ps
CPU time 2.19 seconds
Started Mar 12 02:38:03 PM PDT 24
Finished Mar 12 02:38:05 PM PDT 24
Peak memory 203584 kb
Host smart-32df0b2f-42cc-42cc-9bfa-4a38b06da5c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119064497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4119064497
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3085510428
Short name T1268
Test name
Test status
Simulation time 5422314556 ps
CPU time 5.2 seconds
Started Mar 12 02:38:02 PM PDT 24
Finished Mar 12 02:38:07 PM PDT 24
Peak memory 203564 kb
Host smart-c362b546-c873-40f4-b1cc-70926baf0970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085510428 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3085510428
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1944720794
Short name T966
Test name
Test status
Simulation time 3894054949 ps
CPU time 4.48 seconds
Started Mar 12 02:38:06 PM PDT 24
Finished Mar 12 02:38:11 PM PDT 24
Peak memory 203608 kb
Host smart-0772fa63-8896-4940-94f9-aa1ab0257c57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944720794 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1944720794
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.654235823
Short name T227
Test name
Test status
Simulation time 1002796749 ps
CPU time 2.97 seconds
Started Mar 12 02:38:05 PM PDT 24
Finished Mar 12 02:38:08 PM PDT 24
Peak memory 203540 kb
Host smart-d42c3e0d-27c0-44e9-a783-9d3e7968342d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654235823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_perf.654235823
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.1643262074
Short name T259
Test name
Test status
Simulation time 21288772343 ps
CPU time 29.85 seconds
Started Mar 12 02:38:05 PM PDT 24
Finished Mar 12 02:38:35 PM PDT 24
Peak memory 273784 kb
Host smart-6305ed45-781c-4366-b766-8ceca3918590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643262074 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.1643262074
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.4109564452
Short name T804
Test name
Test status
Simulation time 26633325928 ps
CPU time 111.88 seconds
Started Mar 12 02:37:58 PM PDT 24
Finished Mar 12 02:39:50 PM PDT 24
Peak memory 1688984 kb
Host smart-f1434072-b828-4cef-ab2f-3500beb518b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109564452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.4109564452
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2943585156
Short name T432
Test name
Test status
Simulation time 3570251598 ps
CPU time 7.27 seconds
Started Mar 12 02:38:07 PM PDT 24
Finished Mar 12 02:38:14 PM PDT 24
Peak memory 212692 kb
Host smart-2f971b81-620d-4172-a1e1-67fadce9d43f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943585156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2943585156
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.907737962
Short name T621
Test name
Test status
Simulation time 6604311144 ps
CPU time 8.53 seconds
Started Mar 12 02:38:04 PM PDT 24
Finished Mar 12 02:38:13 PM PDT 24
Peak memory 211276 kb
Host smart-0a54de27-f331-42cc-8313-c4422b58044d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907737962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_unexp_stop.907737962
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1939288311
Short name T456
Test name
Test status
Simulation time 19613844 ps
CPU time 0.64 seconds
Started Mar 12 02:38:26 PM PDT 24
Finished Mar 12 02:38:27 PM PDT 24
Peak memory 203344 kb
Host smart-167b9cf8-c09d-48c3-a914-a3cddcbb4123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939288311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1939288311
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1380079565
Short name T1066
Test name
Test status
Simulation time 35300495 ps
CPU time 1.71 seconds
Started Mar 12 02:38:08 PM PDT 24
Finished Mar 12 02:38:10 PM PDT 24
Peak memory 211756 kb
Host smart-1228f77c-722a-4c86-9f0f-9157f0d4e862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380079565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1380079565
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3379194951
Short name T217
Test name
Test status
Simulation time 1297851465 ps
CPU time 7.02 seconds
Started Mar 12 02:38:09 PM PDT 24
Finished Mar 12 02:38:16 PM PDT 24
Peak memory 271912 kb
Host smart-8d5c10d1-599f-4015-b04e-cb6dd8cdf222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379194951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3379194951
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.714697010
Short name T428
Test name
Test status
Simulation time 6438326384 ps
CPU time 44.59 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:38:54 PM PDT 24
Peak memory 435740 kb
Host smart-f8280435-ac05-4f64-bf88-c2163d5b9534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714697010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.714697010
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3761848902
Short name T38
Test name
Test status
Simulation time 7665193113 ps
CPU time 56.53 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:39:06 PM PDT 24
Peak memory 591808 kb
Host smart-72c4df30-9309-4e5f-864d-694122c8ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761848902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3761848902
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1438393552
Short name T774
Test name
Test status
Simulation time 463392666 ps
CPU time 0.95 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:38:11 PM PDT 24
Peak memory 203500 kb
Host smart-e831f7c7-8e91-47de-b6f2-f7dd9805871b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438393552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1438393552
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.701904289
Short name T1197
Test name
Test status
Simulation time 1171860167 ps
CPU time 6.32 seconds
Started Mar 12 02:38:08 PM PDT 24
Finished Mar 12 02:38:15 PM PDT 24
Peak memory 255160 kb
Host smart-87471aa7-23e1-42ca-9b23-cedfed600baf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701904289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
701904289
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1096984778
Short name T308
Test name
Test status
Simulation time 11965962598 ps
CPU time 192.84 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:41:23 PM PDT 24
Peak memory 1603184 kb
Host smart-dd7e153f-e208-422b-b7fd-5dd71de69426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096984778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1096984778
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2120112398
Short name T25
Test name
Test status
Simulation time 4710933193 ps
CPU time 37.69 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:39:02 PM PDT 24
Peak memory 264180 kb
Host smart-3b5c948c-3fb2-4834-82a1-9bcaffa99e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120112398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2120112398
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3026581239
Short name T1248
Test name
Test status
Simulation time 20914892 ps
CPU time 0.64 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:38:11 PM PDT 24
Peak memory 202532 kb
Host smart-9260c9cc-75c3-4816-b82c-2bab2f565f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026581239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3026581239
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1866091805
Short name T709
Test name
Test status
Simulation time 56398365533 ps
CPU time 185.46 seconds
Started Mar 12 02:38:09 PM PDT 24
Finished Mar 12 02:41:14 PM PDT 24
Peak memory 283992 kb
Host smart-7f7a2086-85fb-47b0-92a1-a7467b716d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866091805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1866091805
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1691539406
Short name T404
Test name
Test status
Simulation time 6867014747 ps
CPU time 50 seconds
Started Mar 12 02:38:05 PM PDT 24
Finished Mar 12 02:38:55 PM PDT 24
Peak memory 313432 kb
Host smart-7554fe2f-26fd-43b3-bb5a-7e5db124a6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691539406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1691539406
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1654817312
Short name T146
Test name
Test status
Simulation time 58639133368 ps
CPU time 937.71 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:53:48 PM PDT 24
Peak memory 1812448 kb
Host smart-d98205e8-733c-490b-bef5-3a4f13caffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654817312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1654817312
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3643768363
Short name T998
Test name
Test status
Simulation time 3446583911 ps
CPU time 13.51 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:38:24 PM PDT 24
Peak memory 213780 kb
Host smart-4f51fd9f-3dad-4ce5-9093-56501bbf0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643768363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3643768363
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3724117947
Short name T603
Test name
Test status
Simulation time 1549004854 ps
CPU time 6.09 seconds
Started Mar 12 02:38:17 PM PDT 24
Finished Mar 12 02:38:24 PM PDT 24
Peak memory 203548 kb
Host smart-94b7a550-b9ef-42a8-9db2-26069b991635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724117947 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3724117947
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1387518238
Short name T447
Test name
Test status
Simulation time 10859410505 ps
CPU time 14.06 seconds
Started Mar 12 02:38:17 PM PDT 24
Finished Mar 12 02:38:32 PM PDT 24
Peak memory 323048 kb
Host smart-d13a5ab9-3a9f-4283-b515-97e4e818ec85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387518238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1387518238
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1615097174
Short name T766
Test name
Test status
Simulation time 1945373434 ps
CPU time 2.4 seconds
Started Mar 12 02:38:23 PM PDT 24
Finished Mar 12 02:38:25 PM PDT 24
Peak memory 203560 kb
Host smart-216bb91d-acfb-400a-9adc-a29aa7c83fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615097174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1615097174
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3663505343
Short name T1122
Test name
Test status
Simulation time 8260889955 ps
CPU time 7.06 seconds
Started Mar 12 02:38:20 PM PDT 24
Finished Mar 12 02:38:27 PM PDT 24
Peak memory 210392 kb
Host smart-06dd0296-f1ed-4df2-8678-b51dd5a03efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663505343 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3663505343
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1238670889
Short name T195
Test name
Test status
Simulation time 10015037260 ps
CPU time 17.77 seconds
Started Mar 12 02:38:17 PM PDT 24
Finished Mar 12 02:38:36 PM PDT 24
Peak memory 456248 kb
Host smart-8c6dd7a2-2138-4d46-99f0-6570f851864b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238670889 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1238670889
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.736795874
Short name T818
Test name
Test status
Simulation time 894694180 ps
CPU time 5.48 seconds
Started Mar 12 02:38:17 PM PDT 24
Finished Mar 12 02:38:22 PM PDT 24
Peak memory 211028 kb
Host smart-458bf0ed-7516-493c-85e0-f3367d47d3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736795874 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_perf.736795874
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1222200802
Short name T191
Test name
Test status
Simulation time 3093975405 ps
CPU time 62.94 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:39:13 PM PDT 24
Peak memory 204712 kb
Host smart-349a23d3-6995-4e2e-84d6-cc011e272f75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222200802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1222200802
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1589003011
Short name T425
Test name
Test status
Simulation time 69624087502 ps
CPU time 1069.1 seconds
Started Mar 12 02:38:10 PM PDT 24
Finished Mar 12 02:55:59 PM PDT 24
Peak memory 6682044 kb
Host smart-916a11d0-7a45-4aac-80c9-a521c336bdeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589003011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1589003011
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3507578028
Short name T1223
Test name
Test status
Simulation time 2970670368 ps
CPU time 7.26 seconds
Started Mar 12 02:38:16 PM PDT 24
Finished Mar 12 02:38:23 PM PDT 24
Peak memory 214692 kb
Host smart-91776c21-b847-4ee0-a41b-d7005e61fbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507578028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3507578028
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.2816557059
Short name T1104
Test name
Test status
Simulation time 2070684539 ps
CPU time 6.57 seconds
Started Mar 12 02:38:17 PM PDT 24
Finished Mar 12 02:38:25 PM PDT 24
Peak memory 203628 kb
Host smart-2ec58381-1abe-410d-a262-231a4dca82e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816557059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.2816557059
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1050944169
Short name T1054
Test name
Test status
Simulation time 25948751 ps
CPU time 0.6 seconds
Started Mar 12 02:38:35 PM PDT 24
Finished Mar 12 02:38:36 PM PDT 24
Peak memory 202348 kb
Host smart-aa84c38e-a6a9-4b94-9392-27ef4672fccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050944169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1050944169
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2782241488
Short name T918
Test name
Test status
Simulation time 169757160 ps
CPU time 1.32 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:26 PM PDT 24
Peak memory 211776 kb
Host smart-be47666d-1b57-4b35-810d-37740c326852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782241488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2782241488
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3282385700
Short name T1184
Test name
Test status
Simulation time 428109739 ps
CPU time 9.93 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:34 PM PDT 24
Peak memory 299344 kb
Host smart-6b2c9369-f7b0-4076-9435-bccf9c62d854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282385700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3282385700
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1751043278
Short name T1065
Test name
Test status
Simulation time 6446463228 ps
CPU time 50.14 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:39:14 PM PDT 24
Peak memory 595052 kb
Host smart-3466f2d6-2dcb-472c-98c9-687d5669e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751043278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1751043278
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2172180333
Short name T859
Test name
Test status
Simulation time 7015457661 ps
CPU time 213 seconds
Started Mar 12 02:38:25 PM PDT 24
Finished Mar 12 02:41:58 PM PDT 24
Peak memory 852324 kb
Host smart-f6ca7958-c60c-416a-b12f-c950fbd1d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172180333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2172180333
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3494750761
Short name T389
Test name
Test status
Simulation time 1063062394 ps
CPU time 0.92 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:25 PM PDT 24
Peak memory 203272 kb
Host smart-0ea318b0-5847-4227-bb4d-be301f8f543b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494750761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3494750761
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.273308151
Short name T1152
Test name
Test status
Simulation time 285191428 ps
CPU time 5.59 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:30 PM PDT 24
Peak memory 203536 kb
Host smart-6861b74e-9772-4aac-a738-82b1d055435a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273308151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
273308151
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1996293599
Short name T484
Test name
Test status
Simulation time 2588264467 ps
CPU time 124.72 seconds
Started Mar 12 02:38:37 PM PDT 24
Finished Mar 12 02:40:42 PM PDT 24
Peak memory 228092 kb
Host smart-1dcee5f4-e9c5-4c4e-9df5-f04946a7be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996293599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1996293599
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3613126243
Short name T615
Test name
Test status
Simulation time 18377007 ps
CPU time 0.65 seconds
Started Mar 12 02:38:23 PM PDT 24
Finished Mar 12 02:38:24 PM PDT 24
Peak memory 202572 kb
Host smart-05e0fa61-a424-45ce-aa3a-829df522eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613126243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3613126243
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2100032456
Short name T187
Test name
Test status
Simulation time 8955364241 ps
CPU time 35.53 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:59 PM PDT 24
Peak memory 227868 kb
Host smart-129b1fca-4ed3-407f-9501-2f839b587ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100032456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2100032456
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1279272487
Short name T715
Test name
Test status
Simulation time 3715803875 ps
CPU time 45.48 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:39:09 PM PDT 24
Peak memory 266688 kb
Host smart-84a4e886-c676-4259-b90a-118434fc4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279272487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1279272487
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.4248232819
Short name T44
Test name
Test status
Simulation time 31638337736 ps
CPU time 1025.42 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:55:30 PM PDT 24
Peak memory 4095560 kb
Host smart-07b4af25-4ecd-4725-afcc-19d81eada5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248232819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4248232819
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2585321223
Short name T1051
Test name
Test status
Simulation time 1139550158 ps
CPU time 16.36 seconds
Started Mar 12 02:38:24 PM PDT 24
Finished Mar 12 02:38:40 PM PDT 24
Peak memory 230632 kb
Host smart-bbc4b6fb-758e-49a5-8633-f601ac3c0825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585321223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2585321223
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2514759223
Short name T468
Test name
Test status
Simulation time 10029698043 ps
CPU time 90.8 seconds
Started Mar 12 02:38:30 PM PDT 24
Finished Mar 12 02:40:00 PM PDT 24
Peak memory 721804 kb
Host smart-04320deb-1d96-4e7e-b310-7ade2d693416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514759223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2514759223
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.576378313
Short name T583
Test name
Test status
Simulation time 549355770 ps
CPU time 2.66 seconds
Started Mar 12 02:38:36 PM PDT 24
Finished Mar 12 02:38:39 PM PDT 24
Peak memory 203604 kb
Host smart-87e3676a-c235-4b13-8dc5-5d037d107505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576378313 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.576378313
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1846119943
Short name T788
Test name
Test status
Simulation time 13637626177 ps
CPU time 3.28 seconds
Started Mar 12 02:38:30 PM PDT 24
Finished Mar 12 02:38:33 PM PDT 24
Peak memory 203604 kb
Host smart-9851e937-8bd5-479c-8fad-01a785e6a61a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846119943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1846119943
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3209710145
Short name T424
Test name
Test status
Simulation time 15705064215 ps
CPU time 51.04 seconds
Started Mar 12 02:38:29 PM PDT 24
Finished Mar 12 02:39:20 PM PDT 24
Peak memory 1021676 kb
Host smart-a2233970-057c-4f51-99d9-d18d509d62d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209710145 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3209710145
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.302688814
Short name T1238
Test name
Test status
Simulation time 681489751 ps
CPU time 4.32 seconds
Started Mar 12 02:38:29 PM PDT 24
Finished Mar 12 02:38:34 PM PDT 24
Peak memory 207364 kb
Host smart-b84ba380-afe6-4241-9f6b-67fa6ec3db9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302688814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_perf.302688814
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1648825647
Short name T285
Test name
Test status
Simulation time 57271908015 ps
CPU time 194.46 seconds
Started Mar 12 02:38:29 PM PDT 24
Finished Mar 12 02:41:43 PM PDT 24
Peak memory 2333664 kb
Host smart-d2564a85-65f8-44a7-9534-f23991996fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648825647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1648825647
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.650692740
Short name T539
Test name
Test status
Simulation time 26148926545 ps
CPU time 1299.64 seconds
Started Mar 12 02:38:30 PM PDT 24
Finished Mar 12 03:00:09 PM PDT 24
Peak memory 3005828 kb
Host smart-6e93aa04-d3e0-48da-a3b2-56b080f5249d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650692740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.650692740
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2194310299
Short name T253
Test name
Test status
Simulation time 1309503426 ps
CPU time 6.17 seconds
Started Mar 12 02:38:31 PM PDT 24
Finished Mar 12 02:38:37 PM PDT 24
Peak memory 203620 kb
Host smart-af44f461-5094-40ae-81a8-9cb26932e1f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194310299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2194310299
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.2692747196
Short name T533
Test name
Test status
Simulation time 2643638589 ps
CPU time 6.73 seconds
Started Mar 12 02:38:30 PM PDT 24
Finished Mar 12 02:38:37 PM PDT 24
Peak memory 210688 kb
Host smart-07ed48f7-fa1d-47b4-8076-b92323ad430f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692747196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.2692747196
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2003330886
Short name T527
Test name
Test status
Simulation time 24430583 ps
CPU time 0.61 seconds
Started Mar 12 02:38:43 PM PDT 24
Finished Mar 12 02:38:44 PM PDT 24
Peak memory 203348 kb
Host smart-178f9e9d-ed96-493c-9f7e-d056e36d9230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003330886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2003330886
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2973536839
Short name T1031
Test name
Test status
Simulation time 194456280 ps
CPU time 1.57 seconds
Started Mar 12 02:38:40 PM PDT 24
Finished Mar 12 02:38:41 PM PDT 24
Peak memory 211760 kb
Host smart-2714ff98-0259-4c3e-aa27-12efdbe81621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973536839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2973536839
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1589338278
Short name T275
Test name
Test status
Simulation time 1019833315 ps
CPU time 3.82 seconds
Started Mar 12 02:38:36 PM PDT 24
Finished Mar 12 02:38:40 PM PDT 24
Peak memory 225624 kb
Host smart-4bcb6663-c644-44ca-a65a-00dddff22338
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589338278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1589338278
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.848113742
Short name T1175
Test name
Test status
Simulation time 2478369311 ps
CPU time 191.46 seconds
Started Mar 12 02:38:37 PM PDT 24
Finished Mar 12 02:41:48 PM PDT 24
Peak memory 819492 kb
Host smart-2e22b806-d219-41bd-ac98-d52f55d77d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848113742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.848113742
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2244605530
Short name T689
Test name
Test status
Simulation time 615359379 ps
CPU time 0.81 seconds
Started Mar 12 02:38:36 PM PDT 24
Finished Mar 12 02:38:37 PM PDT 24
Peak memory 202548 kb
Host smart-7e8fa0bf-9450-4f7d-8dba-3773e47678bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244605530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2244605530
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3738402154
Short name T929
Test name
Test status
Simulation time 188361394 ps
CPU time 9.83 seconds
Started Mar 12 02:38:35 PM PDT 24
Finished Mar 12 02:38:46 PM PDT 24
Peak memory 203456 kb
Host smart-1a7ea227-f9d1-4297-836d-e653fe1b88f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738402154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3738402154
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2350101214
Short name T592
Test name
Test status
Simulation time 10878528870 ps
CPU time 446.54 seconds
Started Mar 12 02:38:47 PM PDT 24
Finished Mar 12 02:46:14 PM PDT 24
Peak memory 1531948 kb
Host smart-fefa0f1f-a300-4007-96ae-906c022ad467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350101214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2350101214
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3105059033
Short name T858
Test name
Test status
Simulation time 7792595428 ps
CPU time 47.94 seconds
Started Mar 12 02:38:44 PM PDT 24
Finished Mar 12 02:39:33 PM PDT 24
Peak memory 254452 kb
Host smart-c6038d25-1481-4bec-a432-e9e3d454fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105059033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3105059033
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3211463597
Short name T747
Test name
Test status
Simulation time 18825162 ps
CPU time 0.63 seconds
Started Mar 12 02:38:49 PM PDT 24
Finished Mar 12 02:38:51 PM PDT 24
Peak memory 202516 kb
Host smart-b0474dac-80e0-4ad6-8086-2466023c1cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211463597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3211463597
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.200056594
Short name T1011
Test name
Test status
Simulation time 7448055758 ps
CPU time 59.76 seconds
Started Mar 12 02:38:36 PM PDT 24
Finished Mar 12 02:39:36 PM PDT 24
Peak memory 228076 kb
Host smart-484e1aed-0c87-4418-b386-0c22a00b660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200056594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.200056594
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3531962431
Short name T1086
Test name
Test status
Simulation time 11640638232 ps
CPU time 30.16 seconds
Started Mar 12 02:38:42 PM PDT 24
Finished Mar 12 02:39:12 PM PDT 24
Peak memory 249232 kb
Host smart-3edb1d48-b460-4fd6-8822-6b1a4e4d5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531962431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3531962431
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3349163985
Short name T976
Test name
Test status
Simulation time 2107535920 ps
CPU time 8.2 seconds
Started Mar 12 02:38:35 PM PDT 24
Finished Mar 12 02:38:43 PM PDT 24
Peak memory 212904 kb
Host smart-ee960ec4-0163-4dd1-b65b-537051909f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349163985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3349163985
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2361370834
Short name T352
Test name
Test status
Simulation time 1813844285 ps
CPU time 3.9 seconds
Started Mar 12 02:38:44 PM PDT 24
Finished Mar 12 02:38:49 PM PDT 24
Peak memory 203588 kb
Host smart-178ea7de-d4cc-4ec5-9eb9-469e2c19f936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361370834 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2361370834
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.756883597
Short name T1069
Test name
Test status
Simulation time 10051503930 ps
CPU time 57.23 seconds
Started Mar 12 02:38:44 PM PDT 24
Finished Mar 12 02:39:42 PM PDT 24
Peak memory 516576 kb
Host smart-ff7a55d0-2453-42b4-bd1a-44628eeba55b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756883597 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.756883597
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3154915874
Short name T54
Test name
Test status
Simulation time 593177007 ps
CPU time 2.8 seconds
Started Mar 12 02:38:44 PM PDT 24
Finished Mar 12 02:38:50 PM PDT 24
Peak memory 203540 kb
Host smart-b805cdd6-fd9b-443a-a9bd-a8b1c7540f49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154915874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3154915874
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3773204845
Short name T679
Test name
Test status
Simulation time 820743544 ps
CPU time 3.41 seconds
Started Mar 12 02:38:43 PM PDT 24
Finished Mar 12 02:38:47 PM PDT 24
Peak memory 203464 kb
Host smart-91fc3896-a373-4839-b407-737cc6440ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773204845 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3773204845
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3328765757
Short name T1194
Test name
Test status
Simulation time 13005186914 ps
CPU time 101.17 seconds
Started Mar 12 02:38:43 PM PDT 24
Finished Mar 12 02:40:25 PM PDT 24
Peak memory 1556212 kb
Host smart-9dc3e479-a26a-478c-9f8c-302cad4a2e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328765757 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3328765757
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.3291925022
Short name T112
Test name
Test status
Simulation time 3021359093 ps
CPU time 4.49 seconds
Started Mar 12 02:38:44 PM PDT 24
Finished Mar 12 02:38:51 PM PDT 24
Peak memory 203664 kb
Host smart-38971ea1-4a49-4fe1-8b3f-03b641fd6119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291925022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.3291925022
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.999101012
Short name T273
Test name
Test status
Simulation time 1096471635 ps
CPU time 43.14 seconds
Started Mar 12 02:38:43 PM PDT 24
Finished Mar 12 02:39:26 PM PDT 24
Peak memory 203588 kb
Host smart-3e6fde73-7e40-42f3-b578-f76f226e3d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999101012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.999101012
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1896840153
Short name T1027
Test name
Test status
Simulation time 30088975207 ps
CPU time 191.84 seconds
Started Mar 12 02:38:42 PM PDT 24
Finished Mar 12 02:41:54 PM PDT 24
Peak memory 2560260 kb
Host smart-1e48f772-4522-409a-99b3-5701ed7c0a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896840153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1896840153
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1044507188
Short name T727
Test name
Test status
Simulation time 2390478789 ps
CPU time 7.05 seconds
Started Mar 12 02:38:43 PM PDT 24
Finished Mar 12 02:38:50 PM PDT 24
Peak memory 208456 kb
Host smart-e789a47c-ef68-4755-ab3e-4fcfb5f5c208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044507188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1044507188
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1947881353
Short name T636
Test name
Test status
Simulation time 37140889 ps
CPU time 0.61 seconds
Started Mar 12 02:39:00 PM PDT 24
Finished Mar 12 02:39:01 PM PDT 24
Peak memory 202340 kb
Host smart-2ca9f122-7e7f-4c5c-9987-9b8c6f0ea6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947881353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1947881353
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.4079816171
Short name T43
Test name
Test status
Simulation time 83809402 ps
CPU time 2.13 seconds
Started Mar 12 02:38:54 PM PDT 24
Finished Mar 12 02:38:56 PM PDT 24
Peak memory 211812 kb
Host smart-1f3b27df-bed2-4258-8b81-4737ee66dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079816171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.4079816171
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2369939771
Short name T784
Test name
Test status
Simulation time 1532939798 ps
CPU time 25.13 seconds
Started Mar 12 02:38:51 PM PDT 24
Finished Mar 12 02:39:17 PM PDT 24
Peak memory 308720 kb
Host smart-8a32b0cc-37cd-4b63-ad61-53f981e706b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369939771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2369939771
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3335824101
Short name T1123
Test name
Test status
Simulation time 2815616912 ps
CPU time 201.98 seconds
Started Mar 12 02:38:51 PM PDT 24
Finished Mar 12 02:42:13 PM PDT 24
Peak memory 831280 kb
Host smart-6ff925e0-7149-4ce7-9f34-f5e0208d1a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335824101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3335824101
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1771503386
Short name T1002
Test name
Test status
Simulation time 8364837522 ps
CPU time 67.92 seconds
Started Mar 12 02:38:49 PM PDT 24
Finished Mar 12 02:39:57 PM PDT 24
Peak memory 736604 kb
Host smart-e4ec8e45-2b94-4692-b5d7-651809c2d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771503386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1771503386
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3668609865
Short name T823
Test name
Test status
Simulation time 123997526 ps
CPU time 0.99 seconds
Started Mar 12 02:38:52 PM PDT 24
Finished Mar 12 02:38:54 PM PDT 24
Peak memory 203244 kb
Host smart-e296ea8d-87f1-4929-87f7-cf984f34478d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668609865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3668609865
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2288312649
Short name T3
Test name
Test status
Simulation time 254748000 ps
CPU time 14.44 seconds
Started Mar 12 02:38:51 PM PDT 24
Finished Mar 12 02:39:07 PM PDT 24
Peak memory 253580 kb
Host smart-d016a3fb-c850-4ad8-9d55-b84aae658b8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288312649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2288312649
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1450939830
Short name T11
Test name
Test status
Simulation time 2590333287 ps
CPU time 124.04 seconds
Started Mar 12 02:39:02 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 247144 kb
Host smart-af412537-e699-4c78-bef3-94234ff91992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450939830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1450939830
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3506152369
Short name T4
Test name
Test status
Simulation time 26656626 ps
CPU time 0.64 seconds
Started Mar 12 02:38:48 PM PDT 24
Finished Mar 12 02:38:49 PM PDT 24
Peak memory 203204 kb
Host smart-9dd0f1e5-58ca-4c63-be30-7e2bf15b4ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506152369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3506152369
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3275814167
Short name T302
Test name
Test status
Simulation time 18822451606 ps
CPU time 215.52 seconds
Started Mar 12 02:38:52 PM PDT 24
Finished Mar 12 02:42:28 PM PDT 24
Peak memory 213248 kb
Host smart-e3cc1ce1-3298-443f-925e-3bf1d4720c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275814167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3275814167
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1165704374
Short name T1114
Test name
Test status
Simulation time 1404663951 ps
CPU time 41.46 seconds
Started Mar 12 02:38:46 PM PDT 24
Finished Mar 12 02:39:28 PM PDT 24
Peak memory 295316 kb
Host smart-a50a742e-b9ae-4f3c-8277-ff0d97e47069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165704374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1165704374
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3731984642
Short name T433
Test name
Test status
Simulation time 44161606740 ps
CPU time 579.77 seconds
Started Mar 12 02:38:50 PM PDT 24
Finished Mar 12 02:48:30 PM PDT 24
Peak memory 1516548 kb
Host smart-d695392a-6f5a-4b3f-81fd-ed5b1344f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731984642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3731984642
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1748365534
Short name T331
Test name
Test status
Simulation time 564442114 ps
CPU time 8.38 seconds
Started Mar 12 02:38:49 PM PDT 24
Finished Mar 12 02:38:58 PM PDT 24
Peak memory 211764 kb
Host smart-303f0b11-fa59-47ad-9311-8904491f6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748365534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1748365534
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3263485249
Short name T462
Test name
Test status
Simulation time 1653061912 ps
CPU time 4.16 seconds
Started Mar 12 02:39:02 PM PDT 24
Finished Mar 12 02:39:06 PM PDT 24
Peak memory 203632 kb
Host smart-4d5ede41-fec0-424d-9475-0c494d7cd3d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263485249 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3263485249
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1497785437
Short name T550
Test name
Test status
Simulation time 10045640172 ps
CPU time 82.89 seconds
Started Mar 12 02:38:52 PM PDT 24
Finished Mar 12 02:40:16 PM PDT 24
Peak memory 597656 kb
Host smart-f67751eb-2ffa-402c-8d36-e9c2537299ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497785437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1497785437
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.538616949
Short name T465
Test name
Test status
Simulation time 10118966241 ps
CPU time 39.71 seconds
Started Mar 12 02:39:03 PM PDT 24
Finished Mar 12 02:39:43 PM PDT 24
Peak memory 439760 kb
Host smart-75a27988-41c8-4715-8349-e256f26ebf95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538616949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.538616949
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.195525816
Short name T1227
Test name
Test status
Simulation time 3745787723 ps
CPU time 2.4 seconds
Started Mar 12 02:39:01 PM PDT 24
Finished Mar 12 02:39:04 PM PDT 24
Peak memory 203668 kb
Host smart-0f2be1d9-c8a1-46b3-8db0-d3934a602491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195525816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.195525816
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2191758639
Short name T838
Test name
Test status
Simulation time 2256067397 ps
CPU time 4.84 seconds
Started Mar 12 02:38:53 PM PDT 24
Finished Mar 12 02:38:58 PM PDT 24
Peak memory 205860 kb
Host smart-a1270a3c-428b-4d4c-a53b-f5a4515175b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191758639 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2191758639
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1682300135
Short name T1187
Test name
Test status
Simulation time 12283235726 ps
CPU time 36.26 seconds
Started Mar 12 02:38:53 PM PDT 24
Finished Mar 12 02:39:29 PM PDT 24
Peak memory 766872 kb
Host smart-540007e6-2efa-4ffd-a9d6-2b024b321b03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682300135 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1682300135
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.703680978
Short name T323
Test name
Test status
Simulation time 5304300499 ps
CPU time 4.3 seconds
Started Mar 12 02:39:00 PM PDT 24
Finished Mar 12 02:39:05 PM PDT 24
Peak memory 210332 kb
Host smart-5c3f25c6-4955-4f50-9f6b-1025efa2b1e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703680978 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_perf.703680978
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.883030740
Short name T284
Test name
Test status
Simulation time 12704248968 ps
CPU time 25 seconds
Started Mar 12 02:38:51 PM PDT 24
Finished Mar 12 02:39:17 PM PDT 24
Peak memory 203596 kb
Host smart-71ade907-3a46-44f4-9de2-4f48f55add2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883030740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.883030740
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.332113593
Short name T962
Test name
Test status
Simulation time 32284274851 ps
CPU time 21.33 seconds
Started Mar 12 02:38:50 PM PDT 24
Finished Mar 12 02:39:12 PM PDT 24
Peak memory 302084 kb
Host smart-5785553a-11c6-45b4-83df-cd5d2ad5dea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332113593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.332113593
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.719079222
Short name T852
Test name
Test status
Simulation time 6619203568 ps
CPU time 7.57 seconds
Started Mar 12 02:38:49 PM PDT 24
Finished Mar 12 02:38:57 PM PDT 24
Peak memory 203716 kb
Host smart-bd503d36-2035-4cd5-be2d-2acf1c39a799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719079222 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.719079222
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1299291610
Short name T413
Test name
Test status
Simulation time 47288158 ps
CPU time 0.64 seconds
Started Mar 12 02:39:14 PM PDT 24
Finished Mar 12 02:39:15 PM PDT 24
Peak memory 203360 kb
Host smart-e3426df1-9b06-4d74-82dc-29c6c8285c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299291610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1299291610
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.30912959
Short name T919
Test name
Test status
Simulation time 516108460 ps
CPU time 1.13 seconds
Started Mar 12 02:39:07 PM PDT 24
Finished Mar 12 02:39:09 PM PDT 24
Peak memory 219688 kb
Host smart-bd78dfa2-5c09-4bd9-afdd-fe97a49ec637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30912959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.30912959
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1974504961
Short name T1161
Test name
Test status
Simulation time 1816229714 ps
CPU time 13.78 seconds
Started Mar 12 02:39:07 PM PDT 24
Finished Mar 12 02:39:21 PM PDT 24
Peak memory 250332 kb
Host smart-24585dfb-f889-4566-8e49-d138a05c5312
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974504961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1974504961
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3600655804
Short name T157
Test name
Test status
Simulation time 10877611230 ps
CPU time 157.33 seconds
Started Mar 12 02:39:06 PM PDT 24
Finished Mar 12 02:41:44 PM PDT 24
Peak memory 669424 kb
Host smart-3f81e534-c2c4-4302-8f66-df8fdb7d642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600655804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3600655804
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2179745095
Short name T717
Test name
Test status
Simulation time 10686419134 ps
CPU time 159.01 seconds
Started Mar 12 02:39:08 PM PDT 24
Finished Mar 12 02:41:48 PM PDT 24
Peak memory 730912 kb
Host smart-bce7617a-d0d2-48a1-bb12-97f58779963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179745095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2179745095
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.354284393
Short name T334
Test name
Test status
Simulation time 245582524 ps
CPU time 0.81 seconds
Started Mar 12 02:39:07 PM PDT 24
Finished Mar 12 02:39:08 PM PDT 24
Peak memory 203328 kb
Host smart-cb7768d2-1be8-4419-a98a-f9687e07cf78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354284393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.354284393
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3483056438
Short name T1230
Test name
Test status
Simulation time 593795381 ps
CPU time 3.88 seconds
Started Mar 12 02:39:11 PM PDT 24
Finished Mar 12 02:39:15 PM PDT 24
Peak memory 228172 kb
Host smart-40b0cb37-c38c-49f5-b0dc-4eb17bf3b37f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483056438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3483056438
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.202115747
Short name T1212
Test name
Test status
Simulation time 21174652169 ps
CPU time 93.39 seconds
Started Mar 12 02:39:07 PM PDT 24
Finished Mar 12 02:40:41 PM PDT 24
Peak memory 1153152 kb
Host smart-85cd2195-c269-4179-9303-ae2876bb5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202115747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.202115747
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1498753763
Short name T420
Test name
Test status
Simulation time 5139747160 ps
CPU time 152.32 seconds
Started Mar 12 02:39:16 PM PDT 24
Finished Mar 12 02:41:50 PM PDT 24
Peak memory 274316 kb
Host smart-607fefd3-f88a-4b98-b229-ca0af60be943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498753763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1498753763
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3567367002
Short name T435
Test name
Test status
Simulation time 95664622 ps
CPU time 0.65 seconds
Started Mar 12 02:39:06 PM PDT 24
Finished Mar 12 02:39:07 PM PDT 24
Peak memory 202568 kb
Host smart-abab6f4f-251f-4ef9-bf8b-ceba1a0e3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567367002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3567367002
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.119437674
Short name T674
Test name
Test status
Simulation time 26022777776 ps
CPU time 139.78 seconds
Started Mar 12 02:39:12 PM PDT 24
Finished Mar 12 02:41:32 PM PDT 24
Peak memory 203548 kb
Host smart-cd4af2ef-8d7f-4212-a0fc-eb85a9282a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119437674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.119437674
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2479603491
Short name T110
Test name
Test status
Simulation time 6644540063 ps
CPU time 95.8 seconds
Started Mar 12 02:39:01 PM PDT 24
Finished Mar 12 02:40:37 PM PDT 24
Peak memory 250260 kb
Host smart-e00871dd-490c-4d83-8370-e8db041b125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479603491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2479603491
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3602498787
Short name T721
Test name
Test status
Simulation time 30131620775 ps
CPU time 513.48 seconds
Started Mar 12 02:39:06 PM PDT 24
Finished Mar 12 02:47:40 PM PDT 24
Peak memory 2163392 kb
Host smart-0d9d90e4-c22a-4dc6-b427-fdfd733644d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602498787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3602498787
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2906779607
Short name T1185
Test name
Test status
Simulation time 2714847363 ps
CPU time 21.69 seconds
Started Mar 12 02:39:09 PM PDT 24
Finished Mar 12 02:39:31 PM PDT 24
Peak memory 211800 kb
Host smart-09fa4330-ae8d-4ef4-a881-d0e1a647341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906779607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2906779607
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3895020127
Short name T820
Test name
Test status
Simulation time 6898423565 ps
CPU time 3.51 seconds
Started Mar 12 02:39:16 PM PDT 24
Finished Mar 12 02:39:20 PM PDT 24
Peak memory 203608 kb
Host smart-7e4dd754-c69c-46f7-822b-27b207f745b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895020127 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3895020127
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1648316038
Short name T571
Test name
Test status
Simulation time 10329776847 ps
CPU time 12.01 seconds
Started Mar 12 02:39:13 PM PDT 24
Finished Mar 12 02:39:26 PM PDT 24
Peak memory 264492 kb
Host smart-962e7f01-3304-44ae-b9f1-3f688fa41aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648316038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1648316038
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3623357218
Short name T596
Test name
Test status
Simulation time 10203796646 ps
CPU time 33.39 seconds
Started Mar 12 02:39:13 PM PDT 24
Finished Mar 12 02:39:47 PM PDT 24
Peak memory 442976 kb
Host smart-e0debafb-096d-4d02-961e-c3d54dd34bc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623357218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3623357218
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2625252461
Short name T605
Test name
Test status
Simulation time 683366868 ps
CPU time 2.27 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:39:20 PM PDT 24
Peak memory 203616 kb
Host smart-d8c7a136-fd0e-4ec7-b439-262de924dfd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625252461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2625252461
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2586798350
Short name T419
Test name
Test status
Simulation time 764468663 ps
CPU time 3.42 seconds
Started Mar 12 02:39:14 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 203540 kb
Host smart-aab48b8c-2afc-49ba-993b-18a12cce8912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586798350 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2586798350
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.838979713
Short name T272
Test name
Test status
Simulation time 8457101681 ps
CPU time 11.51 seconds
Started Mar 12 02:39:11 PM PDT 24
Finished Mar 12 02:39:22 PM PDT 24
Peak memory 246696 kb
Host smart-8ab15dd5-a006-44d9-a3f0-fe32ad6e38aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838979713 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.838979713
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.3851292428
Short name T326
Test name
Test status
Simulation time 1897463270 ps
CPU time 3.17 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:39:21 PM PDT 24
Peak memory 203556 kb
Host smart-193f1fef-c940-45c9-8692-6b2fcd838d2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851292428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.3851292428
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.1651063328
Short name T1016
Test name
Test status
Simulation time 23138428002 ps
CPU time 24.1 seconds
Started Mar 12 02:39:18 PM PDT 24
Finished Mar 12 02:39:43 PM PDT 24
Peak memory 219920 kb
Host smart-71dce4bd-e89b-4766-a1f2-b155b5630fb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651063328 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.1651063328
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.4104419070
Short name T463
Test name
Test status
Simulation time 30641244724 ps
CPU time 200.62 seconds
Started Mar 12 02:39:12 PM PDT 24
Finished Mar 12 02:42:33 PM PDT 24
Peak memory 2716544 kb
Host smart-5e02e4dc-8b04-485b-9fe5-ad97dd533a85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104419070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.4104419070
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2412707558
Short name T793
Test name
Test status
Simulation time 9841979563 ps
CPU time 38.09 seconds
Started Mar 12 02:39:11 PM PDT 24
Finished Mar 12 02:39:49 PM PDT 24
Peak memory 680996 kb
Host smart-6ff25ac9-e86a-4cee-b80d-c8a71ac3b25c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412707558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2412707558
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.332330585
Short name T830
Test name
Test status
Simulation time 1311925524 ps
CPU time 5.86 seconds
Started Mar 12 02:39:07 PM PDT 24
Finished Mar 12 02:39:13 PM PDT 24
Peak memory 203400 kb
Host smart-6ae1c6ea-de2e-4727-aff6-be7d859b131e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332330585 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.332330585
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.1274312376
Short name T537
Test name
Test status
Simulation time 1861735974 ps
CPU time 5.02 seconds
Started Mar 12 02:39:14 PM PDT 24
Finished Mar 12 02:39:20 PM PDT 24
Peak memory 207120 kb
Host smart-68de006c-93b6-47ee-ab54-cf089fbaeb1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274312376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.1274312376
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1034199450
Short name T1225
Test name
Test status
Simulation time 15574767 ps
CPU time 0.63 seconds
Started Mar 12 02:33:12 PM PDT 24
Finished Mar 12 02:33:13 PM PDT 24
Peak memory 202372 kb
Host smart-5bf7c081-8cec-49f2-8510-df806a2e48d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034199450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1034199450
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1379511456
Short name T661
Test name
Test status
Simulation time 222316232 ps
CPU time 1.96 seconds
Started Mar 12 02:33:06 PM PDT 24
Finished Mar 12 02:33:08 PM PDT 24
Peak memory 211732 kb
Host smart-3d1f6e22-6d2d-49ad-bac2-c3a4fea9a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379511456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1379511456
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.4066634662
Short name T1144
Test name
Test status
Simulation time 353075731 ps
CPU time 3.46 seconds
Started Mar 12 02:33:13 PM PDT 24
Finished Mar 12 02:33:17 PM PDT 24
Peak memory 210656 kb
Host smart-9e88a698-dd2c-4a73-b574-ed885b844b65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066634662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.4066634662
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1040396884
Short name T994
Test name
Test status
Simulation time 2370390248 ps
CPU time 162.81 seconds
Started Mar 12 02:33:13 PM PDT 24
Finished Mar 12 02:35:56 PM PDT 24
Peak memory 768048 kb
Host smart-fcbda497-273a-4c2f-9671-22f8e2eee5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040396884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1040396884
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1359104709
Short name T953
Test name
Test status
Simulation time 26366086099 ps
CPU time 154.03 seconds
Started Mar 12 02:33:12 PM PDT 24
Finished Mar 12 02:35:46 PM PDT 24
Peak memory 689004 kb
Host smart-86da30be-646d-4bc4-85fd-f6076e06e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359104709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1359104709
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3618645364
Short name T232
Test name
Test status
Simulation time 104478231 ps
CPU time 0.88 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:15 PM PDT 24
Peak memory 203340 kb
Host smart-56c023a2-be4d-4f8b-a17f-0f01fc4e780e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618645364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3618645364
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2608272664
Short name T914
Test name
Test status
Simulation time 426041751 ps
CPU time 6.3 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:21 PM PDT 24
Peak memory 246172 kb
Host smart-8ce3b5df-050a-4f23-ad88-5c5c0d4de1da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608272664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2608272664
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2618770111
Short name T696
Test name
Test status
Simulation time 17188893295 ps
CPU time 187.32 seconds
Started Mar 12 02:33:13 PM PDT 24
Finished Mar 12 02:36:21 PM PDT 24
Peak memory 852944 kb
Host smart-b16b569f-3149-4e4e-a2ec-52872cd9a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618770111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2618770111
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1352026433
Short name T480
Test name
Test status
Simulation time 5246889454 ps
CPU time 82.97 seconds
Started Mar 12 02:33:12 PM PDT 24
Finished Mar 12 02:34:36 PM PDT 24
Peak memory 314080 kb
Host smart-27015d47-496f-43bd-be0f-9ec1cc9bf497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352026433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1352026433
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.356501427
Short name T587
Test name
Test status
Simulation time 17144774 ps
CPU time 0.64 seconds
Started Mar 12 02:32:57 PM PDT 24
Finished Mar 12 02:32:58 PM PDT 24
Peak memory 202552 kb
Host smart-d84b2af7-1937-4e1b-ac48-66f503fa2298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356501427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.356501427
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2240874152
Short name T609
Test name
Test status
Simulation time 6459114744 ps
CPU time 42.55 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:57 PM PDT 24
Peak memory 276064 kb
Host smart-10d7a56a-e1df-43e0-a65b-5a9cfc12c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240874152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2240874152
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3130835596
Short name T1121
Test name
Test status
Simulation time 7739192004 ps
CPU time 86.98 seconds
Started Mar 12 02:32:56 PM PDT 24
Finished Mar 12 02:34:23 PM PDT 24
Peak memory 358136 kb
Host smart-0167b4e9-e238-4c90-8e79-bc4a35b6e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130835596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3130835596
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.1904804910
Short name T874
Test name
Test status
Simulation time 39008142524 ps
CPU time 1502.98 seconds
Started Mar 12 02:33:09 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 1258036 kb
Host smart-ebc4dbcf-589c-44c4-b168-473d18d93951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904804910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.1904804910
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4060331161
Short name T565
Test name
Test status
Simulation time 2385011157 ps
CPU time 11.61 seconds
Started Mar 12 02:33:08 PM PDT 24
Finished Mar 12 02:33:20 PM PDT 24
Peak memory 211828 kb
Host smart-86801e8c-0468-4bbb-8ff6-2568adb8a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060331161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4060331161
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3806639116
Short name T83
Test name
Test status
Simulation time 290819381 ps
CPU time 0.94 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:15 PM PDT 24
Peak memory 220820 kb
Host smart-39117886-1cce-4694-9108-3f21e3092ae6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806639116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3806639116
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1457267156
Short name T538
Test name
Test status
Simulation time 10317502305 ps
CPU time 11.26 seconds
Started Mar 12 02:33:08 PM PDT 24
Finished Mar 12 02:33:20 PM PDT 24
Peak memory 273564 kb
Host smart-10d56b2c-e929-4a50-bfff-5db0c0136fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457267156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1457267156
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1238054788
Short name T258
Test name
Test status
Simulation time 10071789655 ps
CPU time 66.53 seconds
Started Mar 12 02:33:17 PM PDT 24
Finished Mar 12 02:34:24 PM PDT 24
Peak memory 611020 kb
Host smart-9a303183-9fb5-48e9-80da-2ae635bc8574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238054788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1238054788
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.100767318
Short name T1100
Test name
Test status
Simulation time 1495290889 ps
CPU time 2.1 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:16 PM PDT 24
Peak memory 203568 kb
Host smart-fc5c76f0-3c8b-41f8-8dc1-d29551270fb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100767318 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.100767318
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.890340481
Short name T646
Test name
Test status
Simulation time 8154339273 ps
CPU time 11.47 seconds
Started Mar 12 02:33:09 PM PDT 24
Finished Mar 12 02:33:20 PM PDT 24
Peak memory 249604 kb
Host smart-f2f7647a-8c36-48e1-b11e-018dfe27ac80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890340481 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.890340481
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.563825582
Short name T1044
Test name
Test status
Simulation time 586475714 ps
CPU time 3.62 seconds
Started Mar 12 02:33:14 PM PDT 24
Finished Mar 12 02:33:17 PM PDT 24
Peak memory 203780 kb
Host smart-7a8f9b49-bbff-4aa6-b61b-83f5b4bb192e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563825582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_perf.563825582
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1591602875
Short name T20
Test name
Test status
Simulation time 3057525433 ps
CPU time 7.48 seconds
Started Mar 12 02:33:09 PM PDT 24
Finished Mar 12 02:33:17 PM PDT 24
Peak memory 214620 kb
Host smart-1af802a5-5730-4e04-9e9b-00b396c912e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591602875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1591602875
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.1061361295
Short name T1101
Test name
Test status
Simulation time 3212325599 ps
CPU time 6.22 seconds
Started Mar 12 02:33:07 PM PDT 24
Finished Mar 12 02:33:13 PM PDT 24
Peak memory 203648 kb
Host smart-f0f2c416-d01f-464b-b516-18481712c2e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061361295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.1061361295
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3723892453
Short name T92
Test name
Test status
Simulation time 23274812 ps
CPU time 0.59 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:39:30 PM PDT 24
Peak memory 202328 kb
Host smart-cb28e70e-4144-4d73-a570-35259df6247a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723892453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3723892453
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1115424259
Short name T196
Test name
Test status
Simulation time 413593283 ps
CPU time 1.49 seconds
Started Mar 12 02:39:16 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 211768 kb
Host smart-ee2e509a-5417-4729-8578-8f07b3977966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115424259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1115424259
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1090694721
Short name T1149
Test name
Test status
Simulation time 295333639 ps
CPU time 15.43 seconds
Started Mar 12 02:39:16 PM PDT 24
Finished Mar 12 02:39:33 PM PDT 24
Peak memory 258764 kb
Host smart-b79b003e-5a09-4dce-a4d9-737b77f8ed78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090694721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1090694721
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1419898380
Short name T805
Test name
Test status
Simulation time 6921676978 ps
CPU time 128.2 seconds
Started Mar 12 02:39:15 PM PDT 24
Finished Mar 12 02:41:23 PM PDT 24
Peak memory 651908 kb
Host smart-bc63e729-76b8-483d-a519-1c48aa2daeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419898380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1419898380
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3110354761
Short name T549
Test name
Test status
Simulation time 16414851559 ps
CPU time 153.96 seconds
Started Mar 12 02:39:18 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 693780 kb
Host smart-002971eb-c324-4e1e-ac9c-05644e0dda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110354761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3110354761
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.558195861
Short name T1055
Test name
Test status
Simulation time 318263864 ps
CPU time 1 seconds
Started Mar 12 02:39:12 PM PDT 24
Finished Mar 12 02:39:13 PM PDT 24
Peak memory 203516 kb
Host smart-a035ed36-d0f6-43f2-a486-efd4db4dfa45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558195861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.558195861
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1954692897
Short name T293
Test name
Test status
Simulation time 264723583 ps
CPU time 7.71 seconds
Started Mar 12 02:39:13 PM PDT 24
Finished Mar 12 02:39:20 PM PDT 24
Peak memory 225744 kb
Host smart-c1f5dd4a-0097-424f-a46d-9bb8c0863927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954692897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1954692897
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1560125766
Short name T100
Test name
Test status
Simulation time 3655671233 ps
CPU time 81.8 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:40:40 PM PDT 24
Peak memory 1029408 kb
Host smart-1bfc12fe-c8ba-4742-a1d2-7fc28dbe3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560125766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1560125766
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3622118509
Short name T1182
Test name
Test status
Simulation time 2350397138 ps
CPU time 35.13 seconds
Started Mar 12 02:39:23 PM PDT 24
Finished Mar 12 02:39:58 PM PDT 24
Peak memory 276940 kb
Host smart-1c755719-596e-43eb-a08a-5905464596f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622118509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3622118509
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1092704788
Short name T1001
Test name
Test status
Simulation time 16743790 ps
CPU time 0.69 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:39:18 PM PDT 24
Peak memory 202496 kb
Host smart-8348963f-efca-411d-9e26-ca3bac2823ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092704788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1092704788
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.4043424260
Short name T176
Test name
Test status
Simulation time 15856901689 ps
CPU time 100.81 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:40:58 PM PDT 24
Peak memory 269872 kb
Host smart-9c849e65-de62-4319-ab29-1280316564f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043424260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.4043424260
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3681473016
Short name T418
Test name
Test status
Simulation time 1407467949 ps
CPU time 71.28 seconds
Started Mar 12 02:39:17 PM PDT 24
Finished Mar 12 02:40:29 PM PDT 24
Peak memory 231032 kb
Host smart-535f15ce-09d6-4f20-ae75-febd03f7355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681473016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3681473016
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.228171214
Short name T651
Test name
Test status
Simulation time 915436538 ps
CPU time 14.53 seconds
Started Mar 12 02:39:13 PM PDT 24
Finished Mar 12 02:39:28 PM PDT 24
Peak memory 219776 kb
Host smart-fabb7c68-740a-4587-8049-32895c91dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228171214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.228171214
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2399467646
Short name T597
Test name
Test status
Simulation time 992137947 ps
CPU time 2.47 seconds
Started Mar 12 02:39:21 PM PDT 24
Finished Mar 12 02:39:24 PM PDT 24
Peak memory 203640 kb
Host smart-7f647dc8-de2f-49d2-ac15-eaf78496574e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399467646 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2399467646
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2219114151
Short name T1233
Test name
Test status
Simulation time 10116599247 ps
CPU time 17.28 seconds
Started Mar 12 02:39:25 PM PDT 24
Finished Mar 12 02:39:42 PM PDT 24
Peak memory 322928 kb
Host smart-93d3716a-95fe-46ba-af2f-7e6ca99e42f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219114151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2219114151
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.197510940
Short name T1021
Test name
Test status
Simulation time 10093158740 ps
CPU time 74.24 seconds
Started Mar 12 02:39:23 PM PDT 24
Finished Mar 12 02:40:37 PM PDT 24
Peak memory 659672 kb
Host smart-4a7661a6-9d1d-4e33-8d52-702509595249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197510940 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.197510940
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.156477753
Short name T812
Test name
Test status
Simulation time 1511643559 ps
CPU time 2 seconds
Started Mar 12 02:39:21 PM PDT 24
Finished Mar 12 02:39:24 PM PDT 24
Peak memory 203564 kb
Host smart-d696b6ca-eb49-4795-8d01-dd54b36b15e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156477753 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.156477753
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.979012959
Short name T698
Test name
Test status
Simulation time 17514942030 ps
CPU time 5.59 seconds
Started Mar 12 02:39:23 PM PDT 24
Finished Mar 12 02:39:29 PM PDT 24
Peak memory 211128 kb
Host smart-e5e5fb68-6642-42d9-97aa-0a75db223c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979012959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.979012959
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.642298461
Short name T760
Test name
Test status
Simulation time 22004816243 ps
CPU time 420.95 seconds
Started Mar 12 02:39:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 3848124 kb
Host smart-ac3b2a36-b127-473f-90ff-b27ad4e7fc4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642298461 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.642298461
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3677349326
Short name T114
Test name
Test status
Simulation time 828642993 ps
CPU time 4.95 seconds
Started Mar 12 02:39:24 PM PDT 24
Finished Mar 12 02:39:29 PM PDT 24
Peak memory 203592 kb
Host smart-8e681a32-6820-4810-945e-b36d30069d8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677349326 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3677349326
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.642714541
Short name T8
Test name
Test status
Simulation time 435426378 ps
CPU time 6.33 seconds
Started Mar 12 02:39:23 PM PDT 24
Finished Mar 12 02:39:30 PM PDT 24
Peak memory 203636 kb
Host smart-4655d75e-4aa8-43b8-926f-5e21ff7c41e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642714541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.642714541
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2093884833
Short name T374
Test name
Test status
Simulation time 15724658232 ps
CPU time 5.78 seconds
Started Mar 12 02:39:21 PM PDT 24
Finished Mar 12 02:39:27 PM PDT 24
Peak memory 203620 kb
Host smart-faaba093-c88c-4d3f-830c-837a75457bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093884833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2093884833
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1315055572
Short name T907
Test name
Test status
Simulation time 30760038055 ps
CPU time 604.68 seconds
Started Mar 12 02:39:26 PM PDT 24
Finished Mar 12 02:49:32 PM PDT 24
Peak memory 1702148 kb
Host smart-1284b262-b0f4-4269-8004-2e86635bcea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315055572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1315055572
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3895834797
Short name T1252
Test name
Test status
Simulation time 1573428136 ps
CPU time 7.37 seconds
Started Mar 12 02:39:22 PM PDT 24
Finished Mar 12 02:39:30 PM PDT 24
Peak memory 212900 kb
Host smart-93ff700d-7e1d-4ed0-9e09-0aea3f6983a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895834797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3895834797
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.1019430195
Short name T714
Test name
Test status
Simulation time 5566375509 ps
CPU time 7 seconds
Started Mar 12 02:39:21 PM PDT 24
Finished Mar 12 02:39:29 PM PDT 24
Peak memory 209044 kb
Host smart-5cc55fe8-6b80-424b-83a5-4ee3849402d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019430195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.1019430195
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.458041602
Short name T1154
Test name
Test status
Simulation time 17324608 ps
CPU time 0.64 seconds
Started Mar 12 02:39:37 PM PDT 24
Finished Mar 12 02:39:38 PM PDT 24
Peak memory 202268 kb
Host smart-5d5dfd4a-4345-4ea3-8466-74facfb4bece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458041602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.458041602
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2037633937
Short name T876
Test name
Test status
Simulation time 71133911 ps
CPU time 1.21 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:39:31 PM PDT 24
Peak memory 211688 kb
Host smart-0acd947d-6517-417c-9e73-0f7edbffe2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037633937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2037633937
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3116491911
Short name T946
Test name
Test status
Simulation time 244120313 ps
CPU time 5.64 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:39:34 PM PDT 24
Peak memory 251592 kb
Host smart-9e4f98ed-4208-493e-8317-b22cfb89e431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116491911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3116491911
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3861913840
Short name T712
Test name
Test status
Simulation time 6944167713 ps
CPU time 134.9 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:41:44 PM PDT 24
Peak memory 1069728 kb
Host smart-45b4ef36-91ed-4411-a8ab-e50cc0a3f6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861913840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3861913840
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1894150486
Short name T388
Test name
Test status
Simulation time 6032535367 ps
CPU time 101.19 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 02:41:12 PM PDT 24
Peak memory 564360 kb
Host smart-08a8d1c6-6900-4870-995a-5ae3e86f2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894150486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1894150486
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1382676112
Short name T1089
Test name
Test status
Simulation time 411478940 ps
CPU time 0.79 seconds
Started Mar 12 02:39:32 PM PDT 24
Finished Mar 12 02:39:33 PM PDT 24
Peak memory 203320 kb
Host smart-0020845b-2661-45c8-ad82-33f082a9b6c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382676112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1382676112
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1440694286
Short name T1130
Test name
Test status
Simulation time 158914225 ps
CPU time 4.55 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:39:35 PM PDT 24
Peak memory 229168 kb
Host smart-846235e4-a3d0-4468-a6d7-70c83485e216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440694286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1440694286
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.156778017
Short name T149
Test name
Test status
Simulation time 16984714955 ps
CPU time 122.91 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:41:33 PM PDT 24
Peak memory 1303172 kb
Host smart-fb7fa66a-8d86-4b7d-a8ef-fc48733a0474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156778017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.156778017
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1213839100
Short name T1217
Test name
Test status
Simulation time 1518627621 ps
CPU time 25.8 seconds
Started Mar 12 02:39:37 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 230240 kb
Host smart-eb25a923-1918-4a84-a287-33686616db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213839100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1213839100
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2158446543
Short name T299
Test name
Test status
Simulation time 17816776 ps
CPU time 0.61 seconds
Started Mar 12 02:39:32 PM PDT 24
Finished Mar 12 02:39:33 PM PDT 24
Peak memory 202584 kb
Host smart-d61e13d3-565d-4ea5-97f9-df23842c4583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158446543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2158446543
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3583797706
Short name T189
Test name
Test status
Simulation time 3551868972 ps
CPU time 12.84 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 02:39:44 PM PDT 24
Peak memory 215980 kb
Host smart-eeca43a8-43a2-4f11-b4bf-1997184a2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583797706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3583797706
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3841710999
Short name T749
Test name
Test status
Simulation time 2828092159 ps
CPU time 69.59 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:40:40 PM PDT 24
Peak memory 302628 kb
Host smart-8dd4708c-a6f3-40f2-b748-6ff9de50338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841710999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3841710999
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2177092783
Short name T153
Test name
Test status
Simulation time 14502221661 ps
CPU time 857.46 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:53:48 PM PDT 24
Peak memory 1171888 kb
Host smart-2e9f4332-c96f-4aa6-8ffb-937d0cc2d87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177092783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2177092783
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.4146049693
Short name T530
Test name
Test status
Simulation time 417671227 ps
CPU time 7.33 seconds
Started Mar 12 02:39:30 PM PDT 24
Finished Mar 12 02:39:37 PM PDT 24
Peak memory 211836 kb
Host smart-8b7a05af-2a53-4f7a-8dc0-fd561198a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146049693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4146049693
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1790018992
Short name T761
Test name
Test status
Simulation time 4161048096 ps
CPU time 4.94 seconds
Started Mar 12 02:39:32 PM PDT 24
Finished Mar 12 02:39:37 PM PDT 24
Peak memory 203592 kb
Host smart-4bd6ddbc-2010-414d-a693-6db4a0789896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790018992 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1790018992
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2776628291
Short name T612
Test name
Test status
Simulation time 10048987584 ps
CPU time 74.17 seconds
Started Mar 12 02:39:28 PM PDT 24
Finished Mar 12 02:40:43 PM PDT 24
Peak memory 731372 kb
Host smart-4beb1ff3-5b70-44f3-bd28-9c4ebf4372da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776628291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2776628291
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1900446696
Short name T566
Test name
Test status
Simulation time 814343320 ps
CPU time 2.08 seconds
Started Mar 12 02:39:37 PM PDT 24
Finished Mar 12 02:39:39 PM PDT 24
Peak memory 203568 kb
Host smart-8f2ec5a0-6409-482c-bcda-a9e13d712f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900446696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1900446696
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1470676767
Short name T710
Test name
Test status
Simulation time 6214986782 ps
CPU time 5.06 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:39:34 PM PDT 24
Peak memory 207564 kb
Host smart-2b6f7baa-de11-49ef-87c0-b05b9fc83984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470676767 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1470676767
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2749120448
Short name T1243
Test name
Test status
Simulation time 3617046975 ps
CPU time 4.5 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 02:39:36 PM PDT 24
Peak memory 203672 kb
Host smart-4113b00d-1548-4e31-8f61-e1890189add8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749120448 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2749120448
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.2908473801
Short name T845
Test name
Test status
Simulation time 815518986 ps
CPU time 4.7 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:39:34 PM PDT 24
Peak memory 203604 kb
Host smart-e6b52d2c-c1fd-4c8b-bec8-2168bea61f9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908473801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.2908473801
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.4283934984
Short name T716
Test name
Test status
Simulation time 24790231604 ps
CPU time 58.5 seconds
Started Mar 12 02:39:29 PM PDT 24
Finished Mar 12 02:40:28 PM PDT 24
Peak memory 519088 kb
Host smart-da14dd01-cabb-471c-8141-7c4a76b75970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283934984 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.4283934984
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1918980880
Short name T192
Test name
Test status
Simulation time 22859310103 ps
CPU time 1398.93 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 03:02:50 PM PDT 24
Peak memory 2754776 kb
Host smart-c833468d-7ebc-498f-98f7-a62773b2a4ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918980880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1918980880
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.2806436818
Short name T1244
Test name
Test status
Simulation time 1514941989 ps
CPU time 8.48 seconds
Started Mar 12 02:39:31 PM PDT 24
Finished Mar 12 02:39:40 PM PDT 24
Peak memory 203532 kb
Host smart-32608ea2-df25-43de-9c4f-e75d09826cf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806436818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.2806436818
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3858966742
Short name T585
Test name
Test status
Simulation time 31009611 ps
CPU time 0.59 seconds
Started Mar 12 02:39:55 PM PDT 24
Finished Mar 12 02:39:56 PM PDT 24
Peak memory 203340 kb
Host smart-0a531d2b-c1c1-46a9-be35-5ad75acca52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858966742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3858966742
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1182327908
Short name T833
Test name
Test status
Simulation time 67497361 ps
CPU time 1.25 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 02:39:39 PM PDT 24
Peak memory 211668 kb
Host smart-3f83bf4b-3cf1-4ed3-b4ba-e58307dfd5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182327908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1182327908
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2770638621
Short name T576
Test name
Test status
Simulation time 258821706 ps
CPU time 5.37 seconds
Started Mar 12 02:39:35 PM PDT 24
Finished Mar 12 02:39:41 PM PDT 24
Peak memory 251972 kb
Host smart-6e00481c-adab-499a-97a1-4648411012a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770638621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2770638621
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4013708608
Short name T203
Test name
Test status
Simulation time 1836592369 ps
CPU time 57.28 seconds
Started Mar 12 02:39:35 PM PDT 24
Finished Mar 12 02:40:32 PM PDT 24
Peak memory 609548 kb
Host smart-7a62940b-45e4-42d3-a637-d6e281cc3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013708608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4013708608
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3794935647
Short name T1198
Test name
Test status
Simulation time 2636107618 ps
CPU time 191.92 seconds
Started Mar 12 02:39:37 PM PDT 24
Finished Mar 12 02:42:49 PM PDT 24
Peak memory 791352 kb
Host smart-e5313bf0-91a2-427a-88d8-c69ff5e00820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794935647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3794935647
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2669466712
Short name T1267
Test name
Test status
Simulation time 178623312 ps
CPU time 9.01 seconds
Started Mar 12 02:39:36 PM PDT 24
Finished Mar 12 02:39:45 PM PDT 24
Peak memory 203576 kb
Host smart-9625374d-6f0f-4544-93f3-b440bcc1eb4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669466712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2669466712
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.782433415
Short name T1078
Test name
Test status
Simulation time 14818725516 ps
CPU time 508.9 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 02:48:07 PM PDT 24
Peak memory 1670820 kb
Host smart-efcb65c3-13c1-451e-84bb-c05baef6e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782433415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.782433415
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3659734554
Short name T1041
Test name
Test status
Simulation time 2075802333 ps
CPU time 55.62 seconds
Started Mar 12 02:39:56 PM PDT 24
Finished Mar 12 02:40:52 PM PDT 24
Peak memory 273960 kb
Host smart-f26a8eca-c5d3-4fb4-8b91-e7ef61eb5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659734554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3659734554
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3215857801
Short name T1043
Test name
Test status
Simulation time 20879580 ps
CPU time 0.63 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 02:39:39 PM PDT 24
Peak memory 203040 kb
Host smart-be893b3f-9949-479d-a956-9e32d8ea7c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215857801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3215857801
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3720453605
Short name T1035
Test name
Test status
Simulation time 6079835668 ps
CPU time 87.45 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 265228 kb
Host smart-61d9ce7c-fa1c-4004-b955-3ac404ebea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720453605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3720453605
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2298063909
Short name T1017
Test name
Test status
Simulation time 5300152051 ps
CPU time 86.74 seconds
Started Mar 12 02:39:40 PM PDT 24
Finished Mar 12 02:41:07 PM PDT 24
Peak memory 257456 kb
Host smart-e4e39c12-626e-4085-9caa-c0b29127d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298063909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2298063909
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.874349116
Short name T980
Test name
Test status
Simulation time 13207987789 ps
CPU time 1381.75 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 03:02:40 PM PDT 24
Peak memory 1168000 kb
Host smart-78468b1c-d068-4519-a7d6-f5243198e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874349116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.874349116
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2496845275
Short name T13
Test name
Test status
Simulation time 4812028903 ps
CPU time 17.73 seconds
Started Mar 12 02:39:38 PM PDT 24
Finished Mar 12 02:39:55 PM PDT 24
Peak memory 219980 kb
Host smart-fbc3be8a-93ee-4ebc-82c3-4bd11e5ce4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496845275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2496845275
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.194156508
Short name T224
Test name
Test status
Simulation time 4298566090 ps
CPU time 3.38 seconds
Started Mar 12 02:39:46 PM PDT 24
Finished Mar 12 02:39:49 PM PDT 24
Peak memory 203612 kb
Host smart-b8dba0f2-8953-44bc-b2cf-56932b0d4599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194156508 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.194156508
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4043247042
Short name T1088
Test name
Test status
Simulation time 10115260392 ps
CPU time 66.33 seconds
Started Mar 12 02:39:44 PM PDT 24
Finished Mar 12 02:40:51 PM PDT 24
Peak memory 639676 kb
Host smart-6537ebcc-d484-41fb-81d5-fc99c7c77172
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043247042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.4043247042
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1832810297
Short name T317
Test name
Test status
Simulation time 10523724421 ps
CPU time 10.38 seconds
Started Mar 12 02:39:46 PM PDT 24
Finished Mar 12 02:39:56 PM PDT 24
Peak memory 294144 kb
Host smart-86fff8d3-4c7e-4eec-98bb-e7c0839ddd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832810297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1832810297
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.403439983
Short name T584
Test name
Test status
Simulation time 312405671 ps
CPU time 2.05 seconds
Started Mar 12 02:39:44 PM PDT 24
Finished Mar 12 02:39:47 PM PDT 24
Peak memory 203660 kb
Host smart-6021480f-2650-40ba-9c9a-2b9c110ef3b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403439983 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.403439983
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2855401681
Short name T508
Test name
Test status
Simulation time 6702366512 ps
CPU time 4.34 seconds
Started Mar 12 02:39:44 PM PDT 24
Finished Mar 12 02:39:48 PM PDT 24
Peak memory 204044 kb
Host smart-39ceb320-a225-461d-9d66-e001b7dfe86d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855401681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2855401681
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2078410057
Short name T575
Test name
Test status
Simulation time 14339631614 ps
CPU time 17.73 seconds
Started Mar 12 02:39:45 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 480868 kb
Host smart-8189cd9c-be9f-404b-bcc2-6b9e7173b1ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078410057 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2078410057
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.25678740
Short name T956
Test name
Test status
Simulation time 919515193 ps
CPU time 5.18 seconds
Started Mar 12 02:39:43 PM PDT 24
Finished Mar 12 02:39:48 PM PDT 24
Peak memory 213152 kb
Host smart-a4525a96-d198-4dfe-b49a-e838492d930a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25678740 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.i2c_target_perf.25678740
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2618098217
Short name T457
Test name
Test status
Simulation time 4651199649 ps
CPU time 38.37 seconds
Started Mar 12 02:39:45 PM PDT 24
Finished Mar 12 02:40:23 PM PDT 24
Peak memory 203620 kb
Host smart-e6b3dc2a-f48b-4a65-855a-61e6055f74c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618098217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2618098217
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.29019953
Short name T282
Test name
Test status
Simulation time 28920417830 ps
CPU time 24.94 seconds
Started Mar 12 02:39:46 PM PDT 24
Finished Mar 12 02:40:11 PM PDT 24
Peak memory 576428 kb
Host smart-355ab6e6-4912-4f29-b2ad-4a5505b4692e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29019953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stress_wr.29019953
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3847220609
Short name T1064
Test name
Test status
Simulation time 9124425099 ps
CPU time 7.76 seconds
Started Mar 12 02:39:45 PM PDT 24
Finished Mar 12 02:39:53 PM PDT 24
Peak memory 208252 kb
Host smart-10cb5fc0-7274-41a9-b30e-602b29d1993d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847220609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3847220609
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.3124668177
Short name T346
Test name
Test status
Simulation time 6282811200 ps
CPU time 6.21 seconds
Started Mar 12 02:39:45 PM PDT 24
Finished Mar 12 02:39:52 PM PDT 24
Peak memory 209224 kb
Host smart-12f58dbd-e048-4107-93ba-34963461054c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124668177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.3124668177
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2179164598
Short name T594
Test name
Test status
Simulation time 38064945 ps
CPU time 0.6 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:40:05 PM PDT 24
Peak memory 202372 kb
Host smart-b5e99982-19a0-45ce-9e17-2e35eb3fb0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179164598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2179164598
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2149786596
Short name T1193
Test name
Test status
Simulation time 47777202 ps
CPU time 1.3 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:39:59 PM PDT 24
Peak memory 211836 kb
Host smart-a403fe4e-6a57-4b74-b654-87289d93f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149786596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2149786596
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3733563870
Short name T1008
Test name
Test status
Simulation time 320127237 ps
CPU time 7.05 seconds
Started Mar 12 02:39:56 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 271520 kb
Host smart-9c4d0a03-1f43-4260-9564-d100cba8129f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733563870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3733563870
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3831588303
Short name T669
Test name
Test status
Simulation time 1800850571 ps
CPU time 59.2 seconds
Started Mar 12 02:39:56 PM PDT 24
Finished Mar 12 02:40:55 PM PDT 24
Peak memory 640680 kb
Host smart-1e1c7c63-9383-4fe5-aa83-562fbaf82f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831588303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3831588303
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1285519177
Short name T14
Test name
Test status
Simulation time 6742556049 ps
CPU time 38.77 seconds
Started Mar 12 02:39:55 PM PDT 24
Finished Mar 12 02:40:34 PM PDT 24
Peak memory 517320 kb
Host smart-a9dd1d2a-9631-4169-8766-5edfa283f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285519177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1285519177
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1167473896
Short name T47
Test name
Test status
Simulation time 757222685 ps
CPU time 1.13 seconds
Started Mar 12 02:39:54 PM PDT 24
Finished Mar 12 02:39:56 PM PDT 24
Peak memory 203500 kb
Host smart-913670b9-306b-490e-ac28-7cbe5f8ed9df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167473896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1167473896
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3772817139
Short name T1253
Test name
Test status
Simulation time 207118380 ps
CPU time 10.51 seconds
Started Mar 12 02:39:54 PM PDT 24
Finished Mar 12 02:40:05 PM PDT 24
Peak memory 203492 kb
Host smart-b0ab9cdc-050d-41f4-8eb0-a5d1dc3aa35b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772817139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3772817139
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.887495775
Short name T957
Test name
Test status
Simulation time 9241140321 ps
CPU time 128.96 seconds
Started Mar 12 02:39:54 PM PDT 24
Finished Mar 12 02:42:04 PM PDT 24
Peak memory 1241116 kb
Host smart-5a2cb933-0b40-4b56-89b6-ed636585ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887495775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.887495775
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.558086714
Short name T873
Test name
Test status
Simulation time 7858957906 ps
CPU time 103.81 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:41:49 PM PDT 24
Peak memory 264548 kb
Host smart-65c9fbdf-338d-4f34-a398-7aeee9b00cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558086714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.558086714
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3617942454
Short name T440
Test name
Test status
Simulation time 17676458 ps
CPU time 0.66 seconds
Started Mar 12 02:39:56 PM PDT 24
Finished Mar 12 02:39:57 PM PDT 24
Peak memory 202608 kb
Host smart-74647b5a-6bf7-4f57-ab74-48f74a5b6865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617942454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3617942454
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1222859146
Short name T257
Test name
Test status
Simulation time 23852426566 ps
CPU time 1199.69 seconds
Started Mar 12 02:39:55 PM PDT 24
Finished Mar 12 02:59:56 PM PDT 24
Peak memory 288852 kb
Host smart-d9523e52-46f4-4643-b164-705447539659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222859146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1222859146
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3100076025
Short name T754
Test name
Test status
Simulation time 4501420479 ps
CPU time 18.43 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:40:15 PM PDT 24
Peak memory 229108 kb
Host smart-ab6e9a52-28e4-454e-9449-7a443356cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100076025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3100076025
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.4173845048
Short name T722
Test name
Test status
Simulation time 514345724 ps
CPU time 22.14 seconds
Started Mar 12 02:39:58 PM PDT 24
Finished Mar 12 02:40:20 PM PDT 24
Peak memory 211788 kb
Host smart-c1ddc848-ed8e-42c6-a648-69b7d9ccf7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173845048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.4173845048
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1750950476
Short name T879
Test name
Test status
Simulation time 1256168413 ps
CPU time 5.23 seconds
Started Mar 12 02:39:56 PM PDT 24
Finished Mar 12 02:40:01 PM PDT 24
Peak memory 203628 kb
Host smart-62cd4791-4974-46a3-93b7-a3df1a461f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750950476 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1750950476
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1647611917
Short name T74
Test name
Test status
Simulation time 10053331029 ps
CPU time 63.69 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:41:01 PM PDT 24
Peak memory 526692 kb
Host smart-a8c62936-217a-4e9a-a6b3-74f04f6d19e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647611917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1647611917
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2811042455
Short name T330
Test name
Test status
Simulation time 10044033397 ps
CPU time 29.34 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:40:27 PM PDT 24
Peak memory 384348 kb
Host smart-73146e77-eba8-4c06-8579-7d4618fea11a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811042455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2811042455
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2780839080
Short name T430
Test name
Test status
Simulation time 3232838269 ps
CPU time 3.56 seconds
Started Mar 12 02:39:54 PM PDT 24
Finished Mar 12 02:39:58 PM PDT 24
Peak memory 205200 kb
Host smart-f4c5e89d-d0e1-4abc-a3b7-93d2a641bcc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780839080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2780839080
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_perf.856899222
Short name T225
Test name
Test status
Simulation time 940774565 ps
CPU time 5.39 seconds
Started Mar 12 02:39:55 PM PDT 24
Finished Mar 12 02:40:00 PM PDT 24
Peak memory 203524 kb
Host smart-eced1ce7-6a7f-4f31-870a-54fa0a708593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856899222 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_perf.856899222
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2805812301
Short name T869
Test name
Test status
Simulation time 1446563456 ps
CPU time 10.3 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:40:07 PM PDT 24
Peak memory 203608 kb
Host smart-25d46414-5e71-43ef-aa36-c6ef416e356d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805812301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2805812301
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.54877162
Short name T1249
Test name
Test status
Simulation time 37181129095 ps
CPU time 13.78 seconds
Started Mar 12 02:39:55 PM PDT 24
Finished Mar 12 02:40:09 PM PDT 24
Peak memory 382988 kb
Host smart-41abf10f-8165-489c-91fa-33569543c536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54877162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stress_wr.54877162
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.4116467662
Short name T1250
Test name
Test status
Simulation time 1527875612 ps
CPU time 6.82 seconds
Started Mar 12 02:39:57 PM PDT 24
Finished Mar 12 02:40:04 PM PDT 24
Peak memory 203580 kb
Host smart-ffd9e820-62f1-4b45-b0aa-8688a61b0b66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116467662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.4116467662
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.3345161476
Short name T403
Test name
Test status
Simulation time 4768382465 ps
CPU time 5.75 seconds
Started Mar 12 02:39:58 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 208116 kb
Host smart-862304e8-4f7b-4e13-a012-e2d36e5e6c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345161476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.3345161476
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.992362181
Short name T885
Test name
Test status
Simulation time 39001418 ps
CPU time 0.57 seconds
Started Mar 12 02:40:11 PM PDT 24
Finished Mar 12 02:40:14 PM PDT 24
Peak memory 203364 kb
Host smart-9d762b91-9eef-4aa8-98ff-e876c86b0c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992362181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.992362181
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3447177077
Short name T822
Test name
Test status
Simulation time 42457295 ps
CPU time 1.04 seconds
Started Mar 12 02:40:06 PM PDT 24
Finished Mar 12 02:40:07 PM PDT 24
Peak memory 211768 kb
Host smart-3f4cebde-8b39-488d-bc62-ff70d9c27ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447177077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3447177077
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3343217140
Short name T1234
Test name
Test status
Simulation time 428606173 ps
CPU time 7.64 seconds
Started Mar 12 02:40:03 PM PDT 24
Finished Mar 12 02:40:11 PM PDT 24
Peak memory 265768 kb
Host smart-020d93d9-2239-4ff4-b7bc-909699774420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343217140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3343217140
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1616368302
Short name T540
Test name
Test status
Simulation time 5894277299 ps
CPU time 66.84 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:41:12 PM PDT 24
Peak memory 762164 kb
Host smart-b54e88fd-7390-41ca-90c8-43cee0205061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616368302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1616368302
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.588822851
Short name T1235
Test name
Test status
Simulation time 3152345914 ps
CPU time 105.06 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:41:50 PM PDT 24
Peak memory 927596 kb
Host smart-7a97a631-734b-403d-8d01-7322db25f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588822851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.588822851
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2486035257
Short name T1242
Test name
Test status
Simulation time 653077760 ps
CPU time 1.11 seconds
Started Mar 12 02:40:02 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 203392 kb
Host smart-6ef3cd7d-d9c2-4819-8d6f-cb1daaa05255
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486035257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2486035257
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.690777908
Short name T17
Test name
Test status
Simulation time 1029627431 ps
CPU time 12.63 seconds
Started Mar 12 02:40:06 PM PDT 24
Finished Mar 12 02:40:19 PM PDT 24
Peak memory 203496 kb
Host smart-96b05b14-1705-442b-a6f2-827acd525672
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690777908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
690777908
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.729121621
Short name T941
Test name
Test status
Simulation time 15362414556 ps
CPU time 119.8 seconds
Started Mar 12 02:40:04 PM PDT 24
Finished Mar 12 02:42:04 PM PDT 24
Peak memory 1159396 kb
Host smart-6f5c53ea-7cef-4b50-b883-480a4fcdc83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729121621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.729121621
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.551078631
Short name T382
Test name
Test status
Simulation time 2042430975 ps
CPU time 145.44 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:42:39 PM PDT 24
Peak memory 285948 kb
Host smart-d7446ec7-f88e-4932-9923-a862bb6dbb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551078631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.551078631
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1973944970
Short name T161
Test name
Test status
Simulation time 20503840 ps
CPU time 0.67 seconds
Started Mar 12 02:40:03 PM PDT 24
Finished Mar 12 02:40:04 PM PDT 24
Peak memory 202532 kb
Host smart-009b0186-52eb-4b3f-ac0f-d565f5c7fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973944970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1973944970
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1333337608
Short name T968
Test name
Test status
Simulation time 6907809945 ps
CPU time 177.58 seconds
Started Mar 12 02:40:04 PM PDT 24
Finished Mar 12 02:43:02 PM PDT 24
Peak memory 329452 kb
Host smart-7a76d545-3219-4a8d-9b05-4fd3869dbec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333337608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1333337608
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1570175885
Short name T485
Test name
Test status
Simulation time 1595904623 ps
CPU time 76.03 seconds
Started Mar 12 02:40:06 PM PDT 24
Finished Mar 12 02:41:23 PM PDT 24
Peak memory 247528 kb
Host smart-fee6fb9f-269d-4d65-b2b7-be39873ca501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570175885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1570175885
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2004231029
Short name T1147
Test name
Test status
Simulation time 153565317068 ps
CPU time 2734.05 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 03:25:39 PM PDT 24
Peak memory 3087720 kb
Host smart-8667e024-4630-4a3a-b0b9-37e20bf132e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004231029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2004231029
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3580618477
Short name T278
Test name
Test status
Simulation time 2308674461 ps
CPU time 12.68 seconds
Started Mar 12 02:40:04 PM PDT 24
Finished Mar 12 02:40:17 PM PDT 24
Peak memory 219580 kb
Host smart-a1484944-e321-4fa2-bd66-6576157b4fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580618477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3580618477
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4159472081
Short name T967
Test name
Test status
Simulation time 1643457458 ps
CPU time 6.18 seconds
Started Mar 12 02:40:11 PM PDT 24
Finished Mar 12 02:40:20 PM PDT 24
Peak memory 204532 kb
Host smart-3cb3992d-900e-4d8b-a14f-fbe0ffc5e3fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159472081 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4159472081
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.803549028
Short name T921
Test name
Test status
Simulation time 10606747153 ps
CPU time 12.71 seconds
Started Mar 12 02:40:03 PM PDT 24
Finished Mar 12 02:40:17 PM PDT 24
Peak memory 304512 kb
Host smart-f649a077-57ad-46d4-9727-2977312aba30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803549028 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.803549028
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3832866528
Short name T536
Test name
Test status
Simulation time 10147680648 ps
CPU time 6.86 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:40:12 PM PDT 24
Peak memory 267040 kb
Host smart-ca20ad39-d918-4ead-b912-4b5486119117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832866528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3832866528
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3005207391
Short name T588
Test name
Test status
Simulation time 2106427912 ps
CPU time 2.84 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:40:17 PM PDT 24
Peak memory 203636 kb
Host smart-df0f5191-184c-41a3-97db-2bccda533c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005207391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3005207391
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3357144373
Short name T990
Test name
Test status
Simulation time 23004290927 ps
CPU time 7.31 seconds
Started Mar 12 02:40:06 PM PDT 24
Finished Mar 12 02:40:14 PM PDT 24
Peak memory 216712 kb
Host smart-0c3667e7-fb28-496b-8003-f6cfb92d1aec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357144373 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3357144373
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3071197162
Short name T1046
Test name
Test status
Simulation time 1902694925 ps
CPU time 5.36 seconds
Started Mar 12 02:40:15 PM PDT 24
Finished Mar 12 02:40:22 PM PDT 24
Peak memory 209704 kb
Host smart-35feb9ae-6d3d-4470-b83a-c22f7d6c64fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071197162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3071197162
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.3048561046
Short name T531
Test name
Test status
Simulation time 23883776536 ps
CPU time 390.77 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:46:44 PM PDT 24
Peak memory 3008648 kb
Host smart-59a7da39-b16f-432b-a360-5d067c6cada7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048561046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.3048561046
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3098332515
Short name T1211
Test name
Test status
Simulation time 287674806 ps
CPU time 11.76 seconds
Started Mar 12 02:40:03 PM PDT 24
Finished Mar 12 02:40:16 PM PDT 24
Peak memory 203580 kb
Host smart-d026d3b8-9fb2-4a87-811a-bc4fc7c762b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098332515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3098332515
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1717198967
Short name T708
Test name
Test status
Simulation time 61587743283 ps
CPU time 632.08 seconds
Started Mar 12 02:40:06 PM PDT 24
Finished Mar 12 02:50:38 PM PDT 24
Peak memory 5173644 kb
Host smart-ccfad0b7-6acd-42d9-a574-a12291171168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717198967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1717198967
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.459694045
Short name T666
Test name
Test status
Simulation time 3673682997 ps
CPU time 7.34 seconds
Started Mar 12 02:40:05 PM PDT 24
Finished Mar 12 02:40:12 PM PDT 24
Peak memory 203652 kb
Host smart-1575690c-b5d8-407d-9d6b-5b45eabfe973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459694045 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.459694045
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.523569826
Short name T1010
Test name
Test status
Simulation time 9413991865 ps
CPU time 5.29 seconds
Started Mar 12 02:40:07 PM PDT 24
Finished Mar 12 02:40:13 PM PDT 24
Peak memory 203644 kb
Host smart-eb0084fc-94b2-4678-bdf8-17d72d197202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523569826 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_unexp_stop.523569826
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.393417978
Short name T839
Test name
Test status
Simulation time 17288422 ps
CPU time 0.62 seconds
Started Mar 12 02:40:21 PM PDT 24
Finished Mar 12 02:40:22 PM PDT 24
Peak memory 202336 kb
Host smart-5fc9af50-4b66-4ccd-930f-822c097207b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393417978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.393417978
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2505896624
Short name T61
Test name
Test status
Simulation time 154570485 ps
CPU time 1.11 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:14 PM PDT 24
Peak memory 213752 kb
Host smart-decf764e-353b-423a-aa3a-97b5460a3052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505896624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2505896624
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.87330768
Short name T951
Test name
Test status
Simulation time 238827512 ps
CPU time 5.27 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:40:19 PM PDT 24
Peak memory 249688 kb
Host smart-daf44c66-7523-447d-afa3-1c64aacc8453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87330768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty
.87330768
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1024395881
Short name T982
Test name
Test status
Simulation time 3430470013 ps
CPU time 288.5 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:45:02 PM PDT 24
Peak memory 1056796 kb
Host smart-4ddcaf8c-c6ce-4096-b497-a420b2216322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024395881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1024395881
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.680456793
Short name T729
Test name
Test status
Simulation time 3095381737 ps
CPU time 107.89 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:42:01 PM PDT 24
Peak memory 944384 kb
Host smart-31bd4044-87ec-4319-9413-709b27169418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680456793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.680456793
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.884419211
Short name T48
Test name
Test status
Simulation time 412298779 ps
CPU time 1.06 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:40:15 PM PDT 24
Peak memory 203540 kb
Host smart-10cf6d7d-057e-4091-ba1c-f1dec45903bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884419211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.884419211
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.43163972
Short name T1215
Test name
Test status
Simulation time 326749330 ps
CPU time 3.29 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:17 PM PDT 24
Peak memory 203608 kb
Host smart-20e60887-a989-432b-a6e3-f5c3a469d09b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43163972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.43163972
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3865254015
Short name T390
Test name
Test status
Simulation time 14122262352 ps
CPU time 117.42 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:42:11 PM PDT 24
Peak memory 1157008 kb
Host smart-85773b22-7515-4715-811a-daaca58e42ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865254015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3865254015
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2592881325
Short name T726
Test name
Test status
Simulation time 11035773704 ps
CPU time 58.83 seconds
Started Mar 12 02:40:14 PM PDT 24
Finished Mar 12 02:41:13 PM PDT 24
Peak memory 263216 kb
Host smart-fd80fe18-aa76-4b7f-bf9e-a409a191c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592881325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2592881325
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.776909216
Short name T386
Test name
Test status
Simulation time 37626100 ps
CPU time 0.63 seconds
Started Mar 12 02:40:14 PM PDT 24
Finished Mar 12 02:40:15 PM PDT 24
Peak memory 203248 kb
Host smart-b5c1f534-4bc2-4efa-bc89-cf52075acc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776909216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.776909216
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3386766182
Short name T366
Test name
Test status
Simulation time 1284806289 ps
CPU time 57.77 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:41:11 PM PDT 24
Peak memory 211700 kb
Host smart-ab0c3792-a1af-467e-be56-60449935b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386766182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3386766182
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.941622084
Short name T37
Test name
Test status
Simulation time 1612672221 ps
CPU time 32.69 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:46 PM PDT 24
Peak memory 248764 kb
Host smart-9768e31f-3c29-400a-9b69-99f7002050e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941622084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.941622084
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2895187768
Short name T1224
Test name
Test status
Simulation time 3000263142 ps
CPU time 12.93 seconds
Started Mar 12 02:40:14 PM PDT 24
Finished Mar 12 02:40:27 PM PDT 24
Peak memory 219248 kb
Host smart-b887d033-a927-4919-8f9b-287d45ac3767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895187768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2895187768
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3262492810
Short name T443
Test name
Test status
Simulation time 3762862165 ps
CPU time 4.79 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:18 PM PDT 24
Peak memory 203964 kb
Host smart-f3030f0f-7382-4a44-8468-8ebc6c859369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262492810 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3262492810
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.567744677
Short name T455
Test name
Test status
Simulation time 10182208752 ps
CPU time 14.68 seconds
Started Mar 12 02:40:14 PM PDT 24
Finished Mar 12 02:40:29 PM PDT 24
Peak memory 323932 kb
Host smart-2622fb7f-0144-4288-8bd3-a1f57f4044cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567744677 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.567744677
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2259496635
Short name T880
Test name
Test status
Simulation time 4334865794 ps
CPU time 5.18 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:19 PM PDT 24
Peak memory 205028 kb
Host smart-ee5bd7ef-3994-40ec-a7ec-ffee8e9b21a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259496635 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2259496635
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.4049970889
Short name T300
Test name
Test status
Simulation time 9230878497 ps
CPU time 4.57 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:40:18 PM PDT 24
Peak memory 203504 kb
Host smart-d1e639a3-0014-4d17-b2fe-604770277eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049970889 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4049970889
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.2108226426
Short name T884
Test name
Test status
Simulation time 1855640075 ps
CPU time 2.9 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:16 PM PDT 24
Peak memory 203540 kb
Host smart-0ade4853-c9f3-46ff-90d6-1a76c7927492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108226426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.2108226426
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3896079675
Short name T392
Test name
Test status
Simulation time 1477183652 ps
CPU time 31.24 seconds
Started Mar 12 02:40:12 PM PDT 24
Finished Mar 12 02:40:45 PM PDT 24
Peak memory 203588 kb
Host smart-01d93f49-91fc-4de3-8bef-d2938c6e43a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896079675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3896079675
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2664859418
Short name T786
Test name
Test status
Simulation time 9947271640 ps
CPU time 99.42 seconds
Started Mar 12 02:40:13 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 556924 kb
Host smart-c2fbeeee-0ae1-49fa-bbb7-f596b2bcaf07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664859418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2664859418
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2785430369
Short name T351
Test name
Test status
Simulation time 1865796120 ps
CPU time 6.99 seconds
Started Mar 12 02:40:15 PM PDT 24
Finished Mar 12 02:40:23 PM PDT 24
Peak memory 203632 kb
Host smart-5402758d-7cd0-419a-9a25-019211df882e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785430369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2785430369
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.335619453
Short name T271
Test name
Test status
Simulation time 4621055977 ps
CPU time 6.48 seconds
Started Mar 12 02:40:19 PM PDT 24
Finished Mar 12 02:40:26 PM PDT 24
Peak memory 207572 kb
Host smart-d1b3c47b-505b-4b38-92ff-715ddfa697ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335619453 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_unexp_stop.335619453
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3883309738
Short name T312
Test name
Test status
Simulation time 41028413 ps
CPU time 0.6 seconds
Started Mar 12 02:40:31 PM PDT 24
Finished Mar 12 02:40:33 PM PDT 24
Peak memory 202340 kb
Host smart-45e327b9-da4d-4c2c-abc8-438fd65eec9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883309738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3883309738
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3836251606
Short name T427
Test name
Test status
Simulation time 172904920 ps
CPU time 1.46 seconds
Started Mar 12 02:40:25 PM PDT 24
Finished Mar 12 02:40:29 PM PDT 24
Peak memory 211716 kb
Host smart-dfa5314f-ec59-43e8-a5ad-6d2718f6574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836251606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3836251606
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2926654421
Short name T586
Test name
Test status
Simulation time 345055428 ps
CPU time 5.86 seconds
Started Mar 12 02:40:22 PM PDT 24
Finished Mar 12 02:40:28 PM PDT 24
Peak memory 274028 kb
Host smart-31121eab-40b7-4fdb-bdd6-e72cf907a7ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926654421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2926654421
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2294734963
Short name T547
Test name
Test status
Simulation time 5570219213 ps
CPU time 209.34 seconds
Started Mar 12 02:40:21 PM PDT 24
Finished Mar 12 02:43:51 PM PDT 24
Peak memory 869620 kb
Host smart-60ed8765-9c15-4ab6-a70b-45da9a38d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294734963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2294734963
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3171994794
Short name T461
Test name
Test status
Simulation time 7904591509 ps
CPU time 68.85 seconds
Started Mar 12 02:40:25 PM PDT 24
Finished Mar 12 02:41:35 PM PDT 24
Peak memory 696424 kb
Host smart-6f5992af-40d3-4be7-929c-6f4ad46b6948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171994794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3171994794
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.364240200
Short name T342
Test name
Test status
Simulation time 93591771 ps
CPU time 0.84 seconds
Started Mar 12 02:40:21 PM PDT 24
Finished Mar 12 02:40:22 PM PDT 24
Peak memory 203288 kb
Host smart-1efb0a22-2c42-4c30-b806-efdcb3f2db8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364240200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.364240200
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3126657410
Short name T106
Test name
Test status
Simulation time 420011583 ps
CPU time 5.55 seconds
Started Mar 12 02:40:20 PM PDT 24
Finished Mar 12 02:40:25 PM PDT 24
Peak memory 244016 kb
Host smart-7fbcdac8-cdc8-4ef6-9319-4996a8f2776d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126657410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3126657410
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2008677803
Short name T1214
Test name
Test status
Simulation time 4109352928 ps
CPU time 118.24 seconds
Started Mar 12 02:40:27 PM PDT 24
Finished Mar 12 02:42:26 PM PDT 24
Peak memory 1174216 kb
Host smart-8e4801be-ad87-4150-b50a-c3eaa0ed2265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008677803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2008677803
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2465720388
Short name T261
Test name
Test status
Simulation time 5980421380 ps
CPU time 78.2 seconds
Started Mar 12 02:40:32 PM PDT 24
Finished Mar 12 02:41:50 PM PDT 24
Peak memory 234548 kb
Host smart-76a313b3-a7cb-41fa-9dda-9ae54951d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465720388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2465720388
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3529531598
Short name T817
Test name
Test status
Simulation time 44789632 ps
CPU time 0.62 seconds
Started Mar 12 02:40:24 PM PDT 24
Finished Mar 12 02:40:24 PM PDT 24
Peak memory 202416 kb
Host smart-6083fc5a-eaf9-4cd7-a179-978cba44a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529531598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3529531598
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.177167810
Short name T904
Test name
Test status
Simulation time 29847392022 ps
CPU time 138.02 seconds
Started Mar 12 02:40:27 PM PDT 24
Finished Mar 12 02:42:46 PM PDT 24
Peak memory 219620 kb
Host smart-6b166a80-2d12-422c-812c-dc9e9a95f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177167810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.177167810
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1192216742
Short name T1183
Test name
Test status
Simulation time 4034199344 ps
CPU time 100.46 seconds
Started Mar 12 02:40:26 PM PDT 24
Finished Mar 12 02:42:08 PM PDT 24
Peak memory 219912 kb
Host smart-c7efbf34-c30b-4e58-9e33-0032b51818c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192216742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1192216742
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2546240720
Short name T711
Test name
Test status
Simulation time 2314191444 ps
CPU time 11.75 seconds
Started Mar 12 02:40:26 PM PDT 24
Finished Mar 12 02:40:39 PM PDT 24
Peak memory 219080 kb
Host smart-5a296005-8ff2-403b-9a7e-b7c545bfd8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546240720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2546240720
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.78879716
Short name T861
Test name
Test status
Simulation time 572762942 ps
CPU time 2.98 seconds
Started Mar 12 02:40:32 PM PDT 24
Finished Mar 12 02:40:35 PM PDT 24
Peak memory 203488 kb
Host smart-8151949b-5231-44fc-abc2-37c74ad1c66f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78879716 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_bad_addr.78879716
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2762955205
Short name T1108
Test name
Test status
Simulation time 10946926142 ps
CPU time 3.85 seconds
Started Mar 12 02:40:27 PM PDT 24
Finished Mar 12 02:40:31 PM PDT 24
Peak memory 211692 kb
Host smart-7a52e207-04fc-427d-9121-07e9cde3bfbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762955205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2762955205
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2349720151
Short name T613
Test name
Test status
Simulation time 10086234331 ps
CPU time 93.4 seconds
Started Mar 12 02:40:25 PM PDT 24
Finished Mar 12 02:42:00 PM PDT 24
Peak memory 662396 kb
Host smart-513ff60f-5105-4c44-a788-15670b779f9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349720151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2349720151
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2932440109
Short name T1240
Test name
Test status
Simulation time 4376181498 ps
CPU time 5.4 seconds
Started Mar 12 02:40:21 PM PDT 24
Finished Mar 12 02:40:27 PM PDT 24
Peak memory 208004 kb
Host smart-543e83b5-febf-40e0-9a6c-79d7f6fb7d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932440109 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2932440109
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.430203993
Short name T336
Test name
Test status
Simulation time 2508938076 ps
CPU time 5.23 seconds
Started Mar 12 02:40:20 PM PDT 24
Finished Mar 12 02:40:25 PM PDT 24
Peak memory 203580 kb
Host smart-9abf9c82-1ebd-4734-a542-9c521669c343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430203993 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.430203993
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.3433184318
Short name T634
Test name
Test status
Simulation time 3666349144 ps
CPU time 4.92 seconds
Started Mar 12 02:40:23 PM PDT 24
Finished Mar 12 02:40:29 PM PDT 24
Peak memory 203580 kb
Host smart-0f2c7f8d-ed36-461c-9187-f464dc54ef06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433184318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.3433184318
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.53245720
Short name T1181
Test name
Test status
Simulation time 635707396 ps
CPU time 26.55 seconds
Started Mar 12 02:40:21 PM PDT 24
Finished Mar 12 02:40:48 PM PDT 24
Peak memory 203584 kb
Host smart-ae7ac485-b7ea-46db-92df-c9cc534cabbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53245720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_rd.53245720
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.996872060
Short name T923
Test name
Test status
Simulation time 59900569100 ps
CPU time 237.44 seconds
Started Mar 12 02:40:23 PM PDT 24
Finished Mar 12 02:44:21 PM PDT 24
Peak memory 2539940 kb
Host smart-dffad5d8-9276-4826-8692-5da5dd445aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996872060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.996872060
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1781654108
Short name T589
Test name
Test status
Simulation time 32367811945 ps
CPU time 1219.61 seconds
Started Mar 12 02:40:25 PM PDT 24
Finished Mar 12 03:00:47 PM PDT 24
Peak memory 5195952 kb
Host smart-8b1ef0a8-99b0-4f3f-9bef-6500484f1f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781654108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1781654108
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2254907939
Short name T684
Test name
Test status
Simulation time 11792194956 ps
CPU time 7.47 seconds
Started Mar 12 02:40:22 PM PDT 24
Finished Mar 12 02:40:30 PM PDT 24
Peak memory 213960 kb
Host smart-90ed4f31-5c84-4a58-b989-9ea056789e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254907939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2254907939
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.1287029067
Short name T1056
Test name
Test status
Simulation time 5233290068 ps
CPU time 5.31 seconds
Started Mar 12 02:40:25 PM PDT 24
Finished Mar 12 02:40:33 PM PDT 24
Peak memory 203548 kb
Host smart-46dfeb7e-c896-4a90-aba3-b2c34125ec5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287029067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.1287029067
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.4040959597
Short name T311
Test name
Test status
Simulation time 15557663 ps
CPU time 0.61 seconds
Started Mar 12 02:40:40 PM PDT 24
Finished Mar 12 02:40:42 PM PDT 24
Peak memory 202352 kb
Host smart-07f0cfd3-c182-4afb-88c0-7d99ebc73930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040959597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.4040959597
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1667537933
Short name T1079
Test name
Test status
Simulation time 66658868 ps
CPU time 1.11 seconds
Started Mar 12 02:40:35 PM PDT 24
Finished Mar 12 02:40:37 PM PDT 24
Peak memory 203544 kb
Host smart-85e95d56-9524-483e-b174-0c473306d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667537933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1667537933
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1512383453
Short name T598
Test name
Test status
Simulation time 1138227648 ps
CPU time 9.46 seconds
Started Mar 12 02:40:29 PM PDT 24
Finished Mar 12 02:40:39 PM PDT 24
Peak memory 321476 kb
Host smart-75ff7ae9-2683-4724-8f8e-ea89319eb465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512383453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1512383453
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3871118518
Short name T652
Test name
Test status
Simulation time 3972724042 ps
CPU time 261.03 seconds
Started Mar 12 02:40:31 PM PDT 24
Finished Mar 12 02:44:53 PM PDT 24
Peak memory 1004340 kb
Host smart-19ba316f-5933-4843-aafb-4784c7421223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871118518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3871118518
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2775881997
Short name T1096
Test name
Test status
Simulation time 1487298922 ps
CPU time 37.51 seconds
Started Mar 12 02:40:30 PM PDT 24
Finished Mar 12 02:41:09 PM PDT 24
Peak memory 456172 kb
Host smart-c00f2e4e-2458-4056-b1bd-b7b9e9889453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775881997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2775881997
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1146277593
Short name T735
Test name
Test status
Simulation time 482603589 ps
CPU time 0.72 seconds
Started Mar 12 02:40:32 PM PDT 24
Finished Mar 12 02:40:33 PM PDT 24
Peak memory 202548 kb
Host smart-937d89fd-d28a-4d6f-983a-63679050c0cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146277593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1146277593
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2201502668
Short name T767
Test name
Test status
Simulation time 174024277 ps
CPU time 4.19 seconds
Started Mar 12 02:40:31 PM PDT 24
Finished Mar 12 02:40:36 PM PDT 24
Peak memory 203540 kb
Host smart-553fa414-0ebb-4d4b-a1b1-3cee4674f30c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201502668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2201502668
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1906545117
Short name T1162
Test name
Test status
Simulation time 5506832941 ps
CPU time 129.26 seconds
Started Mar 12 02:40:30 PM PDT 24
Finished Mar 12 02:42:41 PM PDT 24
Peak memory 1368036 kb
Host smart-b33ca96d-49bb-433c-82aa-d5971940f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906545117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1906545117
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.750749952
Short name T626
Test name
Test status
Simulation time 10117400084 ps
CPU time 124.98 seconds
Started Mar 12 02:40:40 PM PDT 24
Finished Mar 12 02:42:46 PM PDT 24
Peak memory 402584 kb
Host smart-16f5d6a7-392e-4854-88ec-03676d0f35d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750749952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.750749952
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.218957586
Short name T975
Test name
Test status
Simulation time 20293207 ps
CPU time 0.64 seconds
Started Mar 12 02:40:31 PM PDT 24
Finished Mar 12 02:40:33 PM PDT 24
Peak memory 202524 kb
Host smart-c207c6cb-d250-48f6-b446-2447f266a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218957586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.218957586
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.12003685
Short name T551
Test name
Test status
Simulation time 52816260991 ps
CPU time 675.68 seconds
Started Mar 12 02:40:32 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 203640 kb
Host smart-ecbaefe5-5e71-48f3-be11-fb9bf25baa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12003685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.12003685
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1804284225
Short name T1124
Test name
Test status
Simulation time 5327560004 ps
CPU time 67.24 seconds
Started Mar 12 02:40:29 PM PDT 24
Finished Mar 12 02:41:37 PM PDT 24
Peak memory 316260 kb
Host smart-4dad7744-1816-4d1b-8ff1-0b873a90eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804284225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1804284225
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.2807659570
Short name T152
Test name
Test status
Simulation time 23433348571 ps
CPU time 1275.85 seconds
Started Mar 12 02:40:31 PM PDT 24
Finished Mar 12 03:01:48 PM PDT 24
Peak memory 2278552 kb
Host smart-770a82a5-81e8-4ba6-b3b3-945da03d852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807659570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2807659570
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.4095480163
Short name T408
Test name
Test status
Simulation time 1775071023 ps
CPU time 13.61 seconds
Started Mar 12 02:40:30 PM PDT 24
Finished Mar 12 02:40:45 PM PDT 24
Peak memory 214048 kb
Host smart-26507cf1-af2b-404b-897c-162144a4f364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095480163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4095480163
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.577382870
Short name T1076
Test name
Test status
Simulation time 3143612938 ps
CPU time 3.64 seconds
Started Mar 12 02:40:44 PM PDT 24
Finished Mar 12 02:40:48 PM PDT 24
Peak memory 203604 kb
Host smart-1afff27b-2e78-4553-ad1b-c494005c0bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577382870 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.577382870
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1625264537
Short name T553
Test name
Test status
Simulation time 10188811598 ps
CPU time 84.22 seconds
Started Mar 12 02:40:38 PM PDT 24
Finished Mar 12 02:42:03 PM PDT 24
Peak memory 698776 kb
Host smart-baeba7ff-536f-46ff-8767-1acb67a5b8b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625264537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1625264537
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3461615493
Short name T188
Test name
Test status
Simulation time 516616570 ps
CPU time 2.64 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:40:44 PM PDT 24
Peak memory 203636 kb
Host smart-9890cbcc-ffdc-40d7-a503-ee23e4999a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461615493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3461615493
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2185939996
Short name T769
Test name
Test status
Simulation time 3064550845 ps
CPU time 6.67 seconds
Started Mar 12 02:40:41 PM PDT 24
Finished Mar 12 02:40:49 PM PDT 24
Peak memory 203584 kb
Host smart-6ff3132a-f169-4c72-b8bb-de72594a7794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185939996 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2185939996
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.284871485
Short name T865
Test name
Test status
Simulation time 21636442189 ps
CPU time 405.65 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:47:26 PM PDT 24
Peak memory 3455224 kb
Host smart-61df2167-506f-4095-abc0-4ec133270ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284871485 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.284871485
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.4188951567
Short name T276
Test name
Test status
Simulation time 1771831386 ps
CPU time 2.83 seconds
Started Mar 12 02:40:38 PM PDT 24
Finished Mar 12 02:40:42 PM PDT 24
Peak memory 203640 kb
Host smart-4a60c2c4-7b8b-4e37-9aae-615646a6c8fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188951567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.4188951567
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.90541483
Short name T1
Test name
Test status
Simulation time 911895571 ps
CPU time 36.1 seconds
Started Mar 12 02:40:38 PM PDT 24
Finished Mar 12 02:41:15 PM PDT 24
Peak memory 203588 kb
Host smart-db718d2b-e55d-4ec1-aefd-dfb6ffa7185a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90541483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_rd.90541483
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4256354798
Short name T1145
Test name
Test status
Simulation time 43085581721 ps
CPU time 587.92 seconds
Started Mar 12 02:40:43 PM PDT 24
Finished Mar 12 02:50:32 PM PDT 24
Peak memory 5238444 kb
Host smart-d1de3b7c-ddcd-4ecb-8600-e46c08827c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256354798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4256354798
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3455086160
Short name T399
Test name
Test status
Simulation time 29417958742 ps
CPU time 2561.59 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 03:23:22 PM PDT 24
Peak memory 7287808 kb
Host smart-50b36e67-521a-44c8-b09d-181dcb2646df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455086160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3455086160
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3654362630
Short name T309
Test name
Test status
Simulation time 8086536937 ps
CPU time 6.52 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:40:48 PM PDT 24
Peak memory 203656 kb
Host smart-2a22faff-16f6-4913-a66a-30123bae19f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654362630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3654362630
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.3123097040
Short name T870
Test name
Test status
Simulation time 2084620166 ps
CPU time 5.91 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:40:47 PM PDT 24
Peak memory 205100 kb
Host smart-e9f694b6-31f7-454b-8ad5-907ae4fef83b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123097040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.3123097040
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3200349535
Short name T619
Test name
Test status
Simulation time 23812681 ps
CPU time 0.61 seconds
Started Mar 12 02:40:57 PM PDT 24
Finished Mar 12 02:40:58 PM PDT 24
Peak memory 202284 kb
Host smart-c100ab5d-590b-4a1c-ba17-2eb522194d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200349535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3200349535
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1901167562
Short name T579
Test name
Test status
Simulation time 47263101 ps
CPU time 1.33 seconds
Started Mar 12 02:40:52 PM PDT 24
Finished Mar 12 02:40:54 PM PDT 24
Peak memory 203528 kb
Host smart-94898ea1-670a-4dd2-b760-011d5a4bffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901167562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1901167562
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3862377359
Short name T449
Test name
Test status
Simulation time 2055126195 ps
CPU time 21.46 seconds
Started Mar 12 02:40:41 PM PDT 24
Finished Mar 12 02:41:04 PM PDT 24
Peak memory 291940 kb
Host smart-e4fa8017-0b34-4bd4-aa17-6066e79272f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862377359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3862377359
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2024521416
Short name T611
Test name
Test status
Simulation time 10031241486 ps
CPU time 165.47 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:43:26 PM PDT 24
Peak memory 656972 kb
Host smart-97361631-53bf-49a6-9a80-fd8d4db36433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024521416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2024521416
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2966676659
Short name T683
Test name
Test status
Simulation time 14272144734 ps
CPU time 233.22 seconds
Started Mar 12 02:40:40 PM PDT 24
Finished Mar 12 02:44:34 PM PDT 24
Peak memory 878964 kb
Host smart-2b2460a4-26a8-46a2-bc5a-e4c69cd27d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966676659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2966676659
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1756459097
Short name T770
Test name
Test status
Simulation time 128390646 ps
CPU time 0.75 seconds
Started Mar 12 02:40:40 PM PDT 24
Finished Mar 12 02:40:42 PM PDT 24
Peak memory 202536 kb
Host smart-67a82a4f-c32c-46f3-9b28-e5ddd5a233ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756459097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1756459097
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3119329589
Short name T644
Test name
Test status
Simulation time 376489023 ps
CPU time 9.56 seconds
Started Mar 12 02:40:38 PM PDT 24
Finished Mar 12 02:40:49 PM PDT 24
Peak memory 203476 kb
Host smart-b6dd6bf0-29c6-4c51-b8b7-08891db064b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119329589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3119329589
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3242426167
Short name T488
Test name
Test status
Simulation time 17408339046 ps
CPU time 120.88 seconds
Started Mar 12 02:40:41 PM PDT 24
Finished Mar 12 02:42:43 PM PDT 24
Peak memory 1200648 kb
Host smart-3d76b052-3db1-44fb-a19e-044d66122c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242426167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3242426167
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1015784181
Short name T10
Test name
Test status
Simulation time 11101261163 ps
CPU time 62.19 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:41:56 PM PDT 24
Peak memory 301752 kb
Host smart-f2689e7b-1b25-4f86-b1d2-bb82816c621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015784181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1015784181
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3272536282
Short name T168
Test name
Test status
Simulation time 59651409 ps
CPU time 0.63 seconds
Started Mar 12 02:40:38 PM PDT 24
Finished Mar 12 02:40:40 PM PDT 24
Peak memory 202568 kb
Host smart-86aea151-ad72-473d-b5d2-d93e60785649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272536282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3272536282
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2267388775
Short name T677
Test name
Test status
Simulation time 13373184193 ps
CPU time 172.79 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:43:33 PM PDT 24
Peak memory 252200 kb
Host smart-0bc59e61-8dcd-4005-b085-a7bd2ab5abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267388775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2267388775
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2859783490
Short name T1012
Test name
Test status
Simulation time 5452018001 ps
CPU time 44.88 seconds
Started Mar 12 02:40:40 PM PDT 24
Finished Mar 12 02:41:26 PM PDT 24
Peak memory 281324 kb
Host smart-7ed43c93-c13a-4b06-9cc1-77f77e14f62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859783490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2859783490
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1257184178
Short name T900
Test name
Test status
Simulation time 100836637651 ps
CPU time 1281.81 seconds
Started Mar 12 02:40:47 PM PDT 24
Finished Mar 12 03:02:09 PM PDT 24
Peak memory 1821432 kb
Host smart-1a805aca-73f5-4e2f-a2e5-a4ef50755b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257184178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1257184178
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1111854717
Short name T402
Test name
Test status
Simulation time 1087422759 ps
CPU time 15.75 seconds
Started Mar 12 02:40:39 PM PDT 24
Finished Mar 12 02:40:56 PM PDT 24
Peak memory 218476 kb
Host smart-1ec5c1c2-e7b5-455d-8e2c-d0391906c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111854717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1111854717
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1861391364
Short name T1034
Test name
Test status
Simulation time 1948184457 ps
CPU time 2.67 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:40:58 PM PDT 24
Peak memory 203616 kb
Host smart-f9561808-3368-4705-a053-c4502e1b54f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861391364 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1861391364
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2293663289
Short name T1155
Test name
Test status
Simulation time 10057518301 ps
CPU time 93.03 seconds
Started Mar 12 02:40:51 PM PDT 24
Finished Mar 12 02:42:25 PM PDT 24
Peak memory 605592 kb
Host smart-fcffffc2-0169-4119-8ba2-94ee063956a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293663289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2293663289
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1737001983
Short name T654
Test name
Test status
Simulation time 3682440699 ps
CPU time 3.89 seconds
Started Mar 12 02:40:46 PM PDT 24
Finished Mar 12 02:40:50 PM PDT 24
Peak memory 203608 kb
Host smart-79b7a5d7-8743-4e5b-879f-b573d4110aef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737001983 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1737001983
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1287058382
Short name T237
Test name
Test status
Simulation time 16734848260 ps
CPU time 189.2 seconds
Started Mar 12 02:40:46 PM PDT 24
Finished Mar 12 02:43:55 PM PDT 24
Peak memory 2415160 kb
Host smart-af3d8964-bfc9-4fbe-ae15-c21644e6d950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287058382 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1287058382
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1051193428
Short name T542
Test name
Test status
Simulation time 731080773 ps
CPU time 4.3 seconds
Started Mar 12 02:40:56 PM PDT 24
Finished Mar 12 02:41:01 PM PDT 24
Peak memory 203624 kb
Host smart-d5179f92-9cc3-4eaf-9866-eebfd27495d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051193428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1051193428
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2837495584
Short name T318
Test name
Test status
Simulation time 1400729021 ps
CPU time 38.61 seconds
Started Mar 12 02:40:45 PM PDT 24
Finished Mar 12 02:41:24 PM PDT 24
Peak memory 203588 kb
Host smart-5884a07e-67af-4113-922d-419370f6d282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837495584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2837495584
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.4181417938
Short name T405
Test name
Test status
Simulation time 7825943622 ps
CPU time 15.8 seconds
Started Mar 12 02:40:47 PM PDT 24
Finished Mar 12 02:41:04 PM PDT 24
Peak memory 203632 kb
Host smart-b893b764-ef64-4257-981f-7c94274e3da0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181417938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.4181417938
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2342837147
Short name T668
Test name
Test status
Simulation time 29059007675 ps
CPU time 113.2 seconds
Started Mar 12 02:40:52 PM PDT 24
Finished Mar 12 02:42:46 PM PDT 24
Peak memory 525292 kb
Host smart-6bee90ff-e860-4ef9-adfa-c63ffa0c269e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342837147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2342837147
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.382436421
Short name T1129
Test name
Test status
Simulation time 6788651576 ps
CPU time 6.87 seconds
Started Mar 12 02:40:45 PM PDT 24
Finished Mar 12 02:40:52 PM PDT 24
Peak memory 213608 kb
Host smart-9e1be144-60e1-40de-8c7d-e9f9398de0ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382436421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.382436421
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.937426124
Short name T1119
Test name
Test status
Simulation time 3227687522 ps
CPU time 7.67 seconds
Started Mar 12 02:40:46 PM PDT 24
Finished Mar 12 02:40:54 PM PDT 24
Peak memory 213924 kb
Host smart-0008d2ce-7029-437d-b455-e2576f6f06fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937426124 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_unexp_stop.937426124
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3644449463
Short name T1177
Test name
Test status
Simulation time 49622288 ps
CPU time 0.63 seconds
Started Mar 12 02:41:01 PM PDT 24
Finished Mar 12 02:41:02 PM PDT 24
Peak memory 202384 kb
Host smart-616caa4a-b51c-428a-9da5-77e567bba19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644449463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3644449463
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2036377168
Short name T236
Test name
Test status
Simulation time 40493213 ps
CPU time 1.87 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:40:57 PM PDT 24
Peak memory 219936 kb
Host smart-3184e716-a6c8-4674-a6a3-c28d0c880bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036377168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2036377168
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2820328783
Short name T316
Test name
Test status
Simulation time 539391769 ps
CPU time 4.89 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:41:00 PM PDT 24
Peak memory 245928 kb
Host smart-eebb085a-5a40-4150-bb38-0f939b0b5191
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820328783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2820328783
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2282411528
Short name T391
Test name
Test status
Simulation time 3817119606 ps
CPU time 46.46 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:41:40 PM PDT 24
Peak memory 486464 kb
Host smart-a316c450-3571-4ca4-896c-2b3c9ce82de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282411528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2282411528
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.404353354
Short name T76
Test name
Test status
Simulation time 7496527535 ps
CPU time 119.07 seconds
Started Mar 12 02:40:57 PM PDT 24
Finished Mar 12 02:42:56 PM PDT 24
Peak memory 570008 kb
Host smart-3d1d04bb-a50b-4b15-bc24-0066eb407bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404353354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.404353354
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3126581591
Short name T744
Test name
Test status
Simulation time 611918980 ps
CPU time 0.98 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:40:56 PM PDT 24
Peak memory 203288 kb
Host smart-fee2a771-e215-411a-a5e1-ff1fb383655a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126581591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3126581591
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.4048057082
Short name T751
Test name
Test status
Simulation time 446953058 ps
CPU time 11.13 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 203448 kb
Host smart-e0b14f99-e3df-4fa1-9bf5-9aea92d1aec0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048057082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.4048057082
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2373121875
Short name T274
Test name
Test status
Simulation time 5576180531 ps
CPU time 182.92 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:43:58 PM PDT 24
Peak memory 1563640 kb
Host smart-e9995e49-48da-4160-a7d0-67a12adc9270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373121875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2373121875
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2936972817
Short name T933
Test name
Test status
Simulation time 1865526789 ps
CPU time 89.34 seconds
Started Mar 12 02:41:04 PM PDT 24
Finished Mar 12 02:42:34 PM PDT 24
Peak memory 253904 kb
Host smart-f9f177d1-6ab7-44ad-adbf-b569d3532d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936972817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2936972817
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.978407053
Short name T164
Test name
Test status
Simulation time 19481635 ps
CPU time 0.61 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:40:56 PM PDT 24
Peak memory 202564 kb
Host smart-3ad5a16f-fb32-489d-b2a9-7556d52730e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978407053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.978407053
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2723626104
Short name T23
Test name
Test status
Simulation time 19361821237 ps
CPU time 488.19 seconds
Started Mar 12 02:40:56 PM PDT 24
Finished Mar 12 02:49:04 PM PDT 24
Peak memory 211764 kb
Host smart-6bb7dff5-4c5c-4587-ae0a-5fcb1220d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723626104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2723626104
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2947346107
Short name T1178
Test name
Test status
Simulation time 3058726634 ps
CPU time 59.42 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 334016 kb
Host smart-4bb86f87-37dc-46b1-a2e5-da2e977511f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947346107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2947346107
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3454223653
Short name T1209
Test name
Test status
Simulation time 32066330831 ps
CPU time 2937.11 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 03:29:52 PM PDT 24
Peak memory 1188492 kb
Host smart-1d2efcf8-18e1-44ce-a317-4c16f5e2c07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454223653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3454223653
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1861447011
Short name T306
Test name
Test status
Simulation time 595444474 ps
CPU time 27.45 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:41:22 PM PDT 24
Peak memory 211704 kb
Host smart-af3ba73d-113f-4ba1-bfaf-7273c30df402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861447011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1861447011
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3735785209
Short name T30
Test name
Test status
Simulation time 3363186135 ps
CPU time 3.8 seconds
Started Mar 12 02:41:02 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 203536 kb
Host smart-c8b83d1b-a87b-4612-9427-829796e60114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735785209 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3735785209
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.405728016
Short name T912
Test name
Test status
Simulation time 10141629777 ps
CPU time 68.99 seconds
Started Mar 12 02:41:06 PM PDT 24
Finished Mar 12 02:42:15 PM PDT 24
Peak memory 616548 kb
Host smart-bacce3b5-b2a9-4cd9-8dbd-3b095c3b6219
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405728016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.405728016
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1932511137
Short name T670
Test name
Test status
Simulation time 10207975737 ps
CPU time 17.36 seconds
Started Mar 12 02:41:05 PM PDT 24
Finished Mar 12 02:41:23 PM PDT 24
Peak memory 319440 kb
Host smart-b18e2936-9c96-45ce-bd2d-f112fd0c5eb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932511137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1932511137
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2290406933
Short name T201
Test name
Test status
Simulation time 493385556 ps
CPU time 2.75 seconds
Started Mar 12 02:41:03 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 203584 kb
Host smart-c13b866b-a8ad-4410-b38b-c45e0cc1cfa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290406933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2290406933
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3297027173
Short name T1239
Test name
Test status
Simulation time 2457540505 ps
CPU time 5.98 seconds
Started Mar 12 02:40:57 PM PDT 24
Finished Mar 12 02:41:03 PM PDT 24
Peak memory 203604 kb
Host smart-1b68e4de-8f35-44c0-80fe-accbba21fbf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297027173 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3297027173
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.417979788
Short name T630
Test name
Test status
Simulation time 9537092667 ps
CPU time 16.5 seconds
Started Mar 12 02:40:56 PM PDT 24
Finished Mar 12 02:41:12 PM PDT 24
Peak memory 400700 kb
Host smart-35f77106-1e8d-4439-9ef9-edfee44d3b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417979788 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.417979788
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.2256587293
Short name T578
Test name
Test status
Simulation time 452674265 ps
CPU time 3.07 seconds
Started Mar 12 02:41:01 PM PDT 24
Finished Mar 12 02:41:05 PM PDT 24
Peak memory 203596 kb
Host smart-67f8178c-c5fd-4186-bb2e-b38d5b882fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256587293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.2256587293
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2494454316
Short name T1220
Test name
Test status
Simulation time 7796610959 ps
CPU time 33.12 seconds
Started Mar 12 02:41:03 PM PDT 24
Finished Mar 12 02:41:36 PM PDT 24
Peak memory 220856 kb
Host smart-37166125-12d3-486f-b3d4-819f8494278a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494454316 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2494454316
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1457370257
Short name T453
Test name
Test status
Simulation time 2009551247 ps
CPU time 17.73 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:41:12 PM PDT 24
Peak memory 203648 kb
Host smart-e6d3f300-6ace-48e4-9e2f-2ba671d7b16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457370257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1457370257
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.761163857
Short name T660
Test name
Test status
Simulation time 27423678918 ps
CPU time 124.93 seconds
Started Mar 12 02:40:55 PM PDT 24
Finished Mar 12 02:43:00 PM PDT 24
Peak memory 1824372 kb
Host smart-36871da8-653a-4dc4-95bd-92cc3483780d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761163857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.761163857
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.3587762743
Short name T472
Test name
Test status
Simulation time 1930975205 ps
CPU time 4.63 seconds
Started Mar 12 02:40:54 PM PDT 24
Finished Mar 12 02:40:59 PM PDT 24
Peak memory 203600 kb
Host smart-a486e07b-877c-41f7-9f5d-093629176f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587762743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.3587762743
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3441173492
Short name T827
Test name
Test status
Simulation time 44702564 ps
CPU time 0.62 seconds
Started Mar 12 02:33:30 PM PDT 24
Finished Mar 12 02:33:31 PM PDT 24
Peak memory 202388 kb
Host smart-6a724d59-7cfc-4e28-b02f-a8df26eeaf77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441173492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3441173492
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.468729787
Short name T328
Test name
Test status
Simulation time 36205590 ps
CPU time 1.28 seconds
Started Mar 12 02:33:24 PM PDT 24
Finished Mar 12 02:33:26 PM PDT 24
Peak memory 211828 kb
Host smart-cdceaa29-ed97-4b1c-8320-e311ad728a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468729787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.468729787
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3523299879
Short name T489
Test name
Test status
Simulation time 308815769 ps
CPU time 5.55 seconds
Started Mar 12 02:33:19 PM PDT 24
Finished Mar 12 02:33:25 PM PDT 24
Peak memory 266132 kb
Host smart-6ed09dfa-85d8-43d3-a58e-5e701e3edc30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523299879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3523299879
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.824843748
Short name T954
Test name
Test status
Simulation time 5184890916 ps
CPU time 87.46 seconds
Started Mar 12 02:33:22 PM PDT 24
Finished Mar 12 02:34:50 PM PDT 24
Peak memory 863108 kb
Host smart-ecd9fc1f-774f-4739-9209-2c9d3d5b03a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824843748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.824843748
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3403266919
Short name T763
Test name
Test status
Simulation time 10624450441 ps
CPU time 79.62 seconds
Started Mar 12 02:33:20 PM PDT 24
Finished Mar 12 02:34:40 PM PDT 24
Peak memory 787684 kb
Host smart-380e3980-cb80-4af6-9eaf-e96d4652cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403266919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3403266919
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.166680798
Short name T1173
Test name
Test status
Simulation time 201729352 ps
CPU time 0.85 seconds
Started Mar 12 02:33:18 PM PDT 24
Finished Mar 12 02:33:19 PM PDT 24
Peak memory 203284 kb
Host smart-e88a1b12-ab19-434c-8f2b-6b224fa7a81a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166680798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.166680798
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2605885258
Short name T811
Test name
Test status
Simulation time 148856434 ps
CPU time 9.03 seconds
Started Mar 12 02:33:21 PM PDT 24
Finished Mar 12 02:33:30 PM PDT 24
Peak memory 229064 kb
Host smart-fee32d36-c953-420c-bda7-fcf03154b2ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605885258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2605885258
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3852861443
Short name T347
Test name
Test status
Simulation time 14744585049 ps
CPU time 316.72 seconds
Started Mar 12 02:33:18 PM PDT 24
Finished Mar 12 02:38:35 PM PDT 24
Peak memory 1231500 kb
Host smart-8011f210-acbb-4982-a5d8-a8ffcbdcdc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852861443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3852861443
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1880817888
Short name T431
Test name
Test status
Simulation time 3080408048 ps
CPU time 36.9 seconds
Started Mar 12 02:33:31 PM PDT 24
Finished Mar 12 02:34:08 PM PDT 24
Peak memory 261596 kb
Host smart-a84b1650-5e70-4c92-baad-3475dc0e03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880817888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1880817888
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.554332440
Short name T338
Test name
Test status
Simulation time 32827923 ps
CPU time 0.64 seconds
Started Mar 12 02:33:19 PM PDT 24
Finished Mar 12 02:33:20 PM PDT 24
Peak memory 202592 kb
Host smart-1aa5e596-2d3f-431c-bd43-3eccaed15feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554332440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.554332440
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1449945263
Short name T851
Test name
Test status
Simulation time 5192381126 ps
CPU time 313.28 seconds
Started Mar 12 02:33:24 PM PDT 24
Finished Mar 12 02:38:37 PM PDT 24
Peak memory 282872 kb
Host smart-52abd2b5-dcff-46f2-8976-55f4f7025632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449945263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1449945263
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1951351797
Short name T842
Test name
Test status
Simulation time 1862451420 ps
CPU time 46.26 seconds
Started Mar 12 02:33:20 PM PDT 24
Finished Mar 12 02:34:06 PM PDT 24
Peak memory 292872 kb
Host smart-053e23f6-51f8-491d-afea-ab40c79c3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951351797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1951351797
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.745318785
Short name T215
Test name
Test status
Simulation time 65175359736 ps
CPU time 1222.04 seconds
Started Mar 12 02:33:25 PM PDT 24
Finished Mar 12 02:53:47 PM PDT 24
Peak memory 3298872 kb
Host smart-df82d8cb-7c9d-4194-bbf4-b931fdc6f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745318785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.745318785
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1427467662
Short name T898
Test name
Test status
Simulation time 1224031140 ps
CPU time 26.13 seconds
Started Mar 12 02:33:24 PM PDT 24
Finished Mar 12 02:33:50 PM PDT 24
Peak memory 211808 kb
Host smart-b181a66f-74b0-489d-b11b-e41bc9fb85bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427467662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1427467662
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1599765923
Short name T104
Test name
Test status
Simulation time 274335311 ps
CPU time 0.83 seconds
Started Mar 12 02:33:31 PM PDT 24
Finished Mar 12 02:33:32 PM PDT 24
Peak memory 220608 kb
Host smart-d064a1a4-c2bf-4766-999a-f7764b67f0ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599765923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1599765923
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1655156057
Short name T393
Test name
Test status
Simulation time 2705174025 ps
CPU time 3.67 seconds
Started Mar 12 02:33:29 PM PDT 24
Finished Mar 12 02:33:33 PM PDT 24
Peak memory 203612 kb
Host smart-cd40f184-8fe9-42ce-bff9-0c9997a8764e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655156057 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1655156057
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1126498209
Short name T999
Test name
Test status
Simulation time 10312894382 ps
CPU time 13.5 seconds
Started Mar 12 02:33:31 PM PDT 24
Finished Mar 12 02:33:45 PM PDT 24
Peak memory 280900 kb
Host smart-befa0e7a-f41f-4ea3-92b8-b05e39c6e8ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126498209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1126498209
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.4283805070
Short name T892
Test name
Test status
Simulation time 10134447111 ps
CPU time 11.16 seconds
Started Mar 12 02:33:30 PM PDT 24
Finished Mar 12 02:33:41 PM PDT 24
Peak memory 289136 kb
Host smart-8243d7aa-ed25-4a5a-a36d-848253684c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283805070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.4283805070
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.550289089
Short name T601
Test name
Test status
Simulation time 2545517379 ps
CPU time 2.9 seconds
Started Mar 12 02:33:29 PM PDT 24
Finished Mar 12 02:33:32 PM PDT 24
Peak memory 203676 kb
Host smart-0e567bf5-9eb6-4363-9c44-65da94e6745a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550289089 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.550289089
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.412506941
Short name T230
Test name
Test status
Simulation time 1746510272 ps
CPU time 4.14 seconds
Started Mar 12 02:33:23 PM PDT 24
Finished Mar 12 02:33:27 PM PDT 24
Peak memory 203576 kb
Host smart-0a262966-a5cc-43d1-ad7c-ba4b8057f088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412506941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.412506941
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3867300662
Short name T269
Test name
Test status
Simulation time 3916376589 ps
CPU time 5.1 seconds
Started Mar 12 02:33:24 PM PDT 24
Finished Mar 12 02:33:29 PM PDT 24
Peak memory 203632 kb
Host smart-faee329f-993c-4d7c-baf3-36e8f721f8c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867300662 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3867300662
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.3650910696
Short name T672
Test name
Test status
Simulation time 740190175 ps
CPU time 4.36 seconds
Started Mar 12 02:33:29 PM PDT 24
Finished Mar 12 02:33:33 PM PDT 24
Peak memory 210932 kb
Host smart-3b328b05-488c-48f6-b2aa-97698daf1299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650910696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.3650910696
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.1558839725
Short name T193
Test name
Test status
Simulation time 35456409412 ps
CPU time 53.16 seconds
Started Mar 12 02:33:32 PM PDT 24
Finished Mar 12 02:34:25 PM PDT 24
Peak memory 594696 kb
Host smart-ff2f3cb1-92eb-4b1d-a788-5f44b668f9c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558839725 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.1558839725
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.4185894444
Short name T1246
Test name
Test status
Simulation time 5529100666 ps
CPU time 61.07 seconds
Started Mar 12 02:33:22 PM PDT 24
Finished Mar 12 02:34:23 PM PDT 24
Peak memory 204372 kb
Host smart-cda5e436-4d66-4791-afc5-03d55a2ad32a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185894444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.4185894444
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1229048737
Short name T972
Test name
Test status
Simulation time 67911757955 ps
CPU time 302.49 seconds
Started Mar 12 02:33:23 PM PDT 24
Finished Mar 12 02:38:26 PM PDT 24
Peak memory 2995396 kb
Host smart-66f1ecfe-4aa0-4c96-adc5-fafc5289fadd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229048737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1229048737
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.225950816
Short name T753
Test name
Test status
Simulation time 41221198690 ps
CPU time 1313.75 seconds
Started Mar 12 02:33:23 PM PDT 24
Finished Mar 12 02:55:17 PM PDT 24
Peak memory 5010288 kb
Host smart-b0c88e07-0283-4d42-9549-bccf0911474f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225950816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.225950816
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.349032176
Short name T524
Test name
Test status
Simulation time 32193311036 ps
CPU time 7.63 seconds
Started Mar 12 02:33:30 PM PDT 24
Finished Mar 12 02:33:37 PM PDT 24
Peak memory 216908 kb
Host smart-d7e495c0-e057-4223-bdd3-0de9e707cc2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349032176 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.349032176
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1214376262
Short name T1257
Test name
Test status
Simulation time 4691518667 ps
CPU time 6.1 seconds
Started Mar 12 02:33:30 PM PDT 24
Finished Mar 12 02:33:37 PM PDT 24
Peak memory 207452 kb
Host smart-ce9748ad-fc88-4977-bc1e-2109fd05d60d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214376262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1214376262
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3190620854
Short name T1204
Test name
Test status
Simulation time 82365977 ps
CPU time 0.57 seconds
Started Mar 12 02:41:11 PM PDT 24
Finished Mar 12 02:41:12 PM PDT 24
Peak memory 202332 kb
Host smart-a7d7fc6f-793c-45b3-acf6-08263739037e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190620854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3190620854
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.507151021
Short name T1103
Test name
Test status
Simulation time 32851121 ps
CPU time 1.41 seconds
Started Mar 12 02:41:03 PM PDT 24
Finished Mar 12 02:41:04 PM PDT 24
Peak memory 203564 kb
Host smart-3c31a682-f6f0-423d-9a08-1062eecec0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507151021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.507151021
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2684290716
Short name T467
Test name
Test status
Simulation time 1770078901 ps
CPU time 21.58 seconds
Started Mar 12 02:41:04 PM PDT 24
Finished Mar 12 02:41:26 PM PDT 24
Peak memory 281248 kb
Host smart-87bb35c1-b5e3-40c7-b20f-bcad72ebee0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684290716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2684290716
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2005187970
Short name T631
Test name
Test status
Simulation time 1550475508 ps
CPU time 57.03 seconds
Started Mar 12 02:41:02 PM PDT 24
Finished Mar 12 02:42:00 PM PDT 24
Peak memory 587532 kb
Host smart-163acd22-64fa-4166-9585-a443bdf9c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005187970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2005187970
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2031213060
Short name T825
Test name
Test status
Simulation time 10836784593 ps
CPU time 99.71 seconds
Started Mar 12 02:41:03 PM PDT 24
Finished Mar 12 02:42:43 PM PDT 24
Peak memory 853312 kb
Host smart-52ce6b97-9874-4aa4-9b73-a1d903357b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031213060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2031213060
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2319637068
Short name T555
Test name
Test status
Simulation time 114622601 ps
CPU time 1.03 seconds
Started Mar 12 02:41:05 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 203520 kb
Host smart-3ee56f25-1de9-4b8f-a4b7-347ca155b9ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319637068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2319637068
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3299190059
Short name T743
Test name
Test status
Simulation time 536512879 ps
CPU time 3.38 seconds
Started Mar 12 02:41:02 PM PDT 24
Finished Mar 12 02:41:06 PM PDT 24
Peak memory 203340 kb
Host smart-25fa58b8-e7c5-4724-adf7-11b8749ca022
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299190059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3299190059
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.757093026
Short name T297
Test name
Test status
Simulation time 2292847027 ps
CPU time 49.96 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:42:03 PM PDT 24
Peak memory 246636 kb
Host smart-20109a9b-964a-4ca4-8ee5-cf7018d262b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757093026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.757093026
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3337833984
Short name T321
Test name
Test status
Simulation time 32990382 ps
CPU time 0.63 seconds
Started Mar 12 02:41:04 PM PDT 24
Finished Mar 12 02:41:05 PM PDT 24
Peak memory 203172 kb
Host smart-017f2c02-68c4-4ace-93d4-f3cd16eb626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337833984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3337833984
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1205328303
Short name T516
Test name
Test status
Simulation time 2451444508 ps
CPU time 40.2 seconds
Started Mar 12 02:41:06 PM PDT 24
Finished Mar 12 02:41:46 PM PDT 24
Peak memory 219984 kb
Host smart-b0826007-c3ba-4056-ad22-4997d9e57b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205328303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1205328303
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.636961508
Short name T695
Test name
Test status
Simulation time 2348571081 ps
CPU time 78.75 seconds
Started Mar 12 02:41:06 PM PDT 24
Finished Mar 12 02:42:24 PM PDT 24
Peak memory 243760 kb
Host smart-baeaef62-6c56-4bc7-91ee-4b4e2c8d484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636961508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.636961508
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.811938103
Short name T39
Test name
Test status
Simulation time 7575813478 ps
CPU time 672.86 seconds
Started Mar 12 02:41:13 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 1059440 kb
Host smart-f1e6a31b-c8c2-4a16-925c-8f0e4ae7ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811938103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.811938103
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.4201115962
Short name T1068
Test name
Test status
Simulation time 759122441 ps
CPU time 26.09 seconds
Started Mar 12 02:41:07 PM PDT 24
Finished Mar 12 02:41:33 PM PDT 24
Peak memory 211784 kb
Host smart-59904d6d-5cdf-4e7d-bdfc-6e9e6e7a1a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201115962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.4201115962
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3859852295
Short name T534
Test name
Test status
Simulation time 910661388 ps
CPU time 2.45 seconds
Started Mar 12 02:41:11 PM PDT 24
Finished Mar 12 02:41:14 PM PDT 24
Peak memory 203552 kb
Host smart-85f180b0-a059-4d94-bd88-84877556d63c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859852295 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3859852295
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2924331724
Short name T221
Test name
Test status
Simulation time 10253991856 ps
CPU time 12.27 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:41:25 PM PDT 24
Peak memory 283036 kb
Host smart-370b0879-017c-47a3-86b7-9a1d06b355d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924331724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2924331724
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.581040802
Short name T16
Test name
Test status
Simulation time 10323878942 ps
CPU time 11.8 seconds
Started Mar 12 02:41:10 PM PDT 24
Finished Mar 12 02:41:22 PM PDT 24
Peak memory 314552 kb
Host smart-9d871c44-adb7-4ece-9950-51d25b4cf8fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581040802 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.581040802
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3755208215
Short name T624
Test name
Test status
Simulation time 503208667 ps
CPU time 2.65 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:41:15 PM PDT 24
Peak memory 203540 kb
Host smart-5a718fe7-f803-4431-a75b-da6b363e8638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755208215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3755208215
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1190269398
Short name T1048
Test name
Test status
Simulation time 3854772230 ps
CPU time 5.02 seconds
Started Mar 12 02:41:14 PM PDT 24
Finished Mar 12 02:41:19 PM PDT 24
Peak memory 203520 kb
Host smart-907ec801-9d92-4b79-bf70-0bf332c71075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190269398 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1190269398
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_perf.4064108449
Short name T548
Test name
Test status
Simulation time 621488088 ps
CPU time 3.58 seconds
Started Mar 12 02:41:11 PM PDT 24
Finished Mar 12 02:41:16 PM PDT 24
Peak memory 208152 kb
Host smart-8a16176b-4d92-4ec1-9dd3-98b5bad1f013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064108449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.4064108449
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.606346635
Short name T949
Test name
Test status
Simulation time 16325923185 ps
CPU time 27.18 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:41:40 PM PDT 24
Peak memory 203628 kb
Host smart-8426c04e-ddc7-4d62-bcbd-7bc26689b2e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606346635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.606346635
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3308647880
Short name T375
Test name
Test status
Simulation time 733065266 ps
CPU time 29.21 seconds
Started Mar 12 02:41:14 PM PDT 24
Finished Mar 12 02:41:44 PM PDT 24
Peak memory 203412 kb
Host smart-5019e11c-6ae2-4386-ac16-a4d5eb07cb16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308647880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3308647880
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1809314025
Short name T383
Test name
Test status
Simulation time 36706119560 ps
CPU time 3091.42 seconds
Started Mar 12 02:41:13 PM PDT 24
Finished Mar 12 03:32:45 PM PDT 24
Peak memory 4488464 kb
Host smart-d635b047-7595-4726-86ee-7dd4ff14a313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809314025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1809314025
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.4089089506
Short name T737
Test name
Test status
Simulation time 1600147709 ps
CPU time 7.17 seconds
Started Mar 12 02:41:10 PM PDT 24
Finished Mar 12 02:41:18 PM PDT 24
Peak memory 206528 kb
Host smart-e415834b-4e1b-4027-885e-1a51f26968bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089089506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.4089089506
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.1418545944
Short name T35
Test name
Test status
Simulation time 10126025639 ps
CPU time 8.36 seconds
Started Mar 12 02:41:44 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 203484 kb
Host smart-e80c435f-43a4-439b-b57f-bb7f7bb5877a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418545944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.1418545944
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2754273814
Short name T701
Test name
Test status
Simulation time 17636041 ps
CPU time 0.64 seconds
Started Mar 12 02:41:28 PM PDT 24
Finished Mar 12 02:41:28 PM PDT 24
Peak memory 202396 kb
Host smart-277d4e78-166e-42b8-bb2b-a9ab756f2d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754273814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2754273814
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3870665886
Short name T1013
Test name
Test status
Simulation time 55234231 ps
CPU time 1.37 seconds
Started Mar 12 02:41:22 PM PDT 24
Finished Mar 12 02:41:24 PM PDT 24
Peak memory 211704 kb
Host smart-db918790-b7c0-44b6-97f5-3104ea29d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870665886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3870665886
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.528274351
Short name T372
Test name
Test status
Simulation time 265977398 ps
CPU time 5.58 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:41:18 PM PDT 24
Peak memory 246284 kb
Host smart-49167e62-2d12-43e4-930e-2a2acc8394f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528274351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.528274351
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1824482770
Short name T574
Test name
Test status
Simulation time 9376937799 ps
CPU time 205.73 seconds
Started Mar 12 02:41:20 PM PDT 24
Finished Mar 12 02:44:46 PM PDT 24
Peak memory 881024 kb
Host smart-aeb0d681-c1e9-4842-9201-c9e7262c5fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824482770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1824482770
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.583079327
Short name T987
Test name
Test status
Simulation time 9142328404 ps
CPU time 170.91 seconds
Started Mar 12 02:41:14 PM PDT 24
Finished Mar 12 02:44:05 PM PDT 24
Peak memory 707612 kb
Host smart-881d72e5-969e-4226-879a-3e1299100120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583079327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.583079327
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.8636531
Short name T741
Test name
Test status
Simulation time 256783416 ps
CPU time 1 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:41:14 PM PDT 24
Peak memory 203316 kb
Host smart-8d5c6abb-54bf-4806-ba2c-83d75101c275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8636531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.8636531
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1443115742
Short name T301
Test name
Test status
Simulation time 221688099 ps
CPU time 12.44 seconds
Started Mar 12 02:41:23 PM PDT 24
Finished Mar 12 02:41:36 PM PDT 24
Peak memory 245824 kb
Host smart-427c1bbc-5fd1-4f42-8199-f9f1de8d939c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443115742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1443115742
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.4098625454
Short name T847
Test name
Test status
Simulation time 5752424071 ps
CPU time 478.66 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:49:11 PM PDT 24
Peak memory 1629548 kb
Host smart-c0eda83f-c967-457b-899a-2ce9170afe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098625454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.4098625454
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2733088125
Short name T945
Test name
Test status
Simulation time 3072809702 ps
CPU time 138.98 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:43:48 PM PDT 24
Peak memory 278728 kb
Host smart-c3d7922a-381b-4587-a5b1-62ebc4747c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733088125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2733088125
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3715321542
Short name T294
Test name
Test status
Simulation time 20900700 ps
CPU time 0.63 seconds
Started Mar 12 02:41:14 PM PDT 24
Finished Mar 12 02:41:14 PM PDT 24
Peak memory 203108 kb
Host smart-6f4be9cb-c746-491d-a09d-da48de26b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715321542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3715321542
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.976271473
Short name T1061
Test name
Test status
Simulation time 54490075726 ps
CPU time 452.31 seconds
Started Mar 12 02:41:20 PM PDT 24
Finished Mar 12 02:48:53 PM PDT 24
Peak memory 516180 kb
Host smart-dd880625-dc4a-45e5-abae-0f3477442bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976271473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.976271473
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.686013806
Short name T1120
Test name
Test status
Simulation time 5731851494 ps
CPU time 77.38 seconds
Started Mar 12 02:41:12 PM PDT 24
Finished Mar 12 02:42:29 PM PDT 24
Peak memory 244284 kb
Host smart-32b73d84-396b-4dc5-8868-c7846a05bc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686013806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.686013806
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3369713935
Short name T916
Test name
Test status
Simulation time 20880229520 ps
CPU time 2261.95 seconds
Started Mar 12 02:41:22 PM PDT 24
Finished Mar 12 03:19:04 PM PDT 24
Peak memory 3231336 kb
Host smart-8f6e3fce-7847-4b08-a5a3-5548f9117bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369713935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3369713935
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.73319935
Short name T659
Test name
Test status
Simulation time 592051217 ps
CPU time 24.96 seconds
Started Mar 12 02:41:20 PM PDT 24
Finished Mar 12 02:41:45 PM PDT 24
Peak memory 211748 kb
Host smart-6031f852-42ad-4aac-8c1c-ab76cfa4306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73319935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.73319935
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3678694776
Short name T776
Test name
Test status
Simulation time 1091541851 ps
CPU time 4.39 seconds
Started Mar 12 02:41:19 PM PDT 24
Finished Mar 12 02:41:24 PM PDT 24
Peak memory 203632 kb
Host smart-b1e6f36b-7665-4171-8223-7dafface9f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678694776 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3678694776
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2837423129
Short name T219
Test name
Test status
Simulation time 10153081345 ps
CPU time 56.35 seconds
Started Mar 12 02:41:20 PM PDT 24
Finished Mar 12 02:42:17 PM PDT 24
Peak memory 498128 kb
Host smart-0fe3206c-1f6b-4157-b605-15145532d2a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837423129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2837423129
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3215910418
Short name T381
Test name
Test status
Simulation time 10044405004 ps
CPU time 91.91 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:42:53 PM PDT 24
Peak memory 767368 kb
Host smart-263a550d-267b-4487-990c-8d053577d26e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215910418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3215910418
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2555617073
Short name T665
Test name
Test status
Simulation time 470615323 ps
CPU time 2.56 seconds
Started Mar 12 02:41:23 PM PDT 24
Finished Mar 12 02:41:26 PM PDT 24
Peak memory 203624 kb
Host smart-6b78453e-0592-47cf-b30c-685531e98f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555617073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2555617073
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1600792504
Short name T1132
Test name
Test status
Simulation time 5558018024 ps
CPU time 6.51 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:41:27 PM PDT 24
Peak memory 212296 kb
Host smart-0d31e8c2-4e8e-41d4-bc32-8fb2363693f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600792504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1600792504
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_perf.2012540669
Short name T355
Test name
Test status
Simulation time 858198725 ps
CPU time 4.83 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:41:26 PM PDT 24
Peak memory 211776 kb
Host smart-bc5e4caf-d918-40c6-9fb0-116030d83b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012540669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.2012540669
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.920703869
Short name T819
Test name
Test status
Simulation time 44323359550 ps
CPU time 269 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:45:50 PM PDT 24
Peak memory 3114328 kb
Host smart-59d8d30d-1f78-46b6-aa9f-b36f514eee95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920703869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.920703869
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.765402514
Short name T481
Test name
Test status
Simulation time 41919263380 ps
CPU time 284.94 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:46:06 PM PDT 24
Peak memory 2164680 kb
Host smart-fe20a3e5-1826-45de-860a-ee142e18d602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765402514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.765402514
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2494513531
Short name T937
Test name
Test status
Simulation time 2834090323 ps
CPU time 6.61 seconds
Started Mar 12 02:41:21 PM PDT 24
Finished Mar 12 02:41:28 PM PDT 24
Peak memory 203612 kb
Host smart-84d0fef8-6602-454e-83d9-689509c0fac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494513531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2494513531
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.856728163
Short name T385
Test name
Test status
Simulation time 3796952168 ps
CPU time 5.41 seconds
Started Mar 12 02:41:19 PM PDT 24
Finished Mar 12 02:41:24 PM PDT 24
Peak memory 203652 kb
Host smart-21bd80ab-bfb2-4cc6-a822-9b02b1598f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856728163 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_unexp_stop.856728163
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.915993042
Short name T863
Test name
Test status
Simulation time 22220588 ps
CPU time 0.6 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:37 PM PDT 24
Peak memory 203372 kb
Host smart-f0b7d211-8ef3-41d4-9ce6-7518c1e43aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915993042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.915993042
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2275509726
Short name T62
Test name
Test status
Simulation time 48937990 ps
CPU time 1.35 seconds
Started Mar 12 02:41:28 PM PDT 24
Finished Mar 12 02:41:30 PM PDT 24
Peak memory 211752 kb
Host smart-38a77c27-5f40-41ad-bbd0-f49733ddb4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275509726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2275509726
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1432699123
Short name T292
Test name
Test status
Simulation time 5260454476 ps
CPU time 7.96 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:41:37 PM PDT 24
Peak memory 268020 kb
Host smart-59f88247-f1d8-4bbc-8a4e-0894dd290106
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432699123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1432699123
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2053137236
Short name T783
Test name
Test status
Simulation time 11124633401 ps
CPU time 80.86 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:42:50 PM PDT 24
Peak memory 842144 kb
Host smart-6f7c315c-481f-4ecf-ae5c-5c0d168eaf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053137236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2053137236
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1474758244
Short name T1186
Test name
Test status
Simulation time 2015906293 ps
CPU time 67.06 seconds
Started Mar 12 02:41:28 PM PDT 24
Finished Mar 12 02:42:35 PM PDT 24
Peak memory 684184 kb
Host smart-8635302e-bc60-48fe-bed2-8d262e0a62ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474758244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1474758244
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2227689745
Short name T350
Test name
Test status
Simulation time 98502350 ps
CPU time 0.86 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:41:30 PM PDT 24
Peak memory 203308 kb
Host smart-c317b144-9798-473d-b344-20205f740abd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227689745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2227689745
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3749637033
Short name T1172
Test name
Test status
Simulation time 250454933 ps
CPU time 4.69 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:41:34 PM PDT 24
Peak memory 203588 kb
Host smart-ac8478c4-40b2-4872-b8d8-6f853dd46aa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749637033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3749637033
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3914462604
Short name T511
Test name
Test status
Simulation time 20236652539 ps
CPU time 151.99 seconds
Started Mar 12 02:41:24 PM PDT 24
Finished Mar 12 02:43:56 PM PDT 24
Peak memory 1452868 kb
Host smart-e64b3b56-efea-47f5-a795-8355e6ff3c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914462604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3914462604
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1999797073
Short name T387
Test name
Test status
Simulation time 7602339894 ps
CPU time 99.34 seconds
Started Mar 12 02:41:38 PM PDT 24
Finished Mar 12 02:43:18 PM PDT 24
Peak memory 244812 kb
Host smart-d588fe7a-0cd6-4c1b-b3ba-182d4486e49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999797073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1999797073
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3024543303
Short name T28
Test name
Test status
Simulation time 7097445986 ps
CPU time 120.32 seconds
Started Mar 12 02:41:27 PM PDT 24
Finished Mar 12 02:43:28 PM PDT 24
Peak memory 372336 kb
Host smart-50b3855b-d239-4e82-9ad4-cb943b69404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024543303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3024543303
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1310648626
Short name T1113
Test name
Test status
Simulation time 2200818204 ps
CPU time 66.72 seconds
Started Mar 12 02:41:27 PM PDT 24
Finished Mar 12 02:42:34 PM PDT 24
Peak memory 316280 kb
Host smart-71689679-a587-4800-bf7a-c2b3594119c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310648626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1310648626
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1535803176
Short name T175
Test name
Test status
Simulation time 72064874638 ps
CPU time 1840.46 seconds
Started Mar 12 02:41:27 PM PDT 24
Finished Mar 12 03:12:07 PM PDT 24
Peak memory 1402236 kb
Host smart-7e225d46-5dbc-43f5-952c-096f909c0662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535803176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1535803176
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3302101673
Short name T890
Test name
Test status
Simulation time 9009186558 ps
CPU time 9.75 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:41:39 PM PDT 24
Peak memory 214660 kb
Host smart-7ba5d2df-b491-4b47-8dc5-f4833439ceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302101673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3302101673
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.312222671
Short name T1262
Test name
Test status
Simulation time 1004656969 ps
CPU time 2.5 seconds
Started Mar 12 02:41:38 PM PDT 24
Finished Mar 12 02:41:41 PM PDT 24
Peak memory 203620 kb
Host smart-69d929a0-929e-4218-b94a-2cf4ad1483b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312222671 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.312222671
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.430186260
Short name T335
Test name
Test status
Simulation time 10273193514 ps
CPU time 24.85 seconds
Started Mar 12 02:41:39 PM PDT 24
Finished Mar 12 02:42:04 PM PDT 24
Peak memory 357688 kb
Host smart-4271b4a7-2a07-48b2-bd1f-1ee9dfb73f04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430186260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.430186260
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.674131852
Short name T991
Test name
Test status
Simulation time 1937271549 ps
CPU time 2.67 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:39 PM PDT 24
Peak memory 203548 kb
Host smart-08f5af6d-1219-4efd-9c16-a16fb54e770a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674131852 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.674131852
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1384386014
Short name T469
Test name
Test status
Simulation time 17955188374 ps
CPU time 264.55 seconds
Started Mar 12 02:41:29 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 2841968 kb
Host smart-79794ab6-937d-402b-95d2-30cd513f9f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384386014 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1384386014
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.315873626
Short name T768
Test name
Test status
Simulation time 2020993059 ps
CPU time 3.2 seconds
Started Mar 12 02:41:38 PM PDT 24
Finished Mar 12 02:41:41 PM PDT 24
Peak memory 207520 kb
Host smart-ddceb8c4-fda4-4a34-8939-f1bf1fd2dcf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315873626 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_perf.315873626
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3634128531
Short name T952
Test name
Test status
Simulation time 66456364529 ps
CPU time 99.63 seconds
Started Mar 12 02:41:28 PM PDT 24
Finished Mar 12 02:43:08 PM PDT 24
Peak memory 1394944 kb
Host smart-e774d154-8ea6-4979-b11f-fdcd2219b584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634128531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3634128531
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1552194137
Short name T563
Test name
Test status
Simulation time 15606805027 ps
CPU time 812.17 seconds
Started Mar 12 02:41:30 PM PDT 24
Finished Mar 12 02:55:02 PM PDT 24
Peak memory 3784124 kb
Host smart-fcc583c0-6d06-4c0c-873c-2c184ac365eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552194137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1552194137
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2423104278
Short name T617
Test name
Test status
Simulation time 3867986461 ps
CPU time 6.29 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:44 PM PDT 24
Peak memory 203640 kb
Host smart-fabf3e0b-c040-4c4a-bf5b-023515ea5b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423104278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2423104278
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.408362605
Short name T992
Test name
Test status
Simulation time 4190145248 ps
CPU time 5.92 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:43 PM PDT 24
Peak memory 203600 kb
Host smart-f60fbd61-3c85-4703-89c7-ecf25e9ea9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408362605 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_unexp_stop.408362605
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3113213503
Short name T567
Test name
Test status
Simulation time 23975204 ps
CPU time 0.63 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:41:48 PM PDT 24
Peak memory 202344 kb
Host smart-1531ca2a-3c35-4bc5-be6e-90ba2493535f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113213503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3113213503
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3170154563
Short name T826
Test name
Test status
Simulation time 335287955 ps
CPU time 1.67 seconds
Started Mar 12 02:41:47 PM PDT 24
Finished Mar 12 02:41:49 PM PDT 24
Peak memory 211708 kb
Host smart-8a59d113-f0d9-4409-9ed7-2f4e64fd1e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170154563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3170154563
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2458230039
Short name T734
Test name
Test status
Simulation time 1223531381 ps
CPU time 15.82 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 266944 kb
Host smart-971d72a9-35de-466f-8a06-061030569342
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458230039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2458230039
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1560610913
Short name T685
Test name
Test status
Simulation time 1617211155 ps
CPU time 112.63 seconds
Started Mar 12 02:41:41 PM PDT 24
Finished Mar 12 02:43:34 PM PDT 24
Peak memory 592188 kb
Host smart-97121625-6fb4-4ee7-8258-13ef65e9c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560610913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1560610913
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.413346558
Short name T635
Test name
Test status
Simulation time 2201596015 ps
CPU time 147.71 seconds
Started Mar 12 02:41:35 PM PDT 24
Finished Mar 12 02:44:03 PM PDT 24
Peak memory 686688 kb
Host smart-9d440bd4-0673-4729-afa8-8de9a47a6d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413346558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.413346558
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3079032514
Short name T988
Test name
Test status
Simulation time 720971421 ps
CPU time 0.93 seconds
Started Mar 12 02:41:38 PM PDT 24
Finished Mar 12 02:41:39 PM PDT 24
Peak memory 203320 kb
Host smart-35b73e45-b297-435b-b876-3dd27737cf03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079032514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3079032514
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.4022658838
Short name T1170
Test name
Test status
Simulation time 189859337 ps
CPU time 4.76 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:42 PM PDT 24
Peak memory 239176 kb
Host smart-356c3f22-ead0-42c3-a81e-4e6d107b440d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022658838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.4022658838
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2146027159
Short name T582
Test name
Test status
Simulation time 6044364767 ps
CPU time 186.43 seconds
Started Mar 12 02:41:36 PM PDT 24
Finished Mar 12 02:44:42 PM PDT 24
Peak memory 1631256 kb
Host smart-19f8b24e-b58b-4ea7-948a-da742d4daf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146027159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2146027159
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2430828024
Short name T1105
Test name
Test status
Simulation time 8185991573 ps
CPU time 41.75 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:42:29 PM PDT 24
Peak memory 271340 kb
Host smart-5f069bd9-f990-4005-9021-34324359b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430828024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2430828024
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3236201858
Short name T989
Test name
Test status
Simulation time 18155391 ps
CPU time 0.65 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:41:38 PM PDT 24
Peak memory 202460 kb
Host smart-a2f9738f-aee5-48fc-b5de-d8f59819d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236201858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3236201858
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2513927336
Short name T687
Test name
Test status
Simulation time 3355740921 ps
CPU time 18.31 seconds
Started Mar 12 02:41:39 PM PDT 24
Finished Mar 12 02:41:58 PM PDT 24
Peak memory 222824 kb
Host smart-c8bc6872-7ced-4edc-8e63-09ce2a7e3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513927336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2513927336
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.842401092
Short name T1245
Test name
Test status
Simulation time 23323130293 ps
CPU time 42.38 seconds
Started Mar 12 02:41:37 PM PDT 24
Finished Mar 12 02:42:20 PM PDT 24
Peak memory 283320 kb
Host smart-4150980c-f373-4d23-98af-92ff819ab7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842401092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.842401092
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2952723765
Short name T108
Test name
Test status
Simulation time 2407453429 ps
CPU time 27.33 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:42:14 PM PDT 24
Peak memory 211836 kb
Host smart-b1607cb2-4495-4d96-9fa3-1a0219b80383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952723765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2952723765
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2480508154
Short name T15
Test name
Test status
Simulation time 10143386237 ps
CPU time 13.55 seconds
Started Mar 12 02:41:45 PM PDT 24
Finished Mar 12 02:41:59 PM PDT 24
Peak memory 294992 kb
Host smart-0db0d956-f1c4-4a93-bc55-1f4b0b48f021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480508154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2480508154
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3358075046
Short name T1260
Test name
Test status
Simulation time 10270778619 ps
CPU time 31.23 seconds
Started Mar 12 02:41:47 PM PDT 24
Finished Mar 12 02:42:18 PM PDT 24
Peak memory 452568 kb
Host smart-a86dd093-f44d-4f51-ade6-ca14d24a381a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358075046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3358075046
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3003741191
Short name T799
Test name
Test status
Simulation time 757264371 ps
CPU time 2.62 seconds
Started Mar 12 02:41:49 PM PDT 24
Finished Mar 12 02:41:52 PM PDT 24
Peak memory 203512 kb
Host smart-67b6f4be-1018-4a6e-ad98-c42660c59e65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003741191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3003741191
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1478149006
Short name T398
Test name
Test status
Simulation time 4866005896 ps
CPU time 5.69 seconds
Started Mar 12 02:41:48 PM PDT 24
Finished Mar 12 02:41:54 PM PDT 24
Peak memory 212980 kb
Host smart-532d1824-50c1-4903-b406-108c469c4046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478149006 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1478149006
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3053985489
Short name T925
Test name
Test status
Simulation time 5363356667 ps
CPU time 4.07 seconds
Started Mar 12 02:41:49 PM PDT 24
Finished Mar 12 02:41:54 PM PDT 24
Peak memory 203592 kb
Host smart-af2c4088-11da-4273-9390-0ac6a529208e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053985489 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3053985489
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.3522326320
Short name T1254
Test name
Test status
Simulation time 1129333610 ps
CPU time 3.66 seconds
Started Mar 12 02:41:49 PM PDT 24
Finished Mar 12 02:41:52 PM PDT 24
Peak memory 206552 kb
Host smart-ae890219-b5f6-4b6c-9fcb-d9debe71522b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522326320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.3522326320
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.2761153407
Short name T1060
Test name
Test status
Simulation time 20956961896 ps
CPU time 45.07 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:42:31 PM PDT 24
Peak memory 227768 kb
Host smart-27ca16d3-3a61-4a5a-8a8e-995227bd1ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761153407 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.2761153407
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.778490927
Short name T862
Test name
Test status
Simulation time 483463718 ps
CPU time 7.2 seconds
Started Mar 12 02:41:47 PM PDT 24
Finished Mar 12 02:41:54 PM PDT 24
Peak memory 204708 kb
Host smart-c9c942eb-a2fd-4008-be23-c93d645b303d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778490927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.778490927
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2607938073
Short name T1067
Test name
Test status
Simulation time 15814722794 ps
CPU time 5.24 seconds
Started Mar 12 02:41:47 PM PDT 24
Finished Mar 12 02:41:53 PM PDT 24
Peak memory 203584 kb
Host smart-eae5cf8e-b778-4d34-93e6-6099dd43fd7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607938073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2607938073
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.4226270062
Short name T850
Test name
Test status
Simulation time 20475998639 ps
CPU time 573.89 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:51:21 PM PDT 24
Peak memory 3734036 kb
Host smart-271acb60-5513-4388-880d-0302b98aaf87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226270062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.4226270062
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3164103587
Short name T1018
Test name
Test status
Simulation time 5839147620 ps
CPU time 6.54 seconds
Started Mar 12 02:41:48 PM PDT 24
Finished Mar 12 02:41:54 PM PDT 24
Peak memory 211352 kb
Host smart-5442f924-e839-41e4-b83a-6ee96bfaea55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164103587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3164103587
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.346624045
Short name T1015
Test name
Test status
Simulation time 6381162522 ps
CPU time 8.24 seconds
Started Mar 12 02:41:46 PM PDT 24
Finished Mar 12 02:41:55 PM PDT 24
Peak memory 210360 kb
Host smart-39c5a1b5-12d4-464b-8e05-4356b843cda6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346624045 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_unexp_stop.346624045
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1322251676
Short name T1265
Test name
Test status
Simulation time 67147097 ps
CPU time 0.62 seconds
Started Mar 12 02:42:12 PM PDT 24
Finished Mar 12 02:42:12 PM PDT 24
Peak memory 203220 kb
Host smart-dcf37bf6-45fd-48a1-a956-22657c3dc0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322251676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1322251676
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2811751654
Short name T692
Test name
Test status
Simulation time 66994828 ps
CPU time 1.16 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:41:55 PM PDT 24
Peak memory 219988 kb
Host smart-ff0c0a58-0342-4dff-aeff-5fce266dfc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811751654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2811751654
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3426655343
Short name T562
Test name
Test status
Simulation time 310646819 ps
CPU time 16.12 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:12 PM PDT 24
Peak memory 263728 kb
Host smart-c324c3eb-5539-4b7a-b2e3-e52a7bab3f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426655343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3426655343
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2418945652
Short name T1206
Test name
Test status
Simulation time 2204295806 ps
CPU time 124.49 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:43:59 PM PDT 24
Peak memory 635336 kb
Host smart-b6ee028a-f2c7-4242-ad7d-8983b9235af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418945652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2418945652
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3327087871
Short name T526
Test name
Test status
Simulation time 7687758384 ps
CPU time 236.63 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 912312 kb
Host smart-ad2b889c-9bc9-4fc9-aa24-67ce215f62ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327087871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3327087871
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1389326997
Short name T509
Test name
Test status
Simulation time 2097529726 ps
CPU time 0.92 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:41:56 PM PDT 24
Peak memory 203316 kb
Host smart-b70b54ea-13a6-4efd-ae91-4e5a15c5452f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389326997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1389326997
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3225471271
Short name T590
Test name
Test status
Simulation time 2268053935 ps
CPU time 11.08 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:07 PM PDT 24
Peak memory 203556 kb
Host smart-f16d30f5-192f-41f1-887f-3983c659e132
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225471271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3225471271
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2035555403
Short name T1117
Test name
Test status
Simulation time 3514206113 ps
CPU time 110.42 seconds
Started Mar 12 02:42:13 PM PDT 24
Finished Mar 12 02:44:04 PM PDT 24
Peak memory 267892 kb
Host smart-4c7f8724-1d18-45e3-aa74-03bd65bef5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035555403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2035555403
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1266128037
Short name T1000
Test name
Test status
Simulation time 50061275 ps
CPU time 0.62 seconds
Started Mar 12 02:41:49 PM PDT 24
Finished Mar 12 02:41:50 PM PDT 24
Peak memory 202504 kb
Host smart-2d8aaa55-95e9-485e-a880-0af27a2231f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266128037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1266128037
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2457294225
Short name T1077
Test name
Test status
Simulation time 725925049 ps
CPU time 2.28 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:41:58 PM PDT 24
Peak memory 211728 kb
Host smart-ebdff690-aeba-4d6e-935d-e4729df77ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457294225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2457294225
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2654731611
Short name T924
Test name
Test status
Simulation time 1770408418 ps
CPU time 94.65 seconds
Started Mar 12 02:41:47 PM PDT 24
Finished Mar 12 02:43:22 PM PDT 24
Peak memory 235720 kb
Host smart-ffec437a-7071-4e7e-aff5-b2f4bb3dfdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654731611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2654731611
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4265964395
Short name T71
Test name
Test status
Simulation time 50064564322 ps
CPU time 1757.44 seconds
Started Mar 12 02:42:00 PM PDT 24
Finished Mar 12 03:11:18 PM PDT 24
Peak memory 2552464 kb
Host smart-ca48c31a-4729-4552-8357-db2087ea554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265964395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4265964395
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1151271133
Short name T1107
Test name
Test status
Simulation time 5703617585 ps
CPU time 40.99 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:36 PM PDT 24
Peak memory 211744 kb
Host smart-2104ee56-9ad3-4427-b6d2-7d10550ec547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151271133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1151271133
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2099204311
Short name T866
Test name
Test status
Simulation time 1616498397 ps
CPU time 4.02 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:41:59 PM PDT 24
Peak memory 203560 kb
Host smart-8d859c76-1045-445c-a1d4-742399677b6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099204311 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2099204311
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1341877327
Short name T1084
Test name
Test status
Simulation time 10026985447 ps
CPU time 89.55 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:43:24 PM PDT 24
Peak memory 662440 kb
Host smart-731d8c8a-88ed-4ad1-aa87-3cc05094a07f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341877327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1341877327
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.788334806
Short name T577
Test name
Test status
Simulation time 339882828 ps
CPU time 1.9 seconds
Started Mar 12 02:41:57 PM PDT 24
Finished Mar 12 02:41:59 PM PDT 24
Peak memory 203532 kb
Host smart-e6e42873-b2c3-4dc2-b886-48cf52477fad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788334806 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.788334806
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3621242256
Short name T325
Test name
Test status
Simulation time 1818248256 ps
CPU time 4.75 seconds
Started Mar 12 02:41:53 PM PDT 24
Finished Mar 12 02:41:58 PM PDT 24
Peak memory 206896 kb
Host smart-32d50af0-d01d-406a-bab1-1c69f3e27c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621242256 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3621242256
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1622039836
Short name T1085
Test name
Test status
Simulation time 21300050691 ps
CPU time 59.84 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:55 PM PDT 24
Peak memory 878348 kb
Host smart-e4cfc0b0-74e1-4771-924d-5767a18101fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622039836 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1622039836
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.3984687259
Short name T681
Test name
Test status
Simulation time 664933049 ps
CPU time 3.88 seconds
Started Mar 12 02:41:57 PM PDT 24
Finished Mar 12 02:42:01 PM PDT 24
Peak memory 203896 kb
Host smart-10647c78-e30a-4544-858f-d19dd7d260ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984687259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.3984687259
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2790856860
Short name T658
Test name
Test status
Simulation time 1653396945 ps
CPU time 22.97 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:19 PM PDT 24
Peak memory 203536 kb
Host smart-0c1b0d1a-caf9-4a66-85ba-15eb1e54be97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790856860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2790856860
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.107190061
Short name T997
Test name
Test status
Simulation time 49327930804 ps
CPU time 103.03 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:43:38 PM PDT 24
Peak memory 847280 kb
Host smart-2a0e822e-6fae-4926-bec1-cb101c7ab9a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107190061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.107190061
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3366403428
Short name T728
Test name
Test status
Simulation time 17986285281 ps
CPU time 10.88 seconds
Started Mar 12 02:41:54 PM PDT 24
Finished Mar 12 02:42:05 PM PDT 24
Peak memory 203652 kb
Host smart-256803e2-85d9-4f3f-a55c-cea73692685d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366403428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3366403428
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3501652974
Short name T570
Test name
Test status
Simulation time 29183582296 ps
CPU time 2663.51 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 03:26:19 PM PDT 24
Peak memory 6850736 kb
Host smart-1a9e3ef3-c060-4221-9820-fbdf862ab422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501652974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3501652974
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1436613485
Short name T1169
Test name
Test status
Simulation time 2860403930 ps
CPU time 7.22 seconds
Started Mar 12 02:41:55 PM PDT 24
Finished Mar 12 02:42:03 PM PDT 24
Peak memory 211684 kb
Host smart-271d0281-b1e9-4d09-a2aa-9103886eda30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436613485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1436613485
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.700858147
Short name T1029
Test name
Test status
Simulation time 3244380631 ps
CPU time 4.3 seconds
Started Mar 12 02:41:53 PM PDT 24
Finished Mar 12 02:41:58 PM PDT 24
Peak memory 203648 kb
Host smart-8b54826b-1c0e-4e5e-a857-cd719c6597f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700858147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_unexp_stop.700858147
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1729753413
Short name T324
Test name
Test status
Simulation time 25453846 ps
CPU time 0.6 seconds
Started Mar 12 02:42:27 PM PDT 24
Finished Mar 12 02:42:28 PM PDT 24
Peak memory 202336 kb
Host smart-cafd42ac-350e-4ad2-97ed-0d8c9eebd51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729753413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1729753413
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1813757135
Short name T63
Test name
Test status
Simulation time 67274586 ps
CPU time 1.71 seconds
Started Mar 12 02:42:06 PM PDT 24
Finished Mar 12 02:42:08 PM PDT 24
Peak memory 219904 kb
Host smart-70c0b28a-05a2-4910-be1a-cc9390ad76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813757135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1813757135
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3265635758
Short name T724
Test name
Test status
Simulation time 269209995 ps
CPU time 13.21 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:42:30 PM PDT 24
Peak memory 250820 kb
Host smart-9dafce1b-8e50-4194-bf5b-fd0818f3c273
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265635758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3265635758
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3922607244
Short name T209
Test name
Test status
Simulation time 3136997769 ps
CPU time 123.78 seconds
Started Mar 12 02:42:12 PM PDT 24
Finished Mar 12 02:44:16 PM PDT 24
Peak memory 945784 kb
Host smart-2e1a3b30-7896-4f50-9f5a-0ea6658f266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922607244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3922607244
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3449121536
Short name T422
Test name
Test status
Simulation time 8023900366 ps
CPU time 101.94 seconds
Started Mar 12 02:42:06 PM PDT 24
Finished Mar 12 02:43:48 PM PDT 24
Peak memory 985224 kb
Host smart-f9b3a7ea-0318-48c8-a8d1-5f004f8a1daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449121536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3449121536
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2268964224
Short name T1040
Test name
Test status
Simulation time 228403293 ps
CPU time 1.05 seconds
Started Mar 12 02:42:07 PM PDT 24
Finished Mar 12 02:42:08 PM PDT 24
Peak memory 203456 kb
Host smart-17f05e50-1314-4e02-b5ff-9d8f7a4e91d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268964224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2268964224
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1552464426
Short name T1140
Test name
Test status
Simulation time 147587400 ps
CPU time 8.81 seconds
Started Mar 12 02:42:12 PM PDT 24
Finished Mar 12 02:42:21 PM PDT 24
Peak memory 228732 kb
Host smart-07248860-cf98-41ea-8ad4-1016d2c3b5ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552464426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1552464426
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1049360542
Short name T144
Test name
Test status
Simulation time 5742250380 ps
CPU time 156.62 seconds
Started Mar 12 02:42:11 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 1627880 kb
Host smart-3f49d249-0927-44a7-bdb3-d39b94caaea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049360542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1049360542
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.578794881
Short name T1263
Test name
Test status
Simulation time 5394596051 ps
CPU time 30.54 seconds
Started Mar 12 02:42:15 PM PDT 24
Finished Mar 12 02:42:46 PM PDT 24
Peak memory 242348 kb
Host smart-2c83d4f8-4f2e-4dc3-a437-dc43655d97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578794881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.578794881
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1427414025
Short name T517
Test name
Test status
Simulation time 167750441 ps
CPU time 0.6 seconds
Started Mar 12 02:42:11 PM PDT 24
Finished Mar 12 02:42:12 PM PDT 24
Peak memory 202568 kb
Host smart-b38fdf88-9203-4250-965d-54936f43fcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427414025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1427414025
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2823278197
Short name T944
Test name
Test status
Simulation time 7174568715 ps
CPU time 348.06 seconds
Started Mar 12 02:42:13 PM PDT 24
Finished Mar 12 02:48:01 PM PDT 24
Peak memory 219500 kb
Host smart-1fc7ae1c-f630-428c-b062-0625f69080cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823278197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2823278197
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2554104125
Short name T363
Test name
Test status
Simulation time 3261970501 ps
CPU time 108.68 seconds
Started Mar 12 02:42:07 PM PDT 24
Finished Mar 12 02:43:56 PM PDT 24
Peak memory 266912 kb
Host smart-16960824-57b2-4edd-ab67-5f040321ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554104125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2554104125
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2582639773
Short name T487
Test name
Test status
Simulation time 704641582 ps
CPU time 33.16 seconds
Started Mar 12 02:42:09 PM PDT 24
Finished Mar 12 02:42:42 PM PDT 24
Peak memory 211780 kb
Host smart-868904e9-1f37-468e-a75f-6526a39314bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582639773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2582639773
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.4216938538
Short name T772
Test name
Test status
Simulation time 3536827605 ps
CPU time 3.54 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:42:20 PM PDT 24
Peak memory 203640 kb
Host smart-c7dff1dd-5e33-42dc-957b-2b9097a1508c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216938538 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.4216938538
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1036732048
Short name T235
Test name
Test status
Simulation time 10159232119 ps
CPU time 28.78 seconds
Started Mar 12 02:42:22 PM PDT 24
Finished Mar 12 02:42:51 PM PDT 24
Peak memory 374256 kb
Host smart-8a60bc0c-71d2-40f5-9cc9-629e2068bf67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036732048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1036732048
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1447557019
Short name T58
Test name
Test status
Simulation time 1501774991 ps
CPU time 2.18 seconds
Started Mar 12 02:42:15 PM PDT 24
Finished Mar 12 02:42:17 PM PDT 24
Peak memory 203640 kb
Host smart-130dad5e-6ce1-4493-86ff-77d76ceacce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447557019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1447557019
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3935391841
Short name T608
Test name
Test status
Simulation time 1478561379 ps
CPU time 5.78 seconds
Started Mar 12 02:42:12 PM PDT 24
Finished Mar 12 02:42:18 PM PDT 24
Peak memory 203636 kb
Host smart-30cf5669-26ae-4bb5-b235-f2fdc60f825f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935391841 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3935391841
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2300906635
Short name T51
Test name
Test status
Simulation time 16424641105 ps
CPU time 42.92 seconds
Started Mar 12 02:42:06 PM PDT 24
Finished Mar 12 02:42:50 PM PDT 24
Peak memory 817068 kb
Host smart-d090f85c-9559-4334-be0f-a251184b5564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300906635 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2300906635
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.3454538480
Short name T296
Test name
Test status
Simulation time 859923430 ps
CPU time 4.95 seconds
Started Mar 12 02:42:17 PM PDT 24
Finished Mar 12 02:42:22 PM PDT 24
Peak memory 205600 kb
Host smart-8b101fee-329f-4e42-9df4-9151f91ec803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454538480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.3454538480
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2263708144
Short name T410
Test name
Test status
Simulation time 775951048 ps
CPU time 20.48 seconds
Started Mar 12 02:42:06 PM PDT 24
Finished Mar 12 02:42:27 PM PDT 24
Peak memory 203452 kb
Host smart-bd7f3179-546b-43cc-94ad-80c49277bc60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263708144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2263708144
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2784127945
Short name T471
Test name
Test status
Simulation time 852330596 ps
CPU time 19.33 seconds
Started Mar 12 02:42:08 PM PDT 24
Finished Mar 12 02:42:27 PM PDT 24
Peak memory 203556 kb
Host smart-415a0ce7-2002-4018-b147-a7c46ec7d859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784127945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2784127945
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2543673504
Short name T720
Test name
Test status
Simulation time 36950389544 ps
CPU time 146.63 seconds
Started Mar 12 02:42:13 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 2158868 kb
Host smart-1db9bc9c-c45d-4b63-8610-4641863399ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543673504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2543673504
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.4094795575
Short name T996
Test name
Test status
Simulation time 4986945172 ps
CPU time 130.91 seconds
Started Mar 12 02:42:12 PM PDT 24
Finished Mar 12 02:44:23 PM PDT 24
Peak memory 709832 kb
Host smart-6c9549d6-ae32-4054-8830-0689553658eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094795575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.4094795575
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3175143484
Short name T802
Test name
Test status
Simulation time 19351144054 ps
CPU time 7.42 seconds
Started Mar 12 02:42:07 PM PDT 24
Finished Mar 12 02:42:15 PM PDT 24
Peak memory 216920 kb
Host smart-7731603c-9d7a-48ff-a57e-a76d8f1f2a0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175143484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3175143484
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.1466000769
Short name T1231
Test name
Test status
Simulation time 3056181040 ps
CPU time 8.2 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:42:24 PM PDT 24
Peak memory 205512 kb
Host smart-e03bcd5d-42db-4199-8186-ddec64d738cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466000769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.1466000769
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1494743048
Short name T1188
Test name
Test status
Simulation time 44486265 ps
CPU time 0.59 seconds
Started Mar 12 02:42:24 PM PDT 24
Finished Mar 12 02:42:24 PM PDT 24
Peak memory 202392 kb
Host smart-1c5d7a5d-4bd4-43b0-a675-19a4efb678f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494743048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1494743048
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.56151155
Short name T367
Test name
Test status
Simulation time 117256995 ps
CPU time 1.07 seconds
Started Mar 12 02:42:27 PM PDT 24
Finished Mar 12 02:42:29 PM PDT 24
Peak memory 211648 kb
Host smart-3bcb0a7a-f179-4b83-9dc5-524160c3c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56151155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.56151155
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1281641175
Short name T1216
Test name
Test status
Simulation time 356905848 ps
CPU time 7 seconds
Started Mar 12 02:42:18 PM PDT 24
Finished Mar 12 02:42:26 PM PDT 24
Peak memory 277348 kb
Host smart-316d79cf-c2d3-42b8-867f-d5345f982bd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281641175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1281641175
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4131764846
Short name T27
Test name
Test status
Simulation time 18242436391 ps
CPU time 117.21 seconds
Started Mar 12 02:42:21 PM PDT 24
Finished Mar 12 02:44:18 PM PDT 24
Peak memory 612876 kb
Host smart-f5f93d51-6ee3-4d27-9085-ab6387f3efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131764846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4131764846
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2050653080
Short name T226
Test name
Test status
Simulation time 15960618584 ps
CPU time 62.02 seconds
Started Mar 12 02:42:26 PM PDT 24
Finished Mar 12 02:43:28 PM PDT 24
Peak memory 638984 kb
Host smart-ce618278-81c9-4605-8cec-72308fb91951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050653080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2050653080
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2503797854
Short name T792
Test name
Test status
Simulation time 133527197 ps
CPU time 0.99 seconds
Started Mar 12 02:42:21 PM PDT 24
Finished Mar 12 02:42:22 PM PDT 24
Peak memory 203228 kb
Host smart-eaa5d2df-1dea-4983-b5e2-2b7cfb570db8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503797854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2503797854
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1444218544
Short name T348
Test name
Test status
Simulation time 152399236 ps
CPU time 7.36 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:42:23 PM PDT 24
Peak memory 225060 kb
Host smart-114356a4-647c-421f-851f-df03b8321c28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444218544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1444218544
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1359392982
Short name T281
Test name
Test status
Simulation time 21498327450 ps
CPU time 127.43 seconds
Started Mar 12 02:42:17 PM PDT 24
Finished Mar 12 02:44:25 PM PDT 24
Peak memory 1221072 kb
Host smart-e6466540-7190-450d-84f3-5a55ae512d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359392982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1359392982
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3568013768
Short name T341
Test name
Test status
Simulation time 2066043015 ps
CPU time 98.55 seconds
Started Mar 12 02:42:26 PM PDT 24
Finished Mar 12 02:44:04 PM PDT 24
Peak memory 214744 kb
Host smart-8aa99536-0cef-4916-bad2-a71e455af24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568013768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3568013768
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2839828255
Short name T1118
Test name
Test status
Simulation time 24276468 ps
CPU time 0.63 seconds
Started Mar 12 02:42:15 PM PDT 24
Finished Mar 12 02:42:16 PM PDT 24
Peak memory 202536 kb
Host smart-5e2e1b00-82c9-4965-921f-eb465d8ac2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839828255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2839828255
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.639892184
Short name T1093
Test name
Test status
Simulation time 7243069230 ps
CPU time 101.55 seconds
Started Mar 12 02:42:27 PM PDT 24
Finished Mar 12 02:44:09 PM PDT 24
Peak memory 214472 kb
Host smart-47215e21-a732-45aa-bfcc-eeab7e2a2ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639892184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.639892184
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.84816932
Short name T836
Test name
Test status
Simulation time 9348001994 ps
CPU time 130.85 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:44:27 PM PDT 24
Peak memory 248696 kb
Host smart-c5c898e9-9b34-4bd2-8224-efc4ca928ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84816932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.84816932
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3273447579
Short name T214
Test name
Test status
Simulation time 9489452050 ps
CPU time 343.07 seconds
Started Mar 12 02:42:17 PM PDT 24
Finished Mar 12 02:48:01 PM PDT 24
Peak memory 1555600 kb
Host smart-576b9113-3a1a-4008-be1d-691e33a57afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273447579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3273447579
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2689968991
Short name T628
Test name
Test status
Simulation time 437091726 ps
CPU time 6.41 seconds
Started Mar 12 02:42:16 PM PDT 24
Finished Mar 12 02:42:22 PM PDT 24
Peak memory 218388 kb
Host smart-4cf38bdb-1da1-405a-acf3-7471dec8a675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689968991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2689968991
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2225799284
Short name T835
Test name
Test status
Simulation time 10220314840 ps
CPU time 30.54 seconds
Started Mar 12 02:42:23 PM PDT 24
Finished Mar 12 02:42:54 PM PDT 24
Peak memory 448380 kb
Host smart-5f7883db-2a5e-4181-acb3-64ea7f7a4dc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225799284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2225799284
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1657568135
Short name T831
Test name
Test status
Simulation time 2286363130 ps
CPU time 1.74 seconds
Started Mar 12 02:42:29 PM PDT 24
Finished Mar 12 02:42:31 PM PDT 24
Peak memory 203624 kb
Host smart-4529fb2d-4803-4522-83aa-129bc47b1120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657568135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1657568135
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3316091092
Short name T781
Test name
Test status
Simulation time 893577676 ps
CPU time 4.03 seconds
Started Mar 12 02:42:17 PM PDT 24
Finished Mar 12 02:42:21 PM PDT 24
Peak memory 203628 kb
Host smart-5c14718b-f9f1-4207-8a99-5eed4907f29b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316091092 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3316091092
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1823009059
Short name T286
Test name
Test status
Simulation time 5371892249 ps
CPU time 6.36 seconds
Started Mar 12 02:42:17 PM PDT 24
Finished Mar 12 02:42:23 PM PDT 24
Peak memory 203608 kb
Host smart-e19dde29-d2fb-48eb-ac8e-4c885bfdfac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823009059 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1823009059
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.4177744410
Short name T1028
Test name
Test status
Simulation time 3617025308 ps
CPU time 3.99 seconds
Started Mar 12 02:42:25 PM PDT 24
Finished Mar 12 02:42:29 PM PDT 24
Peak memory 208012 kb
Host smart-4c4a9be0-1dd6-48ef-984e-4437b46fc7b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177744410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.4177744410
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2728946508
Short name T675
Test name
Test status
Simulation time 38596170353 ps
CPU time 172.17 seconds
Started Mar 12 02:42:19 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 2507660 kb
Host smart-9256391a-274d-4c27-a4ea-cc775f0dbcd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728946508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2728946508
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1554540256
Short name T798
Test name
Test status
Simulation time 12491874938 ps
CPU time 60 seconds
Started Mar 12 02:42:18 PM PDT 24
Finished Mar 12 02:43:18 PM PDT 24
Peak memory 900992 kb
Host smart-669c3300-2897-45e3-aef0-071e8a5986ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554540256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1554540256
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2501746472
Short name T288
Test name
Test status
Simulation time 16837574 ps
CPU time 0.61 seconds
Started Mar 12 02:42:35 PM PDT 24
Finished Mar 12 02:42:36 PM PDT 24
Peak memory 202364 kb
Host smart-f706e881-f5d7-4b1e-9d05-c24fba931775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501746472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2501746472
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2021833342
Short name T1259
Test name
Test status
Simulation time 58586344 ps
CPU time 1.63 seconds
Started Mar 12 02:42:36 PM PDT 24
Finished Mar 12 02:42:38 PM PDT 24
Peak memory 211796 kb
Host smart-671cf9cf-3f81-48f6-ab74-8ff2c0159653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021833342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2021833342
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4100747756
Short name T356
Test name
Test status
Simulation time 3364188299 ps
CPU time 7.98 seconds
Started Mar 12 02:42:29 PM PDT 24
Finished Mar 12 02:42:37 PM PDT 24
Peak memory 277632 kb
Host smart-85e353f7-51ec-4b3e-805f-d806a53c4ef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100747756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4100747756
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1451686267
Short name T543
Test name
Test status
Simulation time 2385092533 ps
CPU time 144.27 seconds
Started Mar 12 02:42:24 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 620312 kb
Host smart-00a35b36-21b3-49c8-a482-56cf3a4f24ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451686267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1451686267
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2333938503
Short name T242
Test name
Test status
Simulation time 1910265954 ps
CPU time 143.16 seconds
Started Mar 12 02:42:26 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 678048 kb
Host smart-4bcfb94d-0c0f-4a29-aa12-dccd5ab0cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333938503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2333938503
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.937562923
Short name T182
Test name
Test status
Simulation time 2205577509 ps
CPU time 0.97 seconds
Started Mar 12 02:42:24 PM PDT 24
Finished Mar 12 02:42:25 PM PDT 24
Peak memory 203340 kb
Host smart-aaa99498-ed74-40c9-815c-92cd93646c5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937562923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fm
t.937562923
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1893859688
Short name T977
Test name
Test status
Simulation time 847866166 ps
CPU time 5.17 seconds
Started Mar 12 02:42:25 PM PDT 24
Finished Mar 12 02:42:30 PM PDT 24
Peak memory 233824 kb
Host smart-3299374b-c338-40e8-9672-8ac8c6768104
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893859688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1893859688
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.854289438
Short name T546
Test name
Test status
Simulation time 5716653408 ps
CPU time 188.95 seconds
Started Mar 12 02:42:33 PM PDT 24
Finished Mar 12 02:45:42 PM PDT 24
Peak memory 1597684 kb
Host smart-a81a7171-3abb-48f7-ad56-23406c7cb48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854289438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.854289438
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3557789866
Short name T932
Test name
Test status
Simulation time 1629320595 ps
CPU time 85.9 seconds
Started Mar 12 02:42:33 PM PDT 24
Finished Mar 12 02:43:59 PM PDT 24
Peak memory 233124 kb
Host smart-e9780b22-9906-40e9-9256-3899abbdcb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557789866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3557789866
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3668062058
Short name T359
Test name
Test status
Simulation time 18275041 ps
CPU time 0.63 seconds
Started Mar 12 02:42:23 PM PDT 24
Finished Mar 12 02:42:24 PM PDT 24
Peak memory 203204 kb
Host smart-974c28eb-8d46-4bf0-9090-1f4530529404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668062058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3668062058
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2405064388
Short name T1110
Test name
Test status
Simulation time 717373753 ps
CPU time 6.16 seconds
Started Mar 12 02:42:22 PM PDT 24
Finished Mar 12 02:42:28 PM PDT 24
Peak memory 219892 kb
Host smart-e635f78c-6f27-4336-82c2-e702accf894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405064388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2405064388
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.587715047
Short name T733
Test name
Test status
Simulation time 4827996102 ps
CPU time 22.93 seconds
Started Mar 12 02:42:29 PM PDT 24
Finished Mar 12 02:42:52 PM PDT 24
Peak memory 211848 kb
Host smart-cac378da-927b-4d08-af28-276e46387b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587715047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.587715047
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1483905491
Short name T213
Test name
Test status
Simulation time 34593695752 ps
CPU time 1028.99 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:59:40 PM PDT 24
Peak memory 2942776 kb
Host smart-fd281ba3-d13f-4bcd-8029-3c3fbf893171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483905491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1483905491
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1009262495
Short name T757
Test name
Test status
Simulation time 760020863 ps
CPU time 12.28 seconds
Started Mar 12 02:42:27 PM PDT 24
Finished Mar 12 02:42:40 PM PDT 24
Peak memory 212452 kb
Host smart-6d013258-d7ec-4aba-b2ae-82d76b03c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009262495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1009262495
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1239643957
Short name T477
Test name
Test status
Simulation time 1111273929 ps
CPU time 4.55 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:42:36 PM PDT 24
Peak memory 203588 kb
Host smart-f6889748-fd5e-4a7d-90b2-11cfa0bd094f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239643957 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1239643957
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.4202888650
Short name T307
Test name
Test status
Simulation time 10210977515 ps
CPU time 12.28 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:42:43 PM PDT 24
Peak memory 264772 kb
Host smart-472c6d2b-1513-4d1e-a0f3-ef7fec34bd77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202888650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.4202888650
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2653706785
Short name T270
Test name
Test status
Simulation time 9034251342 ps
CPU time 3.85 seconds
Started Mar 12 02:42:30 PM PDT 24
Finished Mar 12 02:42:34 PM PDT 24
Peak memory 203636 kb
Host smart-f4d5af3a-8580-46ba-84b6-a6cdfbaeb99d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653706785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2653706785
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_perf.2713245122
Short name T1229
Test name
Test status
Simulation time 2507266290 ps
CPU time 3.63 seconds
Started Mar 12 02:42:30 PM PDT 24
Finished Mar 12 02:42:34 PM PDT 24
Peak memory 203600 kb
Host smart-075cc159-8a1d-4b24-8e30-482536d6359d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713245122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.2713245122
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3810525467
Short name T506
Test name
Test status
Simulation time 1542426791 ps
CPU time 42.13 seconds
Started Mar 12 02:42:32 PM PDT 24
Finished Mar 12 02:43:15 PM PDT 24
Peak memory 203456 kb
Host smart-5f7ce48c-8dc9-461f-890d-8e2cd26254ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810525467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3810525467
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1134128389
Short name T322
Test name
Test status
Simulation time 48555762462 ps
CPU time 137.96 seconds
Started Mar 12 02:42:36 PM PDT 24
Finished Mar 12 02:44:54 PM PDT 24
Peak memory 1822256 kb
Host smart-cdf6423b-8f44-4850-8c63-ea293f06110b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134128389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1134128389
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2751153022
Short name T600
Test name
Test status
Simulation time 24846476388 ps
CPU time 1094.29 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 03:00:45 PM PDT 24
Peak memory 5402744 kb
Host smart-bd3d22b2-4bec-4f39-b44f-6eef6416b39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751153022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2751153022
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.809079950
Short name T1167
Test name
Test status
Simulation time 2199748231 ps
CPU time 5.71 seconds
Started Mar 12 02:42:32 PM PDT 24
Finished Mar 12 02:42:38 PM PDT 24
Peak memory 203632 kb
Host smart-2853121f-6599-4f7a-bab6-1f9f9b26a5ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809079950 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.809079950
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.4238130468
Short name T886
Test name
Test status
Simulation time 1202127483 ps
CPU time 7.42 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:42:39 PM PDT 24
Peak memory 203584 kb
Host smart-32670d9b-3336-4e69-9cf9-4667bc781057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238130468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.4238130468
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2132937237
Short name T518
Test name
Test status
Simulation time 17494656 ps
CPU time 0.62 seconds
Started Mar 12 02:42:39 PM PDT 24
Finished Mar 12 02:42:40 PM PDT 24
Peak memory 202356 kb
Host smart-cd57192e-8fd2-482c-9c3b-b6f13eb42268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132937237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2132937237
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.24922461
Short name T559
Test name
Test status
Simulation time 35036532 ps
CPU time 1.11 seconds
Started Mar 12 02:42:40 PM PDT 24
Finished Mar 12 02:42:41 PM PDT 24
Peak memory 203576 kb
Host smart-03bf47df-ed8c-42ed-9c23-54154ae8ceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24922461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.24922461
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.249328933
Short name T984
Test name
Test status
Simulation time 439250059 ps
CPU time 3.39 seconds
Started Mar 12 02:42:34 PM PDT 24
Finished Mar 12 02:42:38 PM PDT 24
Peak memory 235292 kb
Host smart-48aaf173-3b56-46ae-85eb-e75d37c644be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249328933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.249328933
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1249019897
Short name T208
Test name
Test status
Simulation time 6137247015 ps
CPU time 119.32 seconds
Started Mar 12 02:42:35 PM PDT 24
Finished Mar 12 02:44:35 PM PDT 24
Peak memory 954332 kb
Host smart-68ddb332-aa5e-4b08-a56b-ce06f3cb46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249019897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1249019897
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3995798386
Short name T1261
Test name
Test status
Simulation time 6179421361 ps
CPU time 101.04 seconds
Started Mar 12 02:42:36 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 943892 kb
Host smart-926d6f66-7539-4de2-9c20-dc6eabd354af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995798386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3995798386
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.794126772
Short name T686
Test name
Test status
Simulation time 141949109 ps
CPU time 1.08 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:42:32 PM PDT 24
Peak memory 203520 kb
Host smart-44ee2c8b-82e0-4da5-a154-33a66b9207a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794126772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.794126772
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3634618298
Short name T479
Test name
Test status
Simulation time 173779779 ps
CPU time 4.25 seconds
Started Mar 12 02:42:32 PM PDT 24
Finished Mar 12 02:42:37 PM PDT 24
Peak memory 203568 kb
Host smart-bfff04d0-1eaa-4747-9084-b056ce2caca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634618298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3634618298
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1074074322
Short name T719
Test name
Test status
Simulation time 62462214669 ps
CPU time 167.85 seconds
Started Mar 12 02:42:36 PM PDT 24
Finished Mar 12 02:45:24 PM PDT 24
Peak memory 1633608 kb
Host smart-1a52d78b-0411-4942-9367-5e86eff29973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074074322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1074074322
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2004328915
Short name T632
Test name
Test status
Simulation time 8770382915 ps
CPU time 148.45 seconds
Started Mar 12 02:42:42 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 448344 kb
Host smart-0f2aad0a-ec6a-40b1-8a53-dd9101493c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004328915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2004328915
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.83157408
Short name T1090
Test name
Test status
Simulation time 55621266 ps
CPU time 0.66 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:42:32 PM PDT 24
Peak memory 202624 kb
Host smart-34321a12-fd1b-4680-bdbb-2ff322de574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83157408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.83157408
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1896233086
Short name T1007
Test name
Test status
Simulation time 14885406323 ps
CPU time 183.58 seconds
Started Mar 12 02:42:30 PM PDT 24
Finished Mar 12 02:45:34 PM PDT 24
Peak memory 236024 kb
Host smart-4a0df521-cd3a-4be3-8444-7465572a7de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896233086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1896233086
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2684011525
Short name T500
Test name
Test status
Simulation time 1811488137 ps
CPU time 46.48 seconds
Started Mar 12 02:42:31 PM PDT 24
Finished Mar 12 02:43:17 PM PDT 24
Peak memory 297656 kb
Host smart-ab8fdced-5be9-45bb-b06b-a921837afd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684011525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2684011525
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3963684555
Short name T22
Test name
Test status
Simulation time 17571148980 ps
CPU time 1682.67 seconds
Started Mar 12 02:42:42 PM PDT 24
Finished Mar 12 03:10:45 PM PDT 24
Peak memory 2599876 kb
Host smart-c831d2db-8350-4199-be97-ad7c9d2d2989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963684555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3963684555
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2878130580
Short name T1062
Test name
Test status
Simulation time 3486501339 ps
CPU time 7.06 seconds
Started Mar 12 02:42:42 PM PDT 24
Finished Mar 12 02:42:49 PM PDT 24
Peak memory 212716 kb
Host smart-430c8bb3-9a9b-4bb3-9835-6ad61640c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878130580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2878130580
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1741357640
Short name T1153
Test name
Test status
Simulation time 734026437 ps
CPU time 3.36 seconds
Started Mar 12 02:42:43 PM PDT 24
Finished Mar 12 02:42:46 PM PDT 24
Peak memory 203484 kb
Host smart-e1abe65a-792c-4c42-a403-e02eb1bd284d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741357640 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1741357640
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.292159513
Short name T73
Test name
Test status
Simulation time 10155515004 ps
CPU time 78.53 seconds
Started Mar 12 02:42:40 PM PDT 24
Finished Mar 12 02:43:59 PM PDT 24
Peak memory 614696 kb
Host smart-da9bc031-a6c4-4e33-a8ef-57f3d7df04ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292159513 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.292159513
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2050694845
Short name T895
Test name
Test status
Simulation time 10158965281 ps
CPU time 32.26 seconds
Started Mar 12 02:42:40 PM PDT 24
Finished Mar 12 02:43:12 PM PDT 24
Peak memory 424836 kb
Host smart-81061205-5075-46b6-8b78-539e4c2c656f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050694845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2050694845
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.657754096
Short name T806
Test name
Test status
Simulation time 2133860539 ps
CPU time 2.68 seconds
Started Mar 12 02:42:40 PM PDT 24
Finished Mar 12 02:42:43 PM PDT 24
Peak memory 203556 kb
Host smart-7d683b49-742e-4919-8da3-bd04ef608c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657754096 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.657754096
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2556316239
Short name T452
Test name
Test status
Simulation time 12283385845 ps
CPU time 14.04 seconds
Started Mar 12 02:42:41 PM PDT 24
Finished Mar 12 02:42:55 PM PDT 24
Peak memory 385960 kb
Host smart-5ca0745f-359d-4193-b606-6b611d07fc57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556316239 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2556316239
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.1703834681
Short name T1210
Test name
Test status
Simulation time 3325607086 ps
CPU time 3.75 seconds
Started Mar 12 02:42:43 PM PDT 24
Finished Mar 12 02:42:47 PM PDT 24
Peak memory 204572 kb
Host smart-7355c8d4-665e-4e44-bf39-8b13f8dd37b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703834681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.1703834681
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.982566483
Short name T19
Test name
Test status
Simulation time 36021189334 ps
CPU time 38.41 seconds
Started Mar 12 02:42:41 PM PDT 24
Finished Mar 12 02:43:19 PM PDT 24
Peak memory 221976 kb
Host smart-1f775c38-1697-46aa-ac8e-b3775899f43e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982566483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_stress_all.982566483
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1722783393
Short name T1176
Test name
Test status
Simulation time 52254974076 ps
CPU time 230.54 seconds
Started Mar 12 02:42:40 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 2687976 kb
Host smart-8623060c-c01c-470d-99be-a470af164199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722783393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1722783393
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.4086972716
Short name T561
Test name
Test status
Simulation time 840299343 ps
CPU time 4.66 seconds
Started Mar 12 02:42:43 PM PDT 24
Finished Mar 12 02:42:47 PM PDT 24
Peak memory 204828 kb
Host smart-4a18155c-bc37-491c-a351-596a3ef5ee35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086972716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.4086972716
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4014752749
Short name T604
Test name
Test status
Simulation time 52502243 ps
CPU time 0.58 seconds
Started Mar 12 02:42:54 PM PDT 24
Finished Mar 12 02:42:55 PM PDT 24
Peak memory 202364 kb
Host smart-328a6bcc-0a06-4a72-a320-755e4238b3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014752749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4014752749
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1013725003
Short name T362
Test name
Test status
Simulation time 116885630 ps
CPU time 1.42 seconds
Started Mar 12 02:42:51 PM PDT 24
Finished Mar 12 02:42:53 PM PDT 24
Peak memory 211704 kb
Host smart-b3fd12eb-2f89-49ec-8ad1-dde193e6ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013725003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1013725003
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1533203542
Short name T599
Test name
Test status
Simulation time 651023975 ps
CPU time 5.36 seconds
Started Mar 12 02:42:45 PM PDT 24
Finished Mar 12 02:42:50 PM PDT 24
Peak memory 263472 kb
Host smart-7cd5f502-f486-4d47-bf37-312dee496997
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533203542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1533203542
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3153377139
Short name T1135
Test name
Test status
Simulation time 4821709826 ps
CPU time 177.63 seconds
Started Mar 12 02:42:51 PM PDT 24
Finished Mar 12 02:45:49 PM PDT 24
Peak memory 791980 kb
Host smart-08d5d018-570c-49b4-941d-fada42c9fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153377139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3153377139
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1658513527
Short name T231
Test name
Test status
Simulation time 1672004577 ps
CPU time 47.51 seconds
Started Mar 12 02:42:48 PM PDT 24
Finished Mar 12 02:43:36 PM PDT 24
Peak memory 490788 kb
Host smart-7615c80c-3ab6-4213-9653-61aad8e4f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658513527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1658513527
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1594582790
Short name T1097
Test name
Test status
Simulation time 291373881 ps
CPU time 1.18 seconds
Started Mar 12 02:42:48 PM PDT 24
Finished Mar 12 02:42:49 PM PDT 24
Peak memory 203276 kb
Host smart-00ec149f-6e8a-4888-b032-287449fe1adf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594582790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1594582790
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2725100518
Short name T777
Test name
Test status
Simulation time 1262847981 ps
CPU time 12.24 seconds
Started Mar 12 02:42:49 PM PDT 24
Finished Mar 12 02:43:01 PM PDT 24
Peak memory 244684 kb
Host smart-b483585f-02f7-49d2-8fcf-3a43bd469a65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725100518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2725100518
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3645616829
Short name T202
Test name
Test status
Simulation time 18546890584 ps
CPU time 146.88 seconds
Started Mar 12 02:42:48 PM PDT 24
Finished Mar 12 02:45:15 PM PDT 24
Peak memory 1358356 kb
Host smart-2257e3aa-6e0a-4ef2-9d66-d8f9aabfbfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645616829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3645616829
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3658685843
Short name T867
Test name
Test status
Simulation time 4089115443 ps
CPU time 62.51 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:43:58 PM PDT 24
Peak memory 334412 kb
Host smart-addfe7dc-a800-4427-b23e-403ca8db115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658685843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3658685843
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1912782595
Short name T166
Test name
Test status
Simulation time 54780724 ps
CPU time 0.61 seconds
Started Mar 12 02:42:47 PM PDT 24
Finished Mar 12 02:42:48 PM PDT 24
Peak memory 202528 kb
Host smart-5133a67a-2cc6-458e-af15-a3d7c75f0055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912782595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1912782595
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2697667065
Short name T474
Test name
Test status
Simulation time 3511666920 ps
CPU time 47.39 seconds
Started Mar 12 02:42:47 PM PDT 24
Finished Mar 12 02:43:35 PM PDT 24
Peak memory 277992 kb
Host smart-e1d1f656-8f09-499e-9b54-1ecb4e011c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697667065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2697667065
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3865626656
Short name T1141
Test name
Test status
Simulation time 2042903393 ps
CPU time 108.31 seconds
Started Mar 12 02:42:41 PM PDT 24
Finished Mar 12 02:44:30 PM PDT 24
Peak memory 243748 kb
Host smart-271f85e2-728e-4b20-a3d7-c449c0c01e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865626656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3865626656
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1737936262
Short name T771
Test name
Test status
Simulation time 20628811189 ps
CPU time 1082.54 seconds
Started Mar 12 02:42:47 PM PDT 24
Finished Mar 12 03:00:50 PM PDT 24
Peak memory 3990452 kb
Host smart-db77d773-4e23-4969-b90c-6a53af3cabe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737936262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1737936262
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2483787763
Short name T653
Test name
Test status
Simulation time 1852508748 ps
CPU time 41.95 seconds
Started Mar 12 02:42:51 PM PDT 24
Finished Mar 12 02:43:33 PM PDT 24
Peak memory 211724 kb
Host smart-b23f6887-ce6f-4b4a-af50-1b0c141b0d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483787763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2483787763
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3063728517
Short name T642
Test name
Test status
Simulation time 10076929267 ps
CPU time 67.58 seconds
Started Mar 12 02:42:53 PM PDT 24
Finished Mar 12 02:44:01 PM PDT 24
Peak memory 570392 kb
Host smart-400536bb-c977-4cb0-afcd-c834fd3a75af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063728517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3063728517
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.903623479
Short name T414
Test name
Test status
Simulation time 10057941665 ps
CPU time 72.67 seconds
Started Mar 12 02:42:56 PM PDT 24
Finished Mar 12 02:44:09 PM PDT 24
Peak memory 690716 kb
Host smart-b2847a1b-0312-4b0a-827b-c5d64dfe3885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903623479 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.903623479
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1520953239
Short name T57
Test name
Test status
Simulation time 1623097138 ps
CPU time 2.59 seconds
Started Mar 12 02:42:56 PM PDT 24
Finished Mar 12 02:42:58 PM PDT 24
Peak memory 203588 kb
Host smart-bc4c5262-60b0-4ed5-8b07-b5ea1847e552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520953239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1520953239
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2502135249
Short name T927
Test name
Test status
Simulation time 4607609798 ps
CPU time 5.13 seconds
Started Mar 12 02:42:56 PM PDT 24
Finished Mar 12 02:43:02 PM PDT 24
Peak memory 207132 kb
Host smart-e9aecdce-7721-49be-883f-bee4224a8d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502135249 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2502135249
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_perf.2933793606
Short name T315
Test name
Test status
Simulation time 1344858785 ps
CPU time 4.1 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:42:59 PM PDT 24
Peak memory 208684 kb
Host smart-b2fa1e32-1d23-41b5-98dd-968812fe76fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933793606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.2933793606
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.264133165
Short name T223
Test name
Test status
Simulation time 6811955179 ps
CPU time 29.94 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:43:25 PM PDT 24
Peak memory 219900 kb
Host smart-eb73fd63-4649-4d8f-8db9-a46b49a74121
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264133165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.264133165
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1916758112
Short name T68
Test name
Test status
Simulation time 1664167969 ps
CPU time 67.19 seconds
Started Mar 12 02:42:50 PM PDT 24
Finished Mar 12 02:43:57 PM PDT 24
Peak memory 203472 kb
Host smart-ffe0919c-1705-43c4-bdda-c2192470d748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916758112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1916758112
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.526623297
Short name T1004
Test name
Test status
Simulation time 15718001756 ps
CPU time 9.16 seconds
Started Mar 12 02:46:39 PM PDT 24
Finished Mar 12 02:46:49 PM PDT 24
Peak memory 203580 kb
Host smart-4b435cea-6ea6-41fd-86cc-2ef344d20b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526623297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.526623297
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.3625444414
Short name T616
Test name
Test status
Simulation time 7666646534 ps
CPU time 6.62 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:43:02 PM PDT 24
Peak memory 209764 kb
Host smart-7889c4da-7e6d-4570-b09d-0d1099620f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625444414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.3625444414
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2508439890
Short name T421
Test name
Test status
Simulation time 35186711 ps
CPU time 0.6 seconds
Started Mar 12 02:33:53 PM PDT 24
Finished Mar 12 02:33:54 PM PDT 24
Peak memory 203384 kb
Host smart-ef02c8a6-b70e-4bb5-a1a3-689e04049545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508439890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2508439890
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1269971556
Short name T185
Test name
Test status
Simulation time 43091055 ps
CPU time 1.32 seconds
Started Mar 12 02:33:36 PM PDT 24
Finished Mar 12 02:33:38 PM PDT 24
Peak memory 211716 kb
Host smart-dbdf8f38-bec4-4da8-8042-d281428dca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269971556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1269971556
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3654901969
Short name T756
Test name
Test status
Simulation time 3374641491 ps
CPU time 16.84 seconds
Started Mar 12 02:33:37 PM PDT 24
Finished Mar 12 02:33:54 PM PDT 24
Peak memory 265156 kb
Host smart-905d6104-d440-4a36-8cdf-03f11591c298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654901969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3654901969
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.73881329
Short name T1264
Test name
Test status
Simulation time 4624751812 ps
CPU time 90.89 seconds
Started Mar 12 02:33:36 PM PDT 24
Finished Mar 12 02:35:07 PM PDT 24
Peak memory 780268 kb
Host smart-7c49a020-0e4c-45a9-a43b-337f20106380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73881329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.73881329
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.4101121811
Short name T875
Test name
Test status
Simulation time 2405183690 ps
CPU time 74.86 seconds
Started Mar 12 02:33:32 PM PDT 24
Finished Mar 12 02:34:47 PM PDT 24
Peak memory 659444 kb
Host smart-8bb19863-b704-49bc-a6c4-3225068bdb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101121811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.4101121811
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2096688150
Short name T649
Test name
Test status
Simulation time 124479465 ps
CPU time 1.08 seconds
Started Mar 12 02:33:37 PM PDT 24
Finished Mar 12 02:33:38 PM PDT 24
Peak memory 203456 kb
Host smart-4cfd34cb-c7fc-4d7d-b19d-ef7ee89f8f67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096688150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2096688150
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1297928154
Short name T473
Test name
Test status
Simulation time 1379225559 ps
CPU time 3.84 seconds
Started Mar 12 02:33:45 PM PDT 24
Finished Mar 12 02:33:49 PM PDT 24
Peak memory 227660 kb
Host smart-53829d1a-8a59-42ef-8a6b-3c69ad7f5260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297928154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1297928154
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2941154597
Short name T969
Test name
Test status
Simulation time 4886065695 ps
CPU time 88.52 seconds
Started Mar 12 02:33:50 PM PDT 24
Finished Mar 12 02:35:19 PM PDT 24
Peak memory 349836 kb
Host smart-549d14a6-66c5-4bb6-bb45-c2adf0c8b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941154597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2941154597
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.445816726
Short name T165
Test name
Test status
Simulation time 20451707 ps
CPU time 0.63 seconds
Started Mar 12 02:33:31 PM PDT 24
Finished Mar 12 02:33:31 PM PDT 24
Peak memory 202536 kb
Host smart-cd78285a-6fe4-4faa-8c28-cf5f880817c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445816726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.445816726
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2684745145
Short name T239
Test name
Test status
Simulation time 2108311722 ps
CPU time 59.46 seconds
Started Mar 12 02:33:31 PM PDT 24
Finished Mar 12 02:34:30 PM PDT 24
Peak memory 313552 kb
Host smart-2ec7821d-3f22-4317-a6df-1cbfa2f66c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684745145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2684745145
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.504679934
Short name T897
Test name
Test status
Simulation time 100411713574 ps
CPU time 1290.84 seconds
Started Mar 12 02:33:37 PM PDT 24
Finished Mar 12 02:55:09 PM PDT 24
Peak memory 2526976 kb
Host smart-f3450baf-18f7-41d6-9878-fe8fe4979fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504679934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.504679934
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1302158650
Short name T664
Test name
Test status
Simulation time 4352865661 ps
CPU time 35.79 seconds
Started Mar 12 02:33:34 PM PDT 24
Finished Mar 12 02:34:11 PM PDT 24
Peak memory 211800 kb
Host smart-9be99228-1d8e-492b-83cb-9de19755a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302158650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1302158650
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3033196243
Short name T349
Test name
Test status
Simulation time 5188502847 ps
CPU time 4.36 seconds
Started Mar 12 02:33:48 PM PDT 24
Finished Mar 12 02:33:54 PM PDT 24
Peak memory 203688 kb
Host smart-75cea9c5-d751-45e9-800a-ae3fc0b9cbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033196243 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3033196243
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3080793506
Short name T887
Test name
Test status
Simulation time 10083444173 ps
CPU time 25.21 seconds
Started Mar 12 02:33:53 PM PDT 24
Finished Mar 12 02:34:18 PM PDT 24
Peak memory 344700 kb
Host smart-bc525d28-1163-46cf-864a-10ffbff5cbc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080793506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3080793506
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.125017781
Short name T841
Test name
Test status
Simulation time 10139738764 ps
CPU time 80.91 seconds
Started Mar 12 02:33:50 PM PDT 24
Finished Mar 12 02:35:11 PM PDT 24
Peak memory 660556 kb
Host smart-199013b2-869a-44dc-ac50-0e0d7145878f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125017781 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.125017781
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2171283077
Short name T109
Test name
Test status
Simulation time 12506495049 ps
CPU time 3.45 seconds
Started Mar 12 02:33:50 PM PDT 24
Finished Mar 12 02:33:54 PM PDT 24
Peak memory 203608 kb
Host smart-77a3bc01-8ae2-4c9a-954e-4cee045000d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171283077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2171283077
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1740467670
Short name T985
Test name
Test status
Simulation time 12559242052 ps
CPU time 90.37 seconds
Started Mar 12 02:33:43 PM PDT 24
Finished Mar 12 02:35:13 PM PDT 24
Peak memory 1578708 kb
Host smart-8ae33c31-7314-4a73-bc45-14eba3a7e8a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740467670 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1740467670
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.2271958184
Short name T460
Test name
Test status
Simulation time 1586596919 ps
CPU time 4.78 seconds
Started Mar 12 02:33:49 PM PDT 24
Finished Mar 12 02:33:54 PM PDT 24
Peak memory 210756 kb
Host smart-eda648dd-fa2e-434d-9b6a-c24f2d6af54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271958184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.2271958184
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1763101088
Short name T1191
Test name
Test status
Simulation time 828310533 ps
CPU time 34.4 seconds
Started Mar 12 02:33:48 PM PDT 24
Finished Mar 12 02:34:24 PM PDT 24
Peak memory 203560 kb
Host smart-f72fbf00-7c06-4ee8-a4cf-44f6066b1de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763101088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1763101088
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1450543264
Short name T1136
Test name
Test status
Simulation time 6338306997 ps
CPU time 7.7 seconds
Started Mar 12 02:33:50 PM PDT 24
Finished Mar 12 02:33:58 PM PDT 24
Peak memory 214604 kb
Host smart-06015737-5d14-4450-89a6-2fd50327d633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450543264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1450543264
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.923528371
Short name T1156
Test name
Test status
Simulation time 1454012196 ps
CPU time 7.8 seconds
Started Mar 12 02:33:54 PM PDT 24
Finished Mar 12 02:34:02 PM PDT 24
Peak memory 212068 kb
Host smart-e707ca9f-7ba2-49dc-9ad2-842ee416b347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923528371 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_unexp_stop.923528371
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2594359267
Short name T246
Test name
Test status
Simulation time 173104338 ps
CPU time 0.61 seconds
Started Mar 12 02:34:08 PM PDT 24
Finished Mar 12 02:34:09 PM PDT 24
Peak memory 203340 kb
Host smart-0d42b1ea-a512-41fd-8075-dda13f5b8b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594359267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2594359267
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2286324065
Short name T1023
Test name
Test status
Simulation time 87188906 ps
CPU time 1.5 seconds
Started Mar 12 02:33:54 PM PDT 24
Finished Mar 12 02:33:56 PM PDT 24
Peak memory 211760 kb
Host smart-acf0a22d-c578-40ba-aba2-4f1b5b0eb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286324065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2286324065
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.471624617
Short name T233
Test name
Test status
Simulation time 461544788 ps
CPU time 10.64 seconds
Started Mar 12 02:33:53 PM PDT 24
Finished Mar 12 02:34:04 PM PDT 24
Peak memory 307684 kb
Host smart-06a9ba87-0b61-49a5-9372-fc3ef396613b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471624617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.471624617
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1832128327
Short name T451
Test name
Test status
Simulation time 5739628874 ps
CPU time 206.98 seconds
Started Mar 12 02:33:55 PM PDT 24
Finished Mar 12 02:37:22 PM PDT 24
Peak memory 819996 kb
Host smart-55166eae-ca81-4c9d-b5e0-80b8be5c5db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832128327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1832128327
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.685836057
Short name T780
Test name
Test status
Simulation time 4571601745 ps
CPU time 70.84 seconds
Started Mar 12 02:33:53 PM PDT 24
Finished Mar 12 02:35:05 PM PDT 24
Peak memory 674460 kb
Host smart-55e88a39-ec59-4ccf-acd7-6604de5d0a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685836057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.685836057
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.303338141
Short name T439
Test name
Test status
Simulation time 390626226 ps
CPU time 0.9 seconds
Started Mar 12 02:33:54 PM PDT 24
Finished Mar 12 02:33:55 PM PDT 24
Peak memory 203272 kb
Host smart-2c621fca-3f46-4dd5-a71d-4d9634962ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303338141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.303338141
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.174387002
Short name T940
Test name
Test status
Simulation time 186134330 ps
CPU time 4.85 seconds
Started Mar 12 02:33:54 PM PDT 24
Finished Mar 12 02:33:59 PM PDT 24
Peak memory 237816 kb
Host smart-2a1b38e1-08af-40e4-a087-b29fc48e8c49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174387002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.174387002
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1079118293
Short name T857
Test name
Test status
Simulation time 5555310214 ps
CPU time 192.3 seconds
Started Mar 12 02:33:49 PM PDT 24
Finished Mar 12 02:37:02 PM PDT 24
Peak memory 922108 kb
Host smart-19da28a8-ac9f-4041-852b-89f941101aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079118293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1079118293
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1100793958
Short name T478
Test name
Test status
Simulation time 2789327392 ps
CPU time 46.28 seconds
Started Mar 12 02:34:06 PM PDT 24
Finished Mar 12 02:34:53 PM PDT 24
Peak memory 278696 kb
Host smart-f0e29644-0c12-4aa3-87b6-0fc013d2a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100793958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1100793958
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.671221264
Short name T633
Test name
Test status
Simulation time 16320759 ps
CPU time 0.65 seconds
Started Mar 12 02:33:50 PM PDT 24
Finished Mar 12 02:33:51 PM PDT 24
Peak memory 202588 kb
Host smart-ae1fc544-2651-4693-a51d-4d7b48afa620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671221264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.671221264
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1542665981
Short name T650
Test name
Test status
Simulation time 48371061955 ps
CPU time 621.97 seconds
Started Mar 12 02:33:55 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 299756 kb
Host smart-11ab317f-620c-4028-9e6e-2046685cdfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542665981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1542665981
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1429027018
Short name T486
Test name
Test status
Simulation time 1939173335 ps
CPU time 55.64 seconds
Started Mar 12 02:33:49 PM PDT 24
Finished Mar 12 02:34:45 PM PDT 24
Peak memory 298028 kb
Host smart-0c6e1cac-ec02-45ab-902b-4f180572ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429027018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1429027018
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1195067532
Short name T856
Test name
Test status
Simulation time 1469572008 ps
CPU time 32.07 seconds
Started Mar 12 02:33:54 PM PDT 24
Finished Mar 12 02:34:26 PM PDT 24
Peak memory 211692 kb
Host smart-f69944d6-6a9c-45d8-9748-13698783ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195067532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1195067532
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.381120829
Short name T888
Test name
Test status
Simulation time 10476138838 ps
CPU time 14.84 seconds
Started Mar 12 02:33:59 PM PDT 24
Finished Mar 12 02:34:14 PM PDT 24
Peak memory 301304 kb
Host smart-24246ed0-db83-403a-a55f-bc0b10fcac2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381120829 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.381120829
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.4238393642
Short name T1236
Test name
Test status
Simulation time 10126457219 ps
CPU time 84.13 seconds
Started Mar 12 02:34:00 PM PDT 24
Finished Mar 12 02:35:24 PM PDT 24
Peak memory 707556 kb
Host smart-152c5b34-d180-4823-8d6b-e276f2591f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238393642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.4238393642
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3709418082
Short name T554
Test name
Test status
Simulation time 2121478318 ps
CPU time 2.58 seconds
Started Mar 12 02:34:08 PM PDT 24
Finished Mar 12 02:34:11 PM PDT 24
Peak memory 203628 kb
Host smart-c43d6706-d5d5-4899-b8d1-29e992ff5d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709418082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3709418082
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3743843848
Short name T544
Test name
Test status
Simulation time 1653038448 ps
CPU time 3.51 seconds
Started Mar 12 02:34:01 PM PDT 24
Finished Mar 12 02:34:04 PM PDT 24
Peak memory 203568 kb
Host smart-45d188a7-2a4e-4486-ad48-fc1da5a15d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743843848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3743843848
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3824062386
Short name T1168
Test name
Test status
Simulation time 16337247883 ps
CPU time 177.05 seconds
Started Mar 12 02:34:01 PM PDT 24
Finished Mar 12 02:36:58 PM PDT 24
Peak memory 2404432 kb
Host smart-8a7026ee-c0dd-41a1-8341-27f617658a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824062386 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3824062386
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.844484639
Short name T581
Test name
Test status
Simulation time 794730299 ps
CPU time 4.48 seconds
Started Mar 12 02:34:00 PM PDT 24
Finished Mar 12 02:34:04 PM PDT 24
Peak memory 203644 kb
Host smart-2d1bc58c-77c7-464e-b658-7c3852f7b40c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844484639 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_perf.844484639
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2605279072
Short name T614
Test name
Test status
Simulation time 8786156692 ps
CPU time 8.52 seconds
Started Mar 12 02:33:53 PM PDT 24
Finished Mar 12 02:34:01 PM PDT 24
Peak memory 203584 kb
Host smart-1a6d9a30-b29e-4e32-8a29-5adaada2954e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605279072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2605279072
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.302435987
Short name T936
Test name
Test status
Simulation time 8446643765 ps
CPU time 94.58 seconds
Started Mar 12 02:33:55 PM PDT 24
Finished Mar 12 02:35:30 PM PDT 24
Peak memory 558668 kb
Host smart-dacce425-880f-4a05-a5f8-13f0fd6e4c25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302435987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.302435987
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.135663877
Short name T552
Test name
Test status
Simulation time 1655539388 ps
CPU time 7.06 seconds
Started Mar 12 02:34:01 PM PDT 24
Finished Mar 12 02:34:09 PM PDT 24
Peak memory 203624 kb
Host smart-078bd3dc-9c54-465d-b614-7116b981969a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135663877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.135663877
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.2986808502
Short name T502
Test name
Test status
Simulation time 3954547190 ps
CPU time 4.99 seconds
Started Mar 12 02:34:01 PM PDT 24
Finished Mar 12 02:34:07 PM PDT 24
Peak memory 203624 kb
Host smart-7c060e80-5437-470b-be8d-75f505d52a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986808502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.2986808502
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1179827913
Short name T691
Test name
Test status
Simulation time 62641517 ps
CPU time 0.61 seconds
Started Mar 12 02:34:15 PM PDT 24
Finished Mar 12 02:34:16 PM PDT 24
Peak memory 202260 kb
Host smart-7a7f686b-3d71-4a56-8c26-753105ce7431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179827913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1179827913
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.260820127
Short name T1020
Test name
Test status
Simulation time 62939653 ps
CPU time 1.15 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:34:13 PM PDT 24
Peak memory 211756 kb
Host smart-d8653d6f-8f00-4ad2-bfc3-f1151924c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260820127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.260820127
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1455585497
Short name T694
Test name
Test status
Simulation time 218964173 ps
CPU time 9.44 seconds
Started Mar 12 02:34:06 PM PDT 24
Finished Mar 12 02:34:17 PM PDT 24
Peak memory 236584 kb
Host smart-76d54a64-494f-419d-941a-c1e46e73886a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455585497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1455585497
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1128709662
Short name T641
Test name
Test status
Simulation time 10715450528 ps
CPU time 119.52 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:36:12 PM PDT 24
Peak memory 952244 kb
Host smart-70c4b4fd-b50a-497c-8d0b-e6679ffa9b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128709662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1128709662
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2283920544
Short name T304
Test name
Test status
Simulation time 1635756227 ps
CPU time 44.33 seconds
Started Mar 12 02:34:11 PM PDT 24
Finished Mar 12 02:34:57 PM PDT 24
Peak memory 434824 kb
Host smart-c43b06a1-6afb-434d-9a88-532e386f9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283920544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2283920544
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2305348325
Short name T339
Test name
Test status
Simulation time 617837182 ps
CPU time 1.09 seconds
Started Mar 12 02:34:08 PM PDT 24
Finished Mar 12 02:34:09 PM PDT 24
Peak memory 203468 kb
Host smart-21f0a0eb-5085-4db4-a515-a897e1381d1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305348325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2305348325
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1476964593
Short name T1237
Test name
Test status
Simulation time 361732019 ps
CPU time 4.42 seconds
Started Mar 12 02:34:06 PM PDT 24
Finished Mar 12 02:34:12 PM PDT 24
Peak memory 203524 kb
Host smart-a3ca76eb-2f88-42e8-a5fc-96c69696110f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476964593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1476964593
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3293054860
Short name T1226
Test name
Test status
Simulation time 11936628443 ps
CPU time 196.84 seconds
Started Mar 12 02:34:06 PM PDT 24
Finished Mar 12 02:37:23 PM PDT 24
Peak memory 889560 kb
Host smart-abd7af16-cd6e-4e93-9d76-e8869db08386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293054860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3293054860
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_override.2700779247
Short name T955
Test name
Test status
Simulation time 15111560 ps
CPU time 0.63 seconds
Started Mar 12 02:34:07 PM PDT 24
Finished Mar 12 02:34:08 PM PDT 24
Peak memory 203100 kb
Host smart-ac729253-d62b-4cb1-bf34-985cd0a3dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700779247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2700779247
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2264481370
Short name T1202
Test name
Test status
Simulation time 28179686708 ps
CPU time 350.36 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:40:03 PM PDT 24
Peak memory 211716 kb
Host smart-8f6803cc-bcf3-4017-9610-bbb971d7c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264481370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2264481370
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.4043123422
Short name T379
Test name
Test status
Simulation time 1424198788 ps
CPU time 73.05 seconds
Started Mar 12 02:34:06 PM PDT 24
Finished Mar 12 02:35:20 PM PDT 24
Peak memory 228036 kb
Host smart-72de297a-e315-43a7-954d-1cec11a8573d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043123422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4043123422
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.163181420
Short name T464
Test name
Test status
Simulation time 1252954811 ps
CPU time 11.74 seconds
Started Mar 12 02:34:13 PM PDT 24
Finished Mar 12 02:34:25 PM PDT 24
Peak memory 211792 kb
Host smart-006d373d-6c27-4189-8798-71bd1f3e66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163181420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.163181420
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2484708593
Short name T1030
Test name
Test status
Simulation time 5657642548 ps
CPU time 4.65 seconds
Started Mar 12 02:34:18 PM PDT 24
Finished Mar 12 02:34:22 PM PDT 24
Peak memory 203664 kb
Host smart-614b8b25-fe72-4ef0-ae76-54e2fb88473c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484708593 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2484708593
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3471059682
Short name T218
Test name
Test status
Simulation time 10826929892 ps
CPU time 5.19 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:34:18 PM PDT 24
Peak memory 230936 kb
Host smart-968e73a3-6d40-4cf0-b5dc-026ab3348208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471059682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3471059682
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1907491370
Short name T178
Test name
Test status
Simulation time 10212606358 ps
CPU time 22.72 seconds
Started Mar 12 02:34:13 PM PDT 24
Finished Mar 12 02:34:35 PM PDT 24
Peak memory 409464 kb
Host smart-793170c8-fb98-4a39-906f-b4a882f3fb0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907491370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1907491370
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1521811028
Short name T184
Test name
Test status
Simulation time 348987101 ps
CPU time 2.15 seconds
Started Mar 12 02:34:17 PM PDT 24
Finished Mar 12 02:34:19 PM PDT 24
Peak memory 203552 kb
Host smart-d5c5fce2-521c-4e83-9f34-61afe9e3c3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521811028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1521811028
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.593483422
Short name T1038
Test name
Test status
Simulation time 1270655341 ps
CPU time 3.57 seconds
Started Mar 12 02:34:11 PM PDT 24
Finished Mar 12 02:34:16 PM PDT 24
Peak memory 203548 kb
Host smart-1604e14f-617b-4c77-8e06-4967dadf1a5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593483422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.593483422
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2909806298
Short name T829
Test name
Test status
Simulation time 5975193263 ps
CPU time 3.68 seconds
Started Mar 12 02:34:15 PM PDT 24
Finished Mar 12 02:34:19 PM PDT 24
Peak memory 203636 kb
Host smart-93a99f3d-8f68-4faf-bfe1-6b282b31ca96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909806298 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2909806298
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.51891756
Short name T337
Test name
Test status
Simulation time 426238064 ps
CPU time 3.19 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:34:16 PM PDT 24
Peak memory 203624 kb
Host smart-9c158674-e604-4c0e-b835-677c597fa495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51891756 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.i2c_target_perf.51891756
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3358381495
Short name T1095
Test name
Test status
Simulation time 32739561973 ps
CPU time 32.9 seconds
Started Mar 12 02:34:17 PM PDT 24
Finished Mar 12 02:34:50 PM PDT 24
Peak memory 223144 kb
Host smart-e2ac1033-5bda-47a2-bc8e-e992862c6c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358381495 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3358381495
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.234887022
Short name T800
Test name
Test status
Simulation time 1271816827 ps
CPU time 13.8 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:34:26 PM PDT 24
Peak memory 203524 kb
Host smart-b9fc562b-90b4-4136-b79b-012dee80a738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234887022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.234887022
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1157279038
Short name T1128
Test name
Test status
Simulation time 11542376759 ps
CPU time 6.55 seconds
Started Mar 12 02:34:10 PM PDT 24
Finished Mar 12 02:34:17 PM PDT 24
Peak memory 203664 kb
Host smart-7e2914aa-27f6-43a7-82f3-cd8e65d23bb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157279038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1157279038
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1162437343
Short name T905
Test name
Test status
Simulation time 1918114951 ps
CPU time 6.57 seconds
Started Mar 12 02:34:16 PM PDT 24
Finished Mar 12 02:34:22 PM PDT 24
Peak memory 203520 kb
Host smart-88552220-8f64-45c9-8816-992529c71a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162437343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1162437343
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.1862642887
Short name T65
Test name
Test status
Simulation time 2962348543 ps
CPU time 6.29 seconds
Started Mar 12 02:34:12 PM PDT 24
Finished Mar 12 02:34:19 PM PDT 24
Peak memory 209320 kb
Host smart-ead33e58-7a4e-43e5-9938-0d24764efc2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862642887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.1862642887
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3438256125
Short name T256
Test name
Test status
Simulation time 68214930 ps
CPU time 0.6 seconds
Started Mar 12 02:34:37 PM PDT 24
Finished Mar 12 02:34:38 PM PDT 24
Peak memory 203340 kb
Host smart-cadda09d-3c8a-438c-80fe-04f36031854f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438256125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3438256125
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3017184718
Short name T160
Test name
Test status
Simulation time 41564737 ps
CPU time 1.19 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 02:34:29 PM PDT 24
Peak memory 211820 kb
Host smart-dff33e1a-87b1-445f-a71e-f9494e072262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017184718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3017184718
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.744974573
Short name T934
Test name
Test status
Simulation time 937768795 ps
CPU time 8.06 seconds
Started Mar 12 02:34:26 PM PDT 24
Finished Mar 12 02:34:34 PM PDT 24
Peak memory 307560 kb
Host smart-3474155d-aa5d-4bcf-8877-cb51607ceb5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744974573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.744974573
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2684175399
Short name T1072
Test name
Test status
Simulation time 2407017598 ps
CPU time 68.93 seconds
Started Mar 12 02:34:21 PM PDT 24
Finished Mar 12 02:35:30 PM PDT 24
Peak memory 778620 kb
Host smart-139af845-291c-4c6c-961b-98d1b570a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684175399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2684175399
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3457643140
Short name T268
Test name
Test status
Simulation time 10204094206 ps
CPU time 54.76 seconds
Started Mar 12 02:34:26 PM PDT 24
Finished Mar 12 02:35:21 PM PDT 24
Peak memory 647316 kb
Host smart-f594af10-b3e2-4093-9ecc-a56b97720307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457643140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3457643140
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.300054581
Short name T1192
Test name
Test status
Simulation time 155980524 ps
CPU time 4.16 seconds
Started Mar 12 02:34:22 PM PDT 24
Finished Mar 12 02:34:28 PM PDT 24
Peak memory 230592 kb
Host smart-25311f17-62e4-4f48-b0e2-7a3a7a197374
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300054581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.300054581
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3954590874
Short name T423
Test name
Test status
Simulation time 30680565677 ps
CPU time 220.14 seconds
Started Mar 12 02:34:24 PM PDT 24
Finished Mar 12 02:38:04 PM PDT 24
Peak memory 821572 kb
Host smart-d14d16a0-9042-4ccb-9a7e-423b95cfa25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954590874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3954590874
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.4030013718
Short name T640
Test name
Test status
Simulation time 1942701733 ps
CPU time 63.12 seconds
Started Mar 12 02:34:37 PM PDT 24
Finished Mar 12 02:35:40 PM PDT 24
Peak memory 217880 kb
Host smart-cf93a288-bdcc-4cd1-983d-ee1557593bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030013718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.4030013718
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2916120377
Short name T963
Test name
Test status
Simulation time 27323706 ps
CPU time 0.64 seconds
Started Mar 12 02:34:21 PM PDT 24
Finished Mar 12 02:34:22 PM PDT 24
Peak memory 202604 kb
Host smart-3ab698d3-e701-465f-892e-ccda397e7f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916120377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2916120377
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2121109315
Short name T794
Test name
Test status
Simulation time 14103401281 ps
CPU time 174.24 seconds
Started Mar 12 02:34:22 PM PDT 24
Finished Mar 12 02:37:18 PM PDT 24
Peak memory 203448 kb
Host smart-6f084f1e-5cce-4cb6-90a4-7ef52efc957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121109315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2121109315
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.6278114
Short name T1106
Test name
Test status
Simulation time 6491356158 ps
CPU time 89.12 seconds
Started Mar 12 02:34:18 PM PDT 24
Finished Mar 12 02:35:48 PM PDT 24
Peak memory 236148 kb
Host smart-5a1f86f9-0c1b-4d48-bee2-361969fb17d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6278114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.6278114
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.803051636
Short name T206
Test name
Test status
Simulation time 2781649230 ps
CPU time 11.57 seconds
Started Mar 12 02:34:24 PM PDT 24
Finished Mar 12 02:34:36 PM PDT 24
Peak memory 215376 kb
Host smart-407d631d-c368-4f5c-ae39-89b24dc70ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803051636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.803051636
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2000190865
Short name T483
Test name
Test status
Simulation time 722153202 ps
CPU time 3.32 seconds
Started Mar 12 02:34:39 PM PDT 24
Finished Mar 12 02:34:42 PM PDT 24
Peak memory 203592 kb
Host smart-8ffac642-fec0-476b-8b6d-cb3e5d53d801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000190865 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2000190865
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.457674166
Short name T1057
Test name
Test status
Simulation time 10095361524 ps
CPU time 73.67 seconds
Started Mar 12 02:34:29 PM PDT 24
Finished Mar 12 02:35:44 PM PDT 24
Peak memory 577176 kb
Host smart-f5c06bd7-a32e-40a5-b40d-b95a85cd208e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457674166 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.457674166
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3697167429
Short name T1036
Test name
Test status
Simulation time 10236629122 ps
CPU time 14.73 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 02:34:43 PM PDT 24
Peak memory 316948 kb
Host smart-9c5fb170-f5ce-43e9-9c16-84c44bb9be18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697167429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3697167429
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3157057364
Short name T1151
Test name
Test status
Simulation time 521464772 ps
CPU time 2.85 seconds
Started Mar 12 02:34:37 PM PDT 24
Finished Mar 12 02:34:40 PM PDT 24
Peak memory 203588 kb
Host smart-e9002678-030a-4403-9f77-eff101b90b47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157057364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3157057364
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3948413253
Short name T785
Test name
Test status
Simulation time 777894549 ps
CPU time 4.33 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 02:34:33 PM PDT 24
Peak memory 203504 kb
Host smart-101468cc-7834-4fab-817a-c752936d51ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948413253 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3948413253
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.792053615
Short name T810
Test name
Test status
Simulation time 12172677242 ps
CPU time 21.89 seconds
Started Mar 12 02:34:31 PM PDT 24
Finished Mar 12 02:34:53 PM PDT 24
Peak memory 579136 kb
Host smart-d4cbae79-59f8-4ae2-966c-22d880edee26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792053615 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.792053615
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.2030709016
Short name T725
Test name
Test status
Simulation time 1084416460 ps
CPU time 3.45 seconds
Started Mar 12 02:34:37 PM PDT 24
Finished Mar 12 02:34:41 PM PDT 24
Peak memory 204624 kb
Host smart-0d7446b0-ab79-43e6-ad4a-cd6faae6834f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030709016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.2030709016
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3791125993
Short name T406
Test name
Test status
Simulation time 746800480 ps
CPU time 11.63 seconds
Started Mar 12 02:34:29 PM PDT 24
Finished Mar 12 02:34:42 PM PDT 24
Peak memory 211028 kb
Host smart-20a3f91e-6b82-4447-85f4-7f093df13105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791125993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3791125993
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3302413033
Short name T947
Test name
Test status
Simulation time 16531435477 ps
CPU time 8.43 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 02:34:37 PM PDT 24
Peak memory 203620 kb
Host smart-2f6f461c-a0e5-43f1-b282-b8c4328b0966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302413033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3302413033
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1473951264
Short name T663
Test name
Test status
Simulation time 17424161097 ps
CPU time 2524.75 seconds
Started Mar 12 02:34:28 PM PDT 24
Finished Mar 12 03:16:33 PM PDT 24
Peak memory 4255204 kb
Host smart-29e12a59-66a9-474e-af3d-88d037ffb408
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473951264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1473951264
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3350429842
Short name T378
Test name
Test status
Simulation time 1621433645 ps
CPU time 7.99 seconds
Started Mar 12 02:34:29 PM PDT 24
Finished Mar 12 02:34:38 PM PDT 24
Peak memory 215944 kb
Host smart-8bbeaa10-7bdb-4d25-8532-99e0a2f3984b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350429842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3350429842
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.473593062
Short name T704
Test name
Test status
Simulation time 10898558310 ps
CPU time 7.61 seconds
Started Mar 12 02:34:30 PM PDT 24
Finished Mar 12 02:34:38 PM PDT 24
Peak memory 212280 kb
Host smart-a6f9b704-c1a3-4300-a0c2-ebd62a08e695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473593062 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_unexp_stop.473593062
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2391053638
Short name T796
Test name
Test status
Simulation time 89769091 ps
CPU time 0.57 seconds
Started Mar 12 02:34:55 PM PDT 24
Finished Mar 12 02:34:56 PM PDT 24
Peak memory 202116 kb
Host smart-615a9460-9c74-4ad1-9719-a3b6735d2a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391053638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2391053638
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3078614222
Short name T657
Test name
Test status
Simulation time 322009498 ps
CPU time 1.52 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:34:50 PM PDT 24
Peak memory 211688 kb
Host smart-d84e37b2-abff-4ccc-a19c-8876d76d854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078614222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3078614222
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3514691507
Short name T893
Test name
Test status
Simulation time 406561878 ps
CPU time 14.26 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 259640 kb
Host smart-6273e5f8-f81e-44fb-9571-c56a40830539
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514691507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3514691507
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3176617530
Short name T494
Test name
Test status
Simulation time 2540178530 ps
CPU time 138.38 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:37:07 PM PDT 24
Peak memory 597640 kb
Host smart-ea786026-b25d-46a3-a386-c2ef5f7a5e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176617530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3176617530
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1346962749
Short name T703
Test name
Test status
Simulation time 1447400111 ps
CPU time 102.33 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:36:31 PM PDT 24
Peak memory 524204 kb
Host smart-80c4cb47-b7d9-48d6-a263-2b3a3ff429e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346962749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1346962749
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1786887301
Short name T501
Test name
Test status
Simulation time 157829162 ps
CPU time 1.06 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:34:49 PM PDT 24
Peak memory 203312 kb
Host smart-bcc98b83-d89f-4d80-8d30-9d55408672a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786887301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1786887301
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2179034566
Short name T902
Test name
Test status
Simulation time 863018730 ps
CPU time 12.66 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:35:01 PM PDT 24
Peak memory 247664 kb
Host smart-7fcbe79f-7955-46ad-9304-803deb34f195
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179034566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2179034566
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1370157911
Short name T939
Test name
Test status
Simulation time 6898945008 ps
CPU time 31.55 seconds
Started Mar 12 02:34:54 PM PDT 24
Finished Mar 12 02:35:27 PM PDT 24
Peak memory 261892 kb
Host smart-56a724b2-f52f-400b-b0d0-b8c0f9fa7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370157911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1370157911
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3044812947
Short name T169
Test name
Test status
Simulation time 171859992 ps
CPU time 0.62 seconds
Started Mar 12 02:34:47 PM PDT 24
Finished Mar 12 02:34:48 PM PDT 24
Peak memory 202532 kb
Host smart-424e6a0a-548a-4bb9-9d7f-de4bafe148ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044812947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3044812947
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3037573533
Short name T1024
Test name
Test status
Simulation time 3780461493 ps
CPU time 50.26 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:35:40 PM PDT 24
Peak memory 203548 kb
Host smart-76fc3049-39ed-4512-9bb8-4958d3f1331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037573533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3037573533
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1043613616
Short name T742
Test name
Test status
Simulation time 1782122021 ps
CPU time 49.66 seconds
Started Mar 12 02:34:36 PM PDT 24
Finished Mar 12 02:35:25 PM PDT 24
Peak memory 269880 kb
Host smart-5ed271e7-adfa-400d-b0ab-2908cf18703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043613616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1043613616
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3354796013
Short name T173
Test name
Test status
Simulation time 61316835160 ps
CPU time 3157.47 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 03:27:26 PM PDT 24
Peak memory 891724 kb
Host smart-29ef034d-5b97-4951-b389-af347f533fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354796013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3354796013
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.478497762
Short name T732
Test name
Test status
Simulation time 6109315037 ps
CPU time 30.45 seconds
Started Mar 12 02:34:53 PM PDT 24
Finished Mar 12 02:35:25 PM PDT 24
Peak memory 211772 kb
Host smart-dff9de69-5ca0-414a-9385-b3fd94d44861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478497762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.478497762
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2660447725
Short name T1199
Test name
Test status
Simulation time 2611661874 ps
CPU time 5.77 seconds
Started Mar 12 02:34:50 PM PDT 24
Finished Mar 12 02:34:55 PM PDT 24
Peak memory 204968 kb
Host smart-483202db-3926-484b-9c98-dd6a35c5d6fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660447725 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2660447725
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1639302067
Short name T1083
Test name
Test status
Simulation time 10048662234 ps
CPU time 62.8 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:35:52 PM PDT 24
Peak memory 520668 kb
Host smart-931bd23c-5043-4962-8c39-2cfce79e04a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639302067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1639302067
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2696763225
Short name T532
Test name
Test status
Simulation time 10143371528 ps
CPU time 38.24 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:35:26 PM PDT 24
Peak memory 487296 kb
Host smart-493adad6-69f1-4ad1-9fb8-ecb8bf0d9962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696763225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2696763225
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3750052948
Short name T821
Test name
Test status
Simulation time 2828744468 ps
CPU time 2.39 seconds
Started Mar 12 02:34:54 PM PDT 24
Finished Mar 12 02:34:58 PM PDT 24
Peak memory 203620 kb
Host smart-84f05b49-95ec-44f3-b469-8cf825ec6c49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750052948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3750052948
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3104536670
Short name T1037
Test name
Test status
Simulation time 2248548400 ps
CPU time 3.18 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:34:53 PM PDT 24
Peak memory 203600 kb
Host smart-00d6fc2d-ab3e-4125-85f1-e3ff1d08c1ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104536670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3104536670
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2583942644
Short name T926
Test name
Test status
Simulation time 14978952498 ps
CPU time 12.87 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 351024 kb
Host smart-36c0c0b8-6bf2-4e36-a791-137b111c58e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583942644 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2583942644
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3445632520
Short name T267
Test name
Test status
Simulation time 4802088706 ps
CPU time 4.19 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:34:53 PM PDT 24
Peak memory 203664 kb
Host smart-fe9204e7-a624-49ed-b07a-308d2591d190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445632520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3445632520
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.1489913766
Short name T426
Test name
Test status
Simulation time 21877887271 ps
CPU time 274.32 seconds
Started Mar 12 02:34:50 PM PDT 24
Finished Mar 12 02:39:24 PM PDT 24
Peak memory 2157008 kb
Host smart-627b3f4d-fb62-46e0-bc91-dfcc26219d27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489913766 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.1489913766
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.3890630188
Short name T490
Test name
Test status
Simulation time 1490422707 ps
CPU time 28.13 seconds
Started Mar 12 02:34:50 PM PDT 24
Finished Mar 12 02:35:18 PM PDT 24
Peak memory 203560 kb
Host smart-08edb899-69ff-4285-aea8-c2a7d021cedb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890630188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.3890630188
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1191051865
Short name T1241
Test name
Test status
Simulation time 15776553374 ps
CPU time 151.91 seconds
Started Mar 12 02:34:49 PM PDT 24
Finished Mar 12 02:37:21 PM PDT 24
Peak memory 725500 kb
Host smart-e4d3aad1-663e-4af4-b4e2-b150352f4c9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191051865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1191051865
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1470378960
Short name T935
Test name
Test status
Simulation time 18021861946 ps
CPU time 7.45 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:34:56 PM PDT 24
Peak memory 209776 kb
Host smart-e4a016c3-6783-4772-88a7-242f4f1ca522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470378960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1470378960
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.695575108
Short name T993
Test name
Test status
Simulation time 4574174454 ps
CPU time 6.09 seconds
Started Mar 12 02:34:48 PM PDT 24
Finished Mar 12 02:34:55 PM PDT 24
Peak memory 206944 kb
Host smart-81e20a35-2a6f-46f7-a596-454a6099c232
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695575108 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_unexp_stop.695575108
Directory /workspace/9.i2c_target_unexp_stop/latest
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