Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	330	1			T2	5		T7	1		T8	5
all_pins[1]	330	1			T2	5		T7	1		T8	5
all_pins[2]	330	1			T2	5		T7	1		T8	5
all_pins[3]	330	1			T2	5		T7	1		T8	5
all_pins[4]	330	1			T2	5		T7	1		T8	5
all_pins[5]	330	1			T2	5		T7	1		T8	5
all_pins[6]	330	1			T2	5		T7	1		T8	5
all_pins[7]	330	1			T2	5		T7	1		T8	5
all_pins[8]	330	1			T2	5		T7	1		T8	5
all_pins[9]	330	1			T2	5		T7	1		T8	5
all_pins[10]	330	1			T2	5		T7	1		T8	5
all_pins[11]	330	1			T2	5		T7	1		T8	5
all_pins[12]	330	1			T2	5		T7	1		T8	5
all_pins[13]	330	1			T2	5		T7	1		T8	5
all_pins[14]	330	1			T2	5		T7	1		T8	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4093	1			T2	59		T7	15		T8	59
values[0x1]	857	1			T2	16		T8	16		T9	12
transitions[0x0=>0x1]	635	1			T2	7		T8	9		T9	10
transitions[0x1=>0x0]	647	1			T2	7		T8	9		T9	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282	1			T2	3		T7	1		T8	5
all_pins[0]	values[0x1]	48	1			T2	2		T11	1		T59	1
all_pins[0]	transitions[0x0=>0x1]	33	1			T11	1		T59	1		T65	2
all_pins[0]	transitions[0x1=>0x0]	47	1			T8	2		T9	1		T10	2
all_pins[1]	values[0x0]	268	1			T2	3		T7	1		T8	3
all_pins[1]	values[0x1]	62	1			T2	2		T8	2		T9	1
all_pins[1]	transitions[0x0=>0x1]	46	1			T2	1		T8	1		T9	1
all_pins[1]	transitions[0x1=>0x0]	42	1			T9	1		T10	1		T11	2
all_pins[2]	values[0x0]	272	1			T2	4		T7	1		T8	4
all_pins[2]	values[0x1]	58	1			T2	1		T8	1		T9	1
all_pins[2]	transitions[0x0=>0x1]	42	1			T2	1		T8	1		T10	1
all_pins[2]	transitions[0x1=>0x0]	45	1			T9	1		T11	1		T59	1
all_pins[3]	values[0x0]	269	1			T2	5		T7	1		T8	5
all_pins[3]	values[0x1]	61	1			T9	2		T10	1		T11	1
all_pins[3]	transitions[0x0=>0x1]	46	1			T9	2		T66	2		T67	2
all_pins[3]	transitions[0x1=>0x0]	43	1			T8	3		T9	2		T10	1
all_pins[4]	values[0x0]	272	1			T2	5		T7	1		T8	2
all_pins[4]	values[0x1]	58	1			T8	3		T9	2		T10	2
all_pins[4]	transitions[0x0=>0x1]	41	1			T8	1		T9	2		T10	2
all_pins[4]	transitions[0x1=>0x0]	60	1			T2	2		T11	1		T68	1
all_pins[5]	values[0x0]	253	1			T2	3		T7	1		T8	3
all_pins[5]	values[0x1]	77	1			T2	2		T8	2		T11	4
all_pins[5]	transitions[0x0=>0x1]	53	1			T8	2		T11	4		T68	1
all_pins[5]	transitions[0x1=>0x0]	40	1			T8	1		T9	2		T11	1
all_pins[6]	values[0x0]	266	1			T2	3		T7	1		T8	4
all_pins[6]	values[0x1]	64	1			T2	2		T8	1		T9	2
all_pins[6]	transitions[0x0=>0x1]	48	1			T9	2		T11	1		T59	1
all_pins[6]	transitions[0x1=>0x0]	43	1			T9	1		T10	1		T59	2
all_pins[7]	values[0x0]	271	1			T2	3		T7	1		T8	4
all_pins[7]	values[0x1]	59	1			T2	2		T8	1		T9	1
all_pins[7]	transitions[0x0=>0x1]	45	1			T8	1		T9	1		T10	1
all_pins[7]	transitions[0x1=>0x0]	45	1			T2	1		T8	2		T11	1
all_pins[8]	values[0x0]	271	1			T2	2		T7	1		T8	3
all_pins[8]	values[0x1]	59	1			T2	3		T8	2		T11	1
all_pins[8]	transitions[0x0=>0x1]	49	1			T2	3		T11	1		T68	4
all_pins[8]	transitions[0x1=>0x0]	49	1			T8	1		T10	3		T11	3
all_pins[9]	values[0x0]	271	1			T2	5		T7	1		T8	2
all_pins[9]	values[0x1]	59	1			T8	3		T10	3		T11	3
all_pins[9]	transitions[0x0=>0x1]	45	1			T8	2		T10	2		T11	2
all_pins[9]	transitions[0x1=>0x0]	37	1			T11	1		T59	1		T68	3
all_pins[10]	values[0x0]	279	1			T2	5		T7	1		T8	4
all_pins[10]	values[0x1]	51	1			T8	1		T10	1		T11	2
all_pins[10]	transitions[0x0=>0x1]	39	1			T8	1		T10	1		T59	1
all_pins[10]	transitions[0x1=>0x0]	31	1			T9	1		T59	1		T69	1
all_pins[11]	values[0x0]	287	1			T2	5		T7	1		T8	5
all_pins[11]	values[0x1]	43	1			T9	1		T11	2		T59	1
all_pins[11]	transitions[0x0=>0x1]	35	1			T11	1		T59	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	39	1			T2	2		T9	1		T11	2
all_pins[12]	values[0x0]	283	1			T2	3		T7	1		T8	5
all_pins[12]	values[0x1]	47	1			T2	2		T9	2		T11	3
all_pins[12]	transitions[0x0=>0x1]	38	1			T2	2		T9	2		T68	1
all_pins[12]	transitions[0x1=>0x0]	41	1			T10	1		T11	2		T69	1
all_pins[13]	values[0x0]	280	1			T2	5		T7	1		T8	5
all_pins[13]	values[0x1]	50	1			T10	1		T11	5		T69	2
all_pins[13]	transitions[0x0=>0x1]	41	1			T10	1		T11	5		T69	2
all_pins[13]	transitions[0x1=>0x0]	52	1			T10	1		T59	1		T65	2
all_pins[14]	values[0x0]	269	1			T2	5		T7	1		T8	5
all_pins[14]	values[0x1]	61	1			T10	1		T59	1		T65	2
all_pins[14]	transitions[0x0=>0x1]	34	1			T10	1		T59	1		T66	2
all_pins[14]	transitions[0x1=>0x0]	33	1			T2	2		T11	1		T59	1