| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 59.19 | 52.83 | 59.96 | 94.44 | 0.00 | 53.33 | 100.00 | 53.78 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 49.75 | 49.75 | 50.29 | 50.29 | 52.57 | 52.57 | 91.30 | 91.30 | 0.00 | 0.00 | 51.50 | 51.50 | 95.83 | 95.83 | 6.72 | 6.72 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2185845020 |
| 55.47 | 5.73 | 52.16 | 1.87 | 57.45 | 4.88 | 97.19 | 5.88 | 0.00 | 0.00 | 53.22 | 1.72 | 95.83 | 0.00 | 32.46 | 25.74 | /workspace/coverage/cover_reg_top/10.i2c_intr_test.2423764288 |
| 58.04 | 2.56 | 52.16 | 0.00 | 59.01 | 1.56 | 99.49 | 2.30 | 0.00 | 0.00 | 53.33 | 0.11 | 96.79 | 0.96 | 45.48 | 13.03 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3266854680 |
| 58.67 | 0.64 | 52.16 | 0.00 | 59.01 | 0.00 | 99.49 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 99.68 | 2.88 | 47.06 | 1.58 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2019104546 |
| 59.24 | 0.56 | 52.16 | 0.00 | 59.01 | 0.00 | 99.74 | 0.26 | 0.00 | 0.00 | 53.33 | 0.00 | 99.68 | 0.00 | 50.74 | 3.68 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.17164361 |
| 59.40 | 0.17 | 52.16 | 0.00 | 59.01 | 0.00 | 99.74 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 99.68 | 0.00 | 51.89 | 1.16 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.56148121 |
| 59.56 | 0.16 | 52.83 | 0.67 | 59.35 | 0.34 | 99.74 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 99.68 | 0.00 | 52.00 | 0.11 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1673696937 |
| 59.68 | 0.12 | 52.83 | 0.00 | 59.35 | 0.00 | 99.74 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.32 | 52.52 | 0.53 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3345547194 |
| 59.76 | 0.08 | 52.83 | 0.00 | 59.35 | 0.00 | 100.00 | 0.26 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 52.84 | 0.32 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.550993119 |
| 59.82 | 0.06 | 52.83 | 0.00 | 59.35 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.26 | 0.42 | /workspace/coverage/cover_reg_top/26.i2c_intr_test.2303453053 |
| 59.87 | 0.04 | 52.83 | 0.00 | 59.55 | 0.20 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.36 | 0.11 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3291987274 |
| 59.91 | 0.04 | 52.83 | 0.00 | 59.82 | 0.27 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.36 | 0.00 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2792205215 |
| 59.94 | 0.03 | 52.83 | 0.00 | 59.82 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.57 | 0.21 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3351693273 |
| 59.96 | 0.02 | 52.83 | 0.00 | 59.89 | 0.07 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.68 | 0.11 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1605866122 |
| 59.98 | 0.02 | 52.83 | 0.00 | 59.89 | 0.00 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.78 | 0.11 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3590587322 |
| 59.99 | 0.01 | 52.83 | 0.00 | 59.96 | 0.07 | 100.00 | 0.00 | 0.00 | 0.00 | 53.33 | 0.00 | 100.00 | 0.00 | 53.78 | 0.00 | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3754881744 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.352981837 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2014340900 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1543024297 |
| /workspace/coverage/cover_reg_top/0.i2c_intr_test.2165830026 |
| /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.455014330 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2448455061 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.335418806 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3847255292 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.61991832 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.975497102 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2093101508 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.1035360626 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3837828078 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1356753086 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3467122184 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3087757409 |
| /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1757118726 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1139669686 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.503783953 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2617350535 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2944131710 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.3439041974 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3812060796 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3123932166 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3451160485 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3517358001 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4159510346 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.1299911302 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2213770462 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.576720843 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.371480824 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.3291751161 |
| /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.161405857 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4196668569 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2983667567 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1346281692 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.2941170766 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3417067676 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3676937354 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3104923931 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2390809926 |
| /workspace/coverage/cover_reg_top/15.i2c_intr_test.1507481257 |
| /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1134803476 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_errors.20881701 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2083504476 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.829846529 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.3765634136 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.784155401 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2977622813 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3649665168 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3630329827 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4101781707 |
| /workspace/coverage/cover_reg_top/17.i2c_intr_test.2872267357 |
| /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3349113573 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998495326 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4276500111 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2706064333 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.184648960 |
| /workspace/coverage/cover_reg_top/18.i2c_intr_test.2222049190 |
| /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.172253432 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2370063157 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1089072406 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1638976800 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.875986650 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.3444597434 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1863414652 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1863706048 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.874939974 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4016054022 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.800881613 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1408141741 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1137038782 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3529739811 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.1149528489 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3759845736 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1639430753 |
| /workspace/coverage/cover_reg_top/20.i2c_intr_test.2615696329 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.104825030 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.3135557989 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.3955453683 |
| /workspace/coverage/cover_reg_top/24.i2c_intr_test.1798430280 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.73702922 |
| /workspace/coverage/cover_reg_top/27.i2c_intr_test.90288723 |
| /workspace/coverage/cover_reg_top/28.i2c_intr_test.2602166581 |
| /workspace/coverage/cover_reg_top/29.i2c_intr_test.1503349309 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1520509103 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2710727735 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1511020531 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3208788391 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1700973270 |
| /workspace/coverage/cover_reg_top/3.i2c_intr_test.1066185039 |
| /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.931876353 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1770504477 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4143160691 |
| /workspace/coverage/cover_reg_top/31.i2c_intr_test.483961600 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.548709995 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.3012497091 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.2847496129 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.417039333 |
| /workspace/coverage/cover_reg_top/37.i2c_intr_test.617951045 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.2986997780 |
| /workspace/coverage/cover_reg_top/39.i2c_intr_test.2882296725 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1799928682 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.971477681 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2644699101 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3907637986 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3439124836 |
| /workspace/coverage/cover_reg_top/4.i2c_intr_test.3236460975 |
| /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3503181723 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1799226514 |
| /workspace/coverage/cover_reg_top/40.i2c_intr_test.3255827987 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.3539240230 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.2133900442 |
| /workspace/coverage/cover_reg_top/43.i2c_intr_test.584805420 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.495359190 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.76025467 |
| /workspace/coverage/cover_reg_top/47.i2c_intr_test.770954652 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.1312583479 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.4081967055 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3207758766 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1021106942 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.2614787322 |
| /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1197509125 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2544848697 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4179489392 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.883114159 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2737288720 |
| /workspace/coverage/cover_reg_top/6.i2c_intr_test.1777847805 |
| /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.30251493 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1678074139 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2900127949 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.61160520 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1987620705 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.1705715237 |
| /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3194742195 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.781421337 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.87587376 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1398485013 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1041261111 |
| /workspace/coverage/cover_reg_top/8.i2c_intr_test.3252352794 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2210633489 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1676489136 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.375202628 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3554508531 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.935332231 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.1647849157 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1834101035 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.390095294 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.190807278 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2210633489 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:07 PM PDT 24 | 30052706 ps | ||
| T2 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.550993119 | Mar 14 12:24:44 PM PDT 24 | Mar 14 12:24:45 PM PDT 24 | 40272654 ps | ||
| T3 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2019104546 | Mar 14 12:19:08 PM PDT 24 | Mar 14 12:19:13 PM PDT 24 | 104120486 ps | ||
| T4 | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.87587376 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:31 PM PDT 24 | 50527481 ps | ||
| T7 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1676489136 | Mar 14 12:22:44 PM PDT 24 | Mar 14 12:22:47 PM PDT 24 | 113089496 ps | ||
| T12 | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.971477681 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:05 PM PDT 24 | 249549698 ps | ||
| T5 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2185845020 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:11 PM PDT 24 | 133095216 ps | ||
| T13 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.30251493 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:30 PM PDT 24 | 92058637 ps | ||
| T14 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1197509125 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 36198929 ps | ||
| T8 | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1149528489 | Mar 14 12:24:42 PM PDT 24 | Mar 14 12:24:43 PM PDT 24 | 19570681 ps | ||
| T9 | /workspace/coverage/cover_reg_top/26.i2c_intr_test.2303453053 | Mar 14 12:24:33 PM PDT 24 | Mar 14 12:24:34 PM PDT 24 | 15939682 ps | ||
| T10 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.1507481257 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:34 PM PDT 24 | 19470590 ps | ||
| T23 | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.829846529 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 74853225 ps | ||
| T6 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1673696937 | Mar 14 12:22:26 PM PDT 24 | Mar 14 12:22:28 PM PDT 24 | 91675886 ps | ||
| T11 | /workspace/coverage/cover_reg_top/10.i2c_intr_test.2423764288 | Mar 14 12:22:45 PM PDT 24 | Mar 14 12:22:46 PM PDT 24 | 18716506 ps | ||
| T59 | /workspace/coverage/cover_reg_top/19.i2c_intr_test.3444597434 | Mar 14 12:24:33 PM PDT 24 | Mar 14 12:24:34 PM PDT 24 | 24558726 ps | ||
| T24 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4179489392 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:31 PM PDT 24 | 161790663 ps | ||
| T26 | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3417067676 | Mar 14 12:23:09 PM PDT 24 | Mar 14 12:23:10 PM PDT 24 | 78906744 ps | ||
| T15 | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2706064333 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 30282558 ps | ||
| T16 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3266854680 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:39 PM PDT 24 | 124478825 ps | ||
| T17 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3554508531 | Mar 14 12:22:54 PM PDT 24 | Mar 14 12:22:55 PM PDT 24 | 79778411 ps | ||
| T43 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3759845736 | Mar 14 12:19:58 PM PDT 24 | Mar 14 12:19:59 PM PDT 24 | 85438660 ps | ||
| T27 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1834101035 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 58869406 ps | ||
| T28 | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.172253432 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:12 PM PDT 24 | 154460307 ps | ||
| T68 | /workspace/coverage/cover_reg_top/1.i2c_intr_test.1035360626 | Mar 14 12:23:07 PM PDT 24 | Mar 14 12:23:08 PM PDT 24 | 35709928 ps | ||
| T44 | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1987620705 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 44489747 ps | ||
| T18 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3467122184 | Mar 14 12:22:52 PM PDT 24 | Mar 14 12:22:53 PM PDT 24 | 77414375 ps | ||
| T45 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3345547194 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 41452418 ps | ||
| T29 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3087757409 | Mar 14 12:22:51 PM PDT 24 | Mar 14 12:22:52 PM PDT 24 | 19481854 ps | ||
| T30 | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3439124836 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 38621642 ps | ||
| T69 | /workspace/coverage/cover_reg_top/38.i2c_intr_test.2986997780 | Mar 14 12:24:28 PM PDT 24 | Mar 14 12:24:29 PM PDT 24 | 57418363 ps | ||
| T65 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.3291751161 | Mar 14 12:22:41 PM PDT 24 | Mar 14 12:22:42 PM PDT 24 | 47505627 ps | ||
| T31 | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.61991832 | Mar 14 12:23:18 PM PDT 24 | Mar 14 12:23:21 PM PDT 24 | 60968332 ps | ||
| T19 | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.375202628 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:08 PM PDT 24 | 266424042 ps | ||
| T57 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1799928682 | Mar 14 12:24:14 PM PDT 24 | Mar 14 12:24:15 PM PDT 24 | 51517750 ps | ||
| T32 | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1041261111 | Mar 14 12:22:44 PM PDT 24 | Mar 14 12:22:45 PM PDT 24 | 18968034 ps | ||
| T20 | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3517358001 | Mar 14 12:22:40 PM PDT 24 | Mar 14 12:22:41 PM PDT 24 | 106789079 ps | ||
| T77 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1863414652 | Mar 14 12:24:17 PM PDT 24 | Mar 14 12:24:19 PM PDT 24 | 47518623 ps | ||
| T21 | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3676937354 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:14 PM PDT 24 | 265570536 ps | ||
| T22 | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1089072406 | Mar 14 12:23:16 PM PDT 24 | Mar 14 12:23:17 PM PDT 24 | 220953321 ps | ||
| T66 | /workspace/coverage/cover_reg_top/7.i2c_intr_test.1705715237 | Mar 14 12:24:14 PM PDT 24 | Mar 14 12:24:14 PM PDT 24 | 15355094 ps | ||
| T78 | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1021106942 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 70459074 ps | ||
| T62 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2644699101 | Mar 14 12:24:01 PM PDT 24 | Mar 14 12:24:02 PM PDT 24 | 74249778 ps | ||
| T79 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3252352794 | Mar 14 12:23:57 PM PDT 24 | Mar 14 12:23:59 PM PDT 24 | 44740774 ps | ||
| T58 | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.931876353 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:24 PM PDT 24 | 57330198 ps | ||
| T25 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2370063157 | Mar 14 12:24:21 PM PDT 24 | Mar 14 12:24:22 PM PDT 24 | 110224763 ps | ||
| T80 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3208788391 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 22025999 ps | ||
| T81 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1137038782 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:08 PM PDT 24 | 177927885 ps | ||
| T60 | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3104923931 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:13 PM PDT 24 | 42703077 ps | ||
| T67 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3255827987 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 21198811 ps | ||
| T76 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.17164361 | Mar 14 12:24:29 PM PDT 24 | Mar 14 12:24:30 PM PDT 24 | 29567133 ps | ||
| T47 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2900127949 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 126195503 ps | ||
| T82 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1134803476 | Mar 14 12:23:14 PM PDT 24 | Mar 14 12:23:15 PM PDT 24 | 53301957 ps | ||
| T83 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3907637986 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 42895809 ps | ||
| T50 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.503783953 | Mar 14 12:22:40 PM PDT 24 | Mar 14 12:22:42 PM PDT 24 | 427613766 ps | ||
| T84 | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4196668569 | Mar 14 12:22:51 PM PDT 24 | Mar 14 12:22:53 PM PDT 24 | 413852955 ps | ||
| T85 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2213770462 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:09 PM PDT 24 | 114461947 ps | ||
| T75 | /workspace/coverage/cover_reg_top/17.i2c_intr_test.2872267357 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 16198633 ps | ||
| T86 | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.784155401 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 35087091 ps | ||
| T70 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.56148121 | Mar 14 12:23:13 PM PDT 24 | Mar 14 12:23:14 PM PDT 24 | 29613084 ps | ||
| T87 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3630329827 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:13 PM PDT 24 | 82085813 ps | ||
| T88 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4159510346 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 25204053 ps | ||
| T46 | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3123932166 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:39 PM PDT 24 | 98994142 ps | ||
| T89 | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2617350535 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 57667740 ps | ||
| T49 | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1799226514 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:31 PM PDT 24 | 116328237 ps | ||
| T33 | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.875986650 | Mar 14 12:24:26 PM PDT 24 | Mar 14 12:24:27 PM PDT 24 | 75688879 ps | ||
| T48 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1356753086 | Mar 14 12:23:51 PM PDT 24 | Mar 14 12:23:54 PM PDT 24 | 472526568 ps | ||
| T71 | /workspace/coverage/cover_reg_top/41.i2c_intr_test.3539240230 | Mar 14 12:24:27 PM PDT 24 | Mar 14 12:24:28 PM PDT 24 | 28802066 ps | ||
| T73 | /workspace/coverage/cover_reg_top/22.i2c_intr_test.3135557989 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:11 PM PDT 24 | 20355774 ps | ||
| T90 | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4101781707 | Mar 14 12:23:14 PM PDT 24 | Mar 14 12:23:16 PM PDT 24 | 31271185 ps | ||
| T54 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.190807278 | Mar 14 12:22:40 PM PDT 24 | Mar 14 12:22:42 PM PDT 24 | 95909015 ps | ||
| T91 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.975497102 | Mar 14 12:23:15 PM PDT 24 | Mar 14 12:23:16 PM PDT 24 | 31527116 ps | ||
| T92 | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998495326 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 49822967 ps | ||
| T93 | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.883114159 | Mar 14 12:24:08 PM PDT 24 | Mar 14 12:24:10 PM PDT 24 | 27598773 ps | ||
| T52 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.335418806 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:36 PM PDT 24 | 201206872 ps | ||
| T94 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3349113573 | Mar 14 12:23:13 PM PDT 24 | Mar 14 12:23:14 PM PDT 24 | 79145733 ps | ||
| T95 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1520509103 | Mar 14 12:22:02 PM PDT 24 | Mar 14 12:22:03 PM PDT 24 | 168763755 ps | ||
| T96 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.161405857 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:13 PM PDT 24 | 156059913 ps | ||
| T51 | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4276500111 | Mar 14 12:23:39 PM PDT 24 | Mar 14 12:23:42 PM PDT 24 | 98625548 ps | ||
| T97 | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2544848697 | Mar 14 12:24:15 PM PDT 24 | Mar 14 12:24:16 PM PDT 24 | 25915236 ps | ||
| T63 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1408141741 | Mar 14 12:23:42 PM PDT 24 | Mar 14 12:23:43 PM PDT 24 | 144327283 ps | ||
| T98 | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1770504477 | Mar 14 12:23:33 PM PDT 24 | Mar 14 12:23:35 PM PDT 24 | 183901552 ps | ||
| T74 | /workspace/coverage/cover_reg_top/14.i2c_intr_test.2941170766 | Mar 14 12:23:14 PM PDT 24 | Mar 14 12:23:14 PM PDT 24 | 20242020 ps | ||
| T99 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2792205215 | Mar 14 12:24:15 PM PDT 24 | Mar 14 12:24:17 PM PDT 24 | 87594191 ps | ||
| T100 | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2390809926 | Mar 14 12:24:15 PM PDT 24 | Mar 14 12:24:17 PM PDT 24 | 17675001 ps | ||
| T101 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1638976800 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 33504797 ps | ||
| T102 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2083504476 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 23561730 ps | ||
| T103 | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1543024297 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:24 PM PDT 24 | 40066416 ps | ||
| T104 | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1647849157 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 21134263 ps | ||
| T72 | /workspace/coverage/cover_reg_top/43.i2c_intr_test.584805420 | Mar 14 12:23:26 PM PDT 24 | Mar 14 12:23:27 PM PDT 24 | 16634835 ps | ||
| T34 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.352981837 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:25 PM PDT 24 | 81006084 ps | ||
| T105 | /workspace/coverage/cover_reg_top/33.i2c_intr_test.3012497091 | Mar 14 12:23:39 PM PDT 24 | Mar 14 12:23:41 PM PDT 24 | 29088735 ps | ||
| T106 | /workspace/coverage/cover_reg_top/49.i2c_intr_test.4081967055 | Mar 14 12:24:57 PM PDT 24 | Mar 14 12:24:58 PM PDT 24 | 42815263 ps | ||
| T107 | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3837828078 | Mar 14 12:22:54 PM PDT 24 | Mar 14 12:22:57 PM PDT 24 | 220629707 ps | ||
| T108 | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1139669686 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 106795997 ps | ||
| T109 | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2977622813 | Mar 14 12:23:16 PM PDT 24 | Mar 14 12:23:18 PM PDT 24 | 172105971 ps | ||
| T110 | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2614787322 | Mar 14 12:24:13 PM PDT 24 | Mar 14 12:24:14 PM PDT 24 | 20337323 ps | ||
| T111 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1398485013 | Mar 14 12:22:41 PM PDT 24 | Mar 14 12:22:42 PM PDT 24 | 26226526 ps | ||
| T112 | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3765634136 | Mar 14 12:24:17 PM PDT 24 | Mar 14 12:24:19 PM PDT 24 | 27566634 ps | ||
| T113 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.2602166581 | Mar 14 12:23:08 PM PDT 24 | Mar 14 12:23:09 PM PDT 24 | 49274093 ps | ||
| T114 | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.61160520 | Mar 14 12:22:45 PM PDT 24 | Mar 14 12:22:46 PM PDT 24 | 69745827 ps | ||
| T115 | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.390095294 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:09 PM PDT 24 | 142783470 ps | ||
| T116 | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3207758766 | Mar 14 12:24:01 PM PDT 24 | Mar 14 12:24:02 PM PDT 24 | 30126095 ps | ||
| T117 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1863706048 | Mar 14 12:24:55 PM PDT 24 | Mar 14 12:24:58 PM PDT 24 | 118963481 ps | ||
| T118 | /workspace/coverage/cover_reg_top/36.i2c_intr_test.417039333 | Mar 14 12:24:26 PM PDT 24 | Mar 14 12:24:27 PM PDT 24 | 25323855 ps | ||
| T55 | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4143160691 | Mar 14 12:24:07 PM PDT 24 | Mar 14 12:24:10 PM PDT 24 | 483937262 ps | ||
| T61 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3351693273 | Mar 14 12:23:27 PM PDT 24 | Mar 14 12:23:29 PM PDT 24 | 56548184 ps | ||
| T35 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3847255292 | Mar 14 12:23:18 PM PDT 24 | Mar 14 12:23:20 PM PDT 24 | 64716106 ps | ||
| T119 | /workspace/coverage/cover_reg_top/25.i2c_intr_test.73702922 | Mar 14 12:23:08 PM PDT 24 | Mar 14 12:23:09 PM PDT 24 | 25042638 ps | ||
| T120 | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3194742195 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 18299266 ps | ||
| T121 | /workspace/coverage/cover_reg_top/34.i2c_intr_test.2847496129 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 37560009 ps | ||
| T122 | /workspace/coverage/cover_reg_top/0.i2c_intr_test.2165830026 | Mar 14 12:23:31 PM PDT 24 | Mar 14 12:23:32 PM PDT 24 | 183474935 ps | ||
| T123 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.2133900442 | Mar 14 12:23:24 PM PDT 24 | Mar 14 12:23:26 PM PDT 24 | 21324436 ps | ||
| T36 | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.184648960 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:11 PM PDT 24 | 18229453 ps | ||
| T124 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.770954652 | Mar 14 12:24:55 PM PDT 24 | Mar 14 12:24:57 PM PDT 24 | 59908285 ps | ||
| T125 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.781421337 | Mar 14 12:24:21 PM PDT 24 | Mar 14 12:24:23 PM PDT 24 | 200632582 ps | ||
| T56 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3291987274 | Mar 14 12:23:06 PM PDT 24 | Mar 14 12:23:09 PM PDT 24 | 1237530977 ps | ||
| T126 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.2222049190 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:13 PM PDT 24 | 19470210 ps | ||
| T127 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.800881613 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:48 PM PDT 24 | 330219382 ps | ||
| T128 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.455014330 | Mar 14 12:23:51 PM PDT 24 | Mar 14 12:23:53 PM PDT 24 | 88194201 ps | ||
| T129 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2882296725 | Mar 14 12:23:09 PM PDT 24 | Mar 14 12:23:10 PM PDT 24 | 36423851 ps | ||
| T130 | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3439041974 | Mar 14 12:22:41 PM PDT 24 | Mar 14 12:22:42 PM PDT 24 | 50979946 ps | ||
| T131 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3529739811 | Mar 14 12:23:44 PM PDT 24 | Mar 14 12:23:46 PM PDT 24 | 32659052 ps | ||
| T132 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.617951045 | Mar 14 12:24:26 PM PDT 24 | Mar 14 12:24:27 PM PDT 24 | 18667164 ps | ||
| T133 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1503349309 | Mar 14 12:23:08 PM PDT 24 | Mar 14 12:23:09 PM PDT 24 | 16506692 ps | ||
| T134 | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.576720843 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:11 PM PDT 24 | 65197649 ps | ||
| T53 | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3754881744 | Mar 14 12:23:24 PM PDT 24 | Mar 14 12:23:26 PM PDT 24 | 229160706 ps | ||
| T64 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1605866122 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:25 PM PDT 24 | 153564953 ps | ||
| T37 | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1346281692 | Mar 14 12:24:55 PM PDT 24 | Mar 14 12:24:57 PM PDT 24 | 50759277 ps | ||
| T135 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3503181723 | Mar 14 12:24:08 PM PDT 24 | Mar 14 12:24:09 PM PDT 24 | 60632227 ps | ||
| T136 | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.371480824 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:07 PM PDT 24 | 54219421 ps | ||
| T137 | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2093101508 | Mar 14 12:23:33 PM PDT 24 | Mar 14 12:23:34 PM PDT 24 | 20129377 ps | ||
| T138 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.20881701 | Mar 14 12:23:06 PM PDT 24 | Mar 14 12:23:08 PM PDT 24 | 180865372 ps | ||
| T139 | /workspace/coverage/cover_reg_top/46.i2c_intr_test.76025467 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:30 PM PDT 24 | 27629821 ps | ||
| T140 | /workspace/coverage/cover_reg_top/27.i2c_intr_test.90288723 | Mar 14 12:23:14 PM PDT 24 | Mar 14 12:23:16 PM PDT 24 | 47750670 ps | ||
| T141 | /workspace/coverage/cover_reg_top/32.i2c_intr_test.548709995 | Mar 14 12:24:34 PM PDT 24 | Mar 14 12:24:35 PM PDT 24 | 21454878 ps | ||
| T142 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1639430753 | Mar 14 12:24:59 PM PDT 24 | Mar 14 12:25:00 PM PDT 24 | 78409176 ps | ||
| T143 | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2944131710 | Mar 14 12:23:57 PM PDT 24 | Mar 14 12:23:59 PM PDT 24 | 41349066 ps | ||
| T144 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.1312583479 | Mar 14 12:24:43 PM PDT 24 | Mar 14 12:24:44 PM PDT 24 | 44782322 ps | ||
| T145 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.1798430280 | Mar 14 12:24:21 PM PDT 24 | Mar 14 12:24:22 PM PDT 24 | 17154716 ps | ||
| T146 | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3812060796 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:24 PM PDT 24 | 346746217 ps | ||
| T147 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.483961600 | Mar 14 12:23:10 PM PDT 24 | Mar 14 12:23:11 PM PDT 24 | 46638741 ps | ||
| T38 | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.935332231 | Mar 14 12:24:19 PM PDT 24 | Mar 14 12:24:21 PM PDT 24 | 55094001 ps | ||
| T39 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1511020531 | Mar 14 12:22:04 PM PDT 24 | Mar 14 12:22:04 PM PDT 24 | 44805820 ps | ||
| T148 | /workspace/coverage/cover_reg_top/12.i2c_intr_test.1299911302 | Mar 14 12:22:58 PM PDT 24 | Mar 14 12:22:58 PM PDT 24 | 35685224 ps | ||
| T149 | /workspace/coverage/cover_reg_top/3.i2c_intr_test.1066185039 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:42 PM PDT 24 | 32750504 ps | ||
| T150 | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2983667567 | Mar 14 12:23:12 PM PDT 24 | Mar 14 12:23:13 PM PDT 24 | 24426416 ps | ||
| T151 | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3649665168 | Mar 14 12:23:06 PM PDT 24 | Mar 14 12:23:08 PM PDT 24 | 154108467 ps | ||
| T152 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1678074139 | Mar 14 12:24:15 PM PDT 24 | Mar 14 12:24:16 PM PDT 24 | 81510077 ps | ||
| T40 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3590587322 | Mar 14 12:18:55 PM PDT 24 | Mar 14 12:18:56 PM PDT 24 | 96665138 ps | ||
| T153 | /workspace/coverage/cover_reg_top/21.i2c_intr_test.104825030 | Mar 14 12:23:16 PM PDT 24 | Mar 14 12:23:17 PM PDT 24 | 21462830 ps | ||
| T154 | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2014340900 | Mar 14 12:20:14 PM PDT 24 | Mar 14 12:20:15 PM PDT 24 | 70876774 ps | ||
| T41 | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1700973270 | Mar 14 12:23:38 PM PDT 24 | Mar 14 12:23:39 PM PDT 24 | 78605758 ps | ||
| T155 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3451160485 | Mar 14 12:24:23 PM PDT 24 | Mar 14 12:24:25 PM PDT 24 | 491652097 ps | ||
| T156 | /workspace/coverage/cover_reg_top/4.i2c_intr_test.3236460975 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 47767436 ps | ||
| T157 | /workspace/coverage/cover_reg_top/23.i2c_intr_test.3955453683 | Mar 14 12:24:26 PM PDT 24 | Mar 14 12:24:27 PM PDT 24 | 44035396 ps | ||
| T158 | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2737288720 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 45843170 ps | ||
| T159 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1757118726 | Mar 14 12:24:36 PM PDT 24 | Mar 14 12:24:37 PM PDT 24 | 49123237 ps | ||
| T160 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2448455061 | Mar 14 12:20:01 PM PDT 24 | Mar 14 12:20:03 PM PDT 24 | 115649798 ps | ||
| T42 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4016054022 | Mar 14 12:23:42 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 329298815 ps | ||
| T161 | /workspace/coverage/cover_reg_top/45.i2c_intr_test.495359190 | Mar 14 12:23:24 PM PDT 24 | Mar 14 12:23:25 PM PDT 24 | 19393917 ps | ||
| T162 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.1777847805 | Mar 14 12:24:07 PM PDT 24 | Mar 14 12:24:08 PM PDT 24 | 17740025 ps | ||
| T163 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2615696329 | Mar 14 12:23:16 PM PDT 24 | Mar 14 12:23:17 PM PDT 24 | 27816974 ps | ||
| T164 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2710727735 | Mar 14 12:23:38 PM PDT 24 | Mar 14 12:23:43 PM PDT 24 | 473880249 ps | ||
| T165 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.874939974 | Mar 14 12:23:16 PM PDT 24 | Mar 14 12:23:18 PM PDT 24 | 712626046 ps |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2185845020 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 133095216 ps |
| CPU time | 1.26 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:11 PM PDT 24 |
| Peak memory | 202652 kb |
| Host | smart-82d6cdf6-9fc3-42c1-8735-02b1a516c86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185845020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2185845020 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.2423764288 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 18716506 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:22:45 PM PDT 24 |
| Finished | Mar 14 12:22:46 PM PDT 24 |
| Peak memory | 202500 kb |
| Host | smart-608991da-620b-4eac-be60-ff99ae762d67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423764288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2423764288 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3266854680 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 124478825 ps |
| CPU time | 2.55 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:39 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-4752da24-1350-4273-85c8-ce27293ae6a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266854680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3266854680 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2019104546 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 104120486 ps |
| CPU time | 4.04 seconds |
| Started | Mar 14 12:19:08 PM PDT 24 |
| Finished | Mar 14 12:19:13 PM PDT 24 |
| Peak memory | 202496 kb |
| Host | smart-98a236ba-9c3f-40e3-9ce3-7267dd2ccde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019104546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2019104546 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.17164361 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29567133 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:24:29 PM PDT 24 |
| Finished | Mar 14 12:24:30 PM PDT 24 |
| Peak memory | 202368 kb |
| Host | smart-c3861dd1-73f2-43c2-88b1-a00bb8348b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17164361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.17164361 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.56148121 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 29613084 ps |
| CPU time | 0.75 seconds |
| Started | Mar 14 12:23:13 PM PDT 24 |
| Finished | Mar 14 12:23:14 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-dbee92e5-92fc-4054-a9db-0830fd567bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56148121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.56148121 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1673696937 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 91675886 ps |
| CPU time | 1.33 seconds |
| Started | Mar 14 12:22:26 PM PDT 24 |
| Finished | Mar 14 12:22:28 PM PDT 24 |
| Peak memory | 202760 kb |
| Host | smart-c48976ce-8d30-4db9-9501-d535e6df7d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673696937 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1673696937 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3345547194 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 41452418 ps |
| CPU time | 0.94 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202576 kb |
| Host | smart-9d085a94-d3cc-4036-b77b-623fca6fe6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345547194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.3345547194 |
| Directory | /workspace/12.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.550993119 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 40272654 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:44 PM PDT 24 |
| Finished | Mar 14 12:24:45 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-2f35fe90-367e-4816-b30a-6ea24d4e95bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550993119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.550993119 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.2303453053 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15939682 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:33 PM PDT 24 |
| Finished | Mar 14 12:24:34 PM PDT 24 |
| Peak memory | 202372 kb |
| Host | smart-6fe01cc8-c433-42b9-94e7-0a47a40c41e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303453053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2303453053 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3291987274 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1237530977 ps |
| CPU time | 1.99 seconds |
| Started | Mar 14 12:23:06 PM PDT 24 |
| Finished | Mar 14 12:23:09 PM PDT 24 |
| Peak memory | 202612 kb |
| Host | smart-1ceb1631-1044-413b-841d-c7df6b669ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291987274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3291987274 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2792205215 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 87594191 ps |
| CPU time | 1.84 seconds |
| Started | Mar 14 12:24:15 PM PDT 24 |
| Finished | Mar 14 12:24:17 PM PDT 24 |
| Peak memory | 202728 kb |
| Host | smart-c46a6d85-d6f4-42ce-8850-44bf608543d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792205215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2792205215 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3351693273 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 56548184 ps |
| CPU time | 1.13 seconds |
| Started | Mar 14 12:23:27 PM PDT 24 |
| Finished | Mar 14 12:23:29 PM PDT 24 |
| Peak memory | 202580 kb |
| Host | smart-535b909d-3687-4afd-a4de-cf4f683cd0a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351693273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.3351693273 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1605866122 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 153564953 ps |
| CPU time | 1.7 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:25 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-5c4e9701-0ec3-4b3a-9f9f-1ce883583711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605866122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1605866122 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3590587322 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 96665138 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:18:55 PM PDT 24 |
| Finished | Mar 14 12:18:56 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-0c20cffd-a3ee-4cc5-bc68-fe279af40a07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590587322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3590587322 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3754881744 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 229160706 ps |
| CPU time | 1.22 seconds |
| Started | Mar 14 12:23:24 PM PDT 24 |
| Finished | Mar 14 12:23:26 PM PDT 24 |
| Peak memory | 201452 kb |
| Host | smart-215039ca-d83e-4147-b87d-bfc871140eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754881744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3754881744 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.352981837 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 81006084 ps |
| CPU time | 1.44 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:25 PM PDT 24 |
| Peak memory | 202560 kb |
| Host | smart-6fa2519e-ce99-40c8-bbc7-5d87b7571c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352981837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.352981837 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2014340900 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 70876774 ps |
| CPU time | 0.8 seconds |
| Started | Mar 14 12:20:14 PM PDT 24 |
| Finished | Mar 14 12:20:15 PM PDT 24 |
| Peak memory | 202588 kb |
| Host | smart-2b793c42-2b4b-415a-a6e6-70074dde2c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014340900 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2014340900 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1543024297 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 40066416 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:24 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-3eec35a0-d56f-4305-942f-3e22e7c2b5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543024297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1543024297 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.2165830026 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 183474935 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:31 PM PDT 24 |
| Finished | Mar 14 12:23:32 PM PDT 24 |
| Peak memory | 200996 kb |
| Host | smart-eed346b5-4bbf-415b-9ab9-196b54d118ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165830026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2165830026 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.455014330 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 88194201 ps |
| CPU time | 0.95 seconds |
| Started | Mar 14 12:23:51 PM PDT 24 |
| Finished | Mar 14 12:23:53 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-2c9e9678-b643-4e3e-a8a0-4b57c4ec3e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455014330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.455014330 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2448455061 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 115649798 ps |
| CPU time | 2.25 seconds |
| Started | Mar 14 12:20:01 PM PDT 24 |
| Finished | Mar 14 12:20:03 PM PDT 24 |
| Peak memory | 202620 kb |
| Host | smart-3c0d7c49-f024-4e8a-803c-ff338f2f8d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448455061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2448455061 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.335418806 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 201206872 ps |
| CPU time | 1.75 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:36 PM PDT 24 |
| Peak memory | 202632 kb |
| Host | smart-49e72640-97b3-4988-9820-ed8587fa0d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335418806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.335418806 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3847255292 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 64716106 ps |
| CPU time | 1.01 seconds |
| Started | Mar 14 12:23:18 PM PDT 24 |
| Finished | Mar 14 12:23:20 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-d0688cf7-8abb-4166-b228-8daa111362bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847255292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3847255292 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.61991832 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 60968332 ps |
| CPU time | 2.27 seconds |
| Started | Mar 14 12:23:18 PM PDT 24 |
| Finished | Mar 14 12:23:21 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-86305f75-75ed-4492-bc7f-08100342c5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61991832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.61991832 |
| Directory | /workspace/1.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.975497102 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 31527116 ps |
| CPU time | 0.72 seconds |
| Started | Mar 14 12:23:15 PM PDT 24 |
| Finished | Mar 14 12:23:16 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-e7766d1e-2a96-4115-9cf9-de2d145880e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975497102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.975497102 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2093101508 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 20129377 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:23:33 PM PDT 24 |
| Finished | Mar 14 12:23:34 PM PDT 24 |
| Peak memory | 202384 kb |
| Host | smart-116d3643-1cfe-4562-a341-330cbb756085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093101508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2093101508 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.1035360626 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 35709928 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:23:07 PM PDT 24 |
| Finished | Mar 14 12:23:08 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-f78519ce-8d12-4180-b2e5-37b7e049262b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035360626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1035360626 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3837828078 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 220629707 ps |
| CPU time | 2.39 seconds |
| Started | Mar 14 12:22:54 PM PDT 24 |
| Finished | Mar 14 12:22:57 PM PDT 24 |
| Peak memory | 202808 kb |
| Host | smart-3b4dfdbc-0e0e-45cf-80c9-b8b8140edd28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837828078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3837828078 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1356753086 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 472526568 ps |
| CPU time | 1.89 seconds |
| Started | Mar 14 12:23:51 PM PDT 24 |
| Finished | Mar 14 12:23:54 PM PDT 24 |
| Peak memory | 202576 kb |
| Host | smart-35dd1e3d-84e5-464d-8f56-7a616b95c684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356753086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1356753086 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3467122184 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 77414375 ps |
| CPU time | 0.98 seconds |
| Started | Mar 14 12:22:52 PM PDT 24 |
| Finished | Mar 14 12:22:53 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-026f23d2-9c1e-48aa-9ab0-3ee143bb705d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467122184 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3467122184 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3087757409 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 19481854 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:22:51 PM PDT 24 |
| Finished | Mar 14 12:22:52 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-d0d86b1f-d29f-4748-b711-aa51d78b6614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087757409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3087757409 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1757118726 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 49123237 ps |
| CPU time | 0.82 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-db7893c7-0080-4ab2-8029-cb5aaf43d7e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757118726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.1757118726 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1139669686 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 106795997 ps |
| CPU time | 1.28 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202656 kb |
| Host | smart-325c3cc9-47a7-4fdf-808f-ff3ce2e69219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139669686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1139669686 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.503783953 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 427613766 ps |
| CPU time | 1.95 seconds |
| Started | Mar 14 12:22:40 PM PDT 24 |
| Finished | Mar 14 12:22:42 PM PDT 24 |
| Peak memory | 202704 kb |
| Host | smart-8f55a580-5f20-439c-9ae5-e9cf3dbef844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503783953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.503783953 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2617350535 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 57667740 ps |
| CPU time | 0.87 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-bb81847d-9bd9-4f15-8f11-b37c2910f661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617350535 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2617350535 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2944131710 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 41349066 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:57 PM PDT 24 |
| Finished | Mar 14 12:23:59 PM PDT 24 |
| Peak memory | 200612 kb |
| Host | smart-25a15fa7-262f-4d0f-aae8-4962f1e99539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944131710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2944131710 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3439041974 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 50979946 ps |
| CPU time | 0.77 seconds |
| Started | Mar 14 12:22:41 PM PDT 24 |
| Finished | Mar 14 12:22:42 PM PDT 24 |
| Peak memory | 202556 kb |
| Host | smart-fee11abf-6cac-4c72-bbbf-16a3f0fbd1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439041974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3439041974 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3812060796 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 346746217 ps |
| CPU time | 0.97 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:24 PM PDT 24 |
| Peak memory | 202672 kb |
| Host | smart-c4211bda-7e1b-4cb6-9cf2-53b61417194d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812060796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.3812060796 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3123932166 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 98994142 ps |
| CPU time | 2.13 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:39 PM PDT 24 |
| Peak memory | 202360 kb |
| Host | smart-9e0aa103-14a7-45fe-9e3a-2f5d4faa5873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123932166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3123932166 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3451160485 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 491652097 ps |
| CPU time | 1.92 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:25 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-0feaa1c5-e216-44ae-b382-d7e23212f08c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451160485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3451160485 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3517358001 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 106789079 ps |
| CPU time | 0.99 seconds |
| Started | Mar 14 12:22:40 PM PDT 24 |
| Finished | Mar 14 12:22:41 PM PDT 24 |
| Peak memory | 202616 kb |
| Host | smart-daf0ff27-2c36-47c3-b024-205ff35cc77e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517358001 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3517358001 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4159510346 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 25204053 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-395fb45e-2945-4c75-b95a-f3030673be1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159510346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.4159510346 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.1299911302 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 35685224 ps |
| CPU time | 0.72 seconds |
| Started | Mar 14 12:22:58 PM PDT 24 |
| Finished | Mar 14 12:22:58 PM PDT 24 |
| Peak memory | 202464 kb |
| Host | smart-ed9ce701-ee02-4730-9281-b640edc5f236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299911302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1299911302 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2213770462 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 114461947 ps |
| CPU time | 2.1 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:09 PM PDT 24 |
| Peak memory | 202564 kb |
| Host | smart-d868a2dd-e189-4dd9-af5d-5def1b994e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213770462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2213770462 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.576720843 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 65197649 ps |
| CPU time | 0.93 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:11 PM PDT 24 |
| Peak memory | 202612 kb |
| Host | smart-82f04220-cf9d-4a16-91ef-9d001dbbf611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576720843 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.576720843 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.371480824 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 54219421 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:07 PM PDT 24 |
| Peak memory | 202328 kb |
| Host | smart-ed0f37de-79e7-4438-93b6-911c70dd4df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371480824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.371480824 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.3291751161 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 47505627 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:22:41 PM PDT 24 |
| Finished | Mar 14 12:22:42 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-6706da25-aaf6-4c07-bc40-2220d2da5c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291751161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3291751161 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.161405857 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 156059913 ps |
| CPU time | 1.23 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:13 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-05acb0de-1ef7-4364-b6ad-c25ea0e9fdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161405857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou tstanding.161405857 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4196668569 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 413852955 ps |
| CPU time | 1.97 seconds |
| Started | Mar 14 12:22:51 PM PDT 24 |
| Finished | Mar 14 12:22:53 PM PDT 24 |
| Peak memory | 202712 kb |
| Host | smart-97cadc64-cc65-4bd3-96e6-63d4d2796bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196668569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4196668569 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2983667567 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 24426416 ps |
| CPU time | 0.88 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:13 PM PDT 24 |
| Peak memory | 202740 kb |
| Host | smart-c34985d6-497b-4124-9bec-0230a41cb7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983667567 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2983667567 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1346281692 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 50759277 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 199976 kb |
| Host | smart-b9d1ea60-2cf9-40d0-916b-8d8d5ac4cafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346281692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1346281692 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.2941170766 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20242020 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:23:14 PM PDT 24 |
| Finished | Mar 14 12:23:14 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-c80a20b1-4933-48cd-9fa7-406da5cd15b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941170766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2941170766 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3417067676 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 78906744 ps |
| CPU time | 0.98 seconds |
| Started | Mar 14 12:23:09 PM PDT 24 |
| Finished | Mar 14 12:23:10 PM PDT 24 |
| Peak memory | 203100 kb |
| Host | smart-adc61943-948c-463b-92b0-cf9785b31bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417067676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.3417067676 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3676937354 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 265570536 ps |
| CPU time | 1.74 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:14 PM PDT 24 |
| Peak memory | 202760 kb |
| Host | smart-8eca1814-bb26-4f4e-b380-7fe93bdea5df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676937354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3676937354 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3104923931 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 42703077 ps |
| CPU time | 1.04 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:13 PM PDT 24 |
| Peak memory | 202740 kb |
| Host | smart-58e4b056-99db-4bfb-b8a5-0db5d7d5d50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104923931 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3104923931 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2390809926 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 17675001 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:24:15 PM PDT 24 |
| Finished | Mar 14 12:24:17 PM PDT 24 |
| Peak memory | 201196 kb |
| Host | smart-35d78800-7561-4382-b785-83f335da3dee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390809926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2390809926 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.1507481257 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19470590 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:34 PM PDT 24 |
| Peak memory | 202364 kb |
| Host | smart-c372f39f-49c0-4162-a6bf-f2e0ced5218e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507481257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1507481257 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1134803476 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 53301957 ps |
| CPU time | 0.87 seconds |
| Started | Mar 14 12:23:14 PM PDT 24 |
| Finished | Mar 14 12:23:15 PM PDT 24 |
| Peak memory | 202516 kb |
| Host | smart-91e76a66-d43d-492f-9f67-16dd0a68b16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134803476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1134803476 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.20881701 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 180865372 ps |
| CPU time | 2.19 seconds |
| Started | Mar 14 12:23:06 PM PDT 24 |
| Finished | Mar 14 12:23:08 PM PDT 24 |
| Peak memory | 202740 kb |
| Host | smart-8da0077b-abf2-4af8-9da0-065c5f6fc1cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20881701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.20881701 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2083504476 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 23561730 ps |
| CPU time | 0.73 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-3276ea55-ed52-4011-99cd-b0de6a6b8be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083504476 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2083504476 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.829846529 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 74853225 ps |
| CPU time | 0.72 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-bd04b7ba-506d-40eb-b1aa-c6ced45b5bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829846529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.829846529 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3765634136 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 27566634 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:17 PM PDT 24 |
| Finished | Mar 14 12:24:19 PM PDT 24 |
| Peak memory | 201420 kb |
| Host | smart-0053ee5d-906b-40f5-a114-e0b8bc69511d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765634136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3765634136 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.784155401 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 35087091 ps |
| CPU time | 0.8 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-813cfb85-c032-4005-850d-ef8cc4c2f6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784155401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou tstanding.784155401 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2977622813 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 172105971 ps |
| CPU time | 2.06 seconds |
| Started | Mar 14 12:23:16 PM PDT 24 |
| Finished | Mar 14 12:23:18 PM PDT 24 |
| Peak memory | 202712 kb |
| Host | smart-c7ceb026-a475-4c57-b6a3-a0e68b8096e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977622813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2977622813 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3649665168 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 154108467 ps |
| CPU time | 1.42 seconds |
| Started | Mar 14 12:23:06 PM PDT 24 |
| Finished | Mar 14 12:23:08 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-11e7c1a0-4313-4e3b-b44b-f19d7b9982cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649665168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3649665168 |
| Directory | /workspace/16.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3630329827 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 82085813 ps |
| CPU time | 1.19 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:13 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-88632c47-ed6d-4923-8e5c-49fd3f6bd6b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630329827 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3630329827 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4101781707 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 31271185 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:23:14 PM PDT 24 |
| Finished | Mar 14 12:23:16 PM PDT 24 |
| Peak memory | 202460 kb |
| Host | smart-5624a102-715a-45a4-bcc0-c84cf9808447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101781707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4101781707 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.2872267357 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16198633 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-496062f4-20a3-41a8-96a8-f91806e4f13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872267357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2872267357 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3349113573 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 79145733 ps |
| CPU time | 1.03 seconds |
| Started | Mar 14 12:23:13 PM PDT 24 |
| Finished | Mar 14 12:23:14 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-b769f4ec-964d-42cd-9ea0-5828002299ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349113573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.3349113573 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998495326 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 49822967 ps |
| CPU time | 1.12 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202616 kb |
| Host | smart-75f6a663-3c9a-4003-9134-bfe43d01f92d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998495326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3998495326 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4276500111 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 98625548 ps |
| CPU time | 1.76 seconds |
| Started | Mar 14 12:23:39 PM PDT 24 |
| Finished | Mar 14 12:23:42 PM PDT 24 |
| Peak memory | 202768 kb |
| Host | smart-b5b53ebe-237b-432c-90e6-5f8e7f37fed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276500111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.4276500111 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2706064333 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30282558 ps |
| CPU time | 0.89 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-e3eea492-e24a-4777-81e2-ab48187c0392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706064333 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2706064333 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.184648960 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 18229453 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:11 PM PDT 24 |
| Peak memory | 201696 kb |
| Host | smart-e6676b14-2324-4e8b-b908-d04323a24604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184648960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.184648960 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.2222049190 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 19470210 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:12 PM PDT 24 |
| Finished | Mar 14 12:23:13 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-7b4b9380-498d-4804-bb30-c9450ba522c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222049190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2222049190 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.172253432 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 154460307 ps |
| CPU time | 1.05 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:12 PM PDT 24 |
| Peak memory | 202624 kb |
| Host | smart-8949812d-7939-4650-8752-09ae19f7bf25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172253432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou tstanding.172253432 |
| Directory | /workspace/18.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2370063157 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 110224763 ps |
| CPU time | 1.36 seconds |
| Started | Mar 14 12:24:21 PM PDT 24 |
| Finished | Mar 14 12:24:22 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-619d00c7-8baa-4fa9-942b-dbde26799655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370063157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2370063157 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1089072406 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 220953321 ps |
| CPU time | 1.26 seconds |
| Started | Mar 14 12:23:16 PM PDT 24 |
| Finished | Mar 14 12:23:17 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-63cad232-1275-4548-8930-835561c1d632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089072406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1089072406 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1638976800 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 33504797 ps |
| CPU time | 0.91 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-4cdff036-7844-47b9-b266-c68f333b47f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638976800 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1638976800 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.875986650 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 75688879 ps |
| CPU time | 0.83 seconds |
| Started | Mar 14 12:24:26 PM PDT 24 |
| Finished | Mar 14 12:24:27 PM PDT 24 |
| Peak memory | 201028 kb |
| Host | smart-d9f4b496-6ec6-4489-b437-caf868f1cce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875986650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.875986650 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.3444597434 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 24558726 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:24:33 PM PDT 24 |
| Finished | Mar 14 12:24:34 PM PDT 24 |
| Peak memory | 202360 kb |
| Host | smart-fbfec02b-0448-4c48-a3b0-f8aa78b8dc62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444597434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3444597434 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1863414652 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 47518623 ps |
| CPU time | 1.07 seconds |
| Started | Mar 14 12:24:17 PM PDT 24 |
| Finished | Mar 14 12:24:19 PM PDT 24 |
| Peak memory | 201568 kb |
| Host | smart-d07f5780-f9bc-4034-851c-0ae2d1427e0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863414652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1863414652 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1863706048 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 118963481 ps |
| CPU time | 1.58 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:58 PM PDT 24 |
| Peak memory | 200372 kb |
| Host | smart-f161f2ab-92d5-4d1a-9baf-67224022e906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863706048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1863706048 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.874939974 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 712626046 ps |
| CPU time | 2.01 seconds |
| Started | Mar 14 12:23:16 PM PDT 24 |
| Finished | Mar 14 12:23:18 PM PDT 24 |
| Peak memory | 202632 kb |
| Host | smart-bb9e9f02-79e3-4450-8740-dc12a790ceb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874939974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.874939974 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4016054022 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 329298815 ps |
| CPU time | 1.49 seconds |
| Started | Mar 14 12:23:42 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 202400 kb |
| Host | smart-be78266b-3d5c-4c85-9790-465422b5e21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016054022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4016054022 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.800881613 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 330219382 ps |
| CPU time | 4.38 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:48 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-b910fc0e-d49c-4b4a-8adf-7887cc23401f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800881613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.800881613 |
| Directory | /workspace/2.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1408141741 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 144327283 ps |
| CPU time | 0.77 seconds |
| Started | Mar 14 12:23:42 PM PDT 24 |
| Finished | Mar 14 12:23:43 PM PDT 24 |
| Peak memory | 202600 kb |
| Host | smart-56c7ca1d-8b89-4f86-880a-42523cf53fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408141741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1408141741 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1137038782 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 177927885 ps |
| CPU time | 1 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:08 PM PDT 24 |
| Peak memory | 201684 kb |
| Host | smart-6d8c1dce-cede-4bb3-9bc2-0d1ab471eca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137038782 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1137038782 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3529739811 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 32659052 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:44 PM PDT 24 |
| Finished | Mar 14 12:23:46 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-e13547d8-ba18-4d54-a92d-94c319e17af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529739811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3529739811 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1149528489 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 19570681 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:24:42 PM PDT 24 |
| Finished | Mar 14 12:24:43 PM PDT 24 |
| Peak memory | 201616 kb |
| Host | smart-7d15251f-2463-4608-ad19-073245bfe3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149528489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1149528489 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3759845736 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 85438660 ps |
| CPU time | 1.04 seconds |
| Started | Mar 14 12:19:58 PM PDT 24 |
| Finished | Mar 14 12:19:59 PM PDT 24 |
| Peak memory | 203044 kb |
| Host | smart-a1a74ea5-f343-4c16-8432-276836a6b8bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759845736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.3759845736 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1639430753 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 78409176 ps |
| CPU time | 1.77 seconds |
| Started | Mar 14 12:24:59 PM PDT 24 |
| Finished | Mar 14 12:25:00 PM PDT 24 |
| Peak memory | 202616 kb |
| Host | smart-81b19e12-0906-4330-a0c3-2bfdaad93ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639430753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1639430753 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2615696329 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 27816974 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:23:16 PM PDT 24 |
| Finished | Mar 14 12:23:17 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-d0718c1e-dcfa-4186-9029-cc18a81ea0ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615696329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2615696329 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.104825030 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 21462830 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:23:16 PM PDT 24 |
| Finished | Mar 14 12:23:17 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-83b3353f-fd1c-42a2-a908-12d73e93212d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104825030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.104825030 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.3135557989 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 20355774 ps |
| CPU time | 0.71 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:11 PM PDT 24 |
| Peak memory | 202436 kb |
| Host | smart-4641f461-775c-4a8c-ba8f-4663cfe7be0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135557989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3135557989 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.3955453683 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 44035396 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:24:26 PM PDT 24 |
| Finished | Mar 14 12:24:27 PM PDT 24 |
| Peak memory | 201096 kb |
| Host | smart-b37fa92c-05b3-416f-92f6-954b157777ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955453683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3955453683 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.1798430280 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 17154716 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:24:21 PM PDT 24 |
| Finished | Mar 14 12:24:22 PM PDT 24 |
| Peak memory | 202360 kb |
| Host | smart-ac41f6af-9be1-4925-8ec9-8a2bac30519d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798430280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1798430280 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.73702922 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 25042638 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:23:08 PM PDT 24 |
| Finished | Mar 14 12:23:09 PM PDT 24 |
| Peak memory | 202876 kb |
| Host | smart-88b0df81-1244-4e90-9570-8cedf666c98a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73702922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.73702922 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.90288723 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 47750670 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:14 PM PDT 24 |
| Finished | Mar 14 12:23:16 PM PDT 24 |
| Peak memory | 202440 kb |
| Host | smart-ac1e3c6b-5667-4f52-863e-41ecffdac294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90288723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.90288723 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.2602166581 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 49274093 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:23:08 PM PDT 24 |
| Finished | Mar 14 12:23:09 PM PDT 24 |
| Peak memory | 202900 kb |
| Host | smart-11c0e2db-edd6-46e0-856a-115d027d4099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602166581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2602166581 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1503349309 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 16506692 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:08 PM PDT 24 |
| Finished | Mar 14 12:23:09 PM PDT 24 |
| Peak memory | 202888 kb |
| Host | smart-199f6730-688e-4f1a-8379-8eaa26d8ceeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503349309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1503349309 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1520509103 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 168763755 ps |
| CPU time | 1.02 seconds |
| Started | Mar 14 12:22:02 PM PDT 24 |
| Finished | Mar 14 12:22:03 PM PDT 24 |
| Peak memory | 202440 kb |
| Host | smart-77ab1ced-04f0-4e63-a4a9-a1381cfff369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520509103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1520509103 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2710727735 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 473880249 ps |
| CPU time | 4.63 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:43 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-03d9918e-26b3-46a2-b901-243e3e59b245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710727735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2710727735 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1511020531 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 44805820 ps |
| CPU time | 0.77 seconds |
| Started | Mar 14 12:22:04 PM PDT 24 |
| Finished | Mar 14 12:22:04 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-cf4861c6-b6e3-4860-ad34-fe086415834e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511020531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1511020531 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3208788391 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 22025999 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 202568 kb |
| Host | smart-5e5c9ff1-eadc-4823-ba61-915c9b7ad79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208788391 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3208788391 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1700973270 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 78605758 ps |
| CPU time | 0.8 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-d5e28e8f-5744-4836-a734-2198f0394090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700973270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1700973270 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.1066185039 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 32750504 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:42 PM PDT 24 |
| Peak memory | 201084 kb |
| Host | smart-ec1fbe49-660d-48f6-a222-92c60e08e512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066185039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1066185039 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.931876353 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 57330198 ps |
| CPU time | 0.79 seconds |
| Started | Mar 14 12:24:23 PM PDT 24 |
| Finished | Mar 14 12:24:24 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-0aa22273-528e-4c97-864f-9639beef0efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931876353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out standing.931876353 |
| Directory | /workspace/3.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1770504477 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 183901552 ps |
| CPU time | 1.13 seconds |
| Started | Mar 14 12:23:33 PM PDT 24 |
| Finished | Mar 14 12:23:35 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-5d45624e-4bcb-4bcf-97c9-e21b565b207d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770504477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1770504477 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4143160691 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 483937262 ps |
| CPU time | 1.95 seconds |
| Started | Mar 14 12:24:07 PM PDT 24 |
| Finished | Mar 14 12:24:10 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-146f2a8d-67fe-474f-9e74-4654921404b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143160691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4143160691 |
| Directory | /workspace/3.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.483961600 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 46638741 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:23:10 PM PDT 24 |
| Finished | Mar 14 12:23:11 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-b76c3b30-7dc5-44d5-9bd9-4c200ec4c701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483961600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.483961600 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.548709995 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 21454878 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202372 kb |
| Host | smart-abb36e0c-79dd-4df8-be98-a198792f2b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548709995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.548709995 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.3012497091 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 29088735 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:39 PM PDT 24 |
| Finished | Mar 14 12:23:41 PM PDT 24 |
| Peak memory | 202564 kb |
| Host | smart-b6184ec5-1cd7-4d0f-950b-6b0109ab729a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012497091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3012497091 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.2847496129 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 37560009 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:34 PM PDT 24 |
| Finished | Mar 14 12:24:35 PM PDT 24 |
| Peak memory | 202376 kb |
| Host | smart-ca297f40-4403-4216-9518-a9e27e01a0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847496129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2847496129 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.417039333 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 25323855 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:24:26 PM PDT 24 |
| Finished | Mar 14 12:24:27 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-46ee9d4f-f7a6-450b-b524-f733f4f9a5f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417039333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.417039333 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.617951045 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 18667164 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:26 PM PDT 24 |
| Finished | Mar 14 12:24:27 PM PDT 24 |
| Peak memory | 201712 kb |
| Host | smart-989d3b39-dd84-4ace-a755-9ffa889f7471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617951045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.617951045 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.2986997780 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 57418363 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:28 PM PDT 24 |
| Finished | Mar 14 12:24:29 PM PDT 24 |
| Peak memory | 202348 kb |
| Host | smart-ad3f234c-10d4-4e99-af11-cefcd4b1b067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986997780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2986997780 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2882296725 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 36423851 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:23:09 PM PDT 24 |
| Finished | Mar 14 12:23:10 PM PDT 24 |
| Peak memory | 202892 kb |
| Host | smart-e67886c9-a9f7-4bf4-a3f7-dae33517e316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882296725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2882296725 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1799928682 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 51517750 ps |
| CPU time | 1.05 seconds |
| Started | Mar 14 12:24:14 PM PDT 24 |
| Finished | Mar 14 12:24:15 PM PDT 24 |
| Peak memory | 202512 kb |
| Host | smart-34a10143-2d49-424d-9008-47bf652afe30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799928682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1799928682 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.971477681 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 249549698 ps |
| CPU time | 2.23 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:05 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-3672a64a-cedb-4337-acaf-729dc0b8a549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971477681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.971477681 |
| Directory | /workspace/4.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2644699101 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 74249778 ps |
| CPU time | 0.73 seconds |
| Started | Mar 14 12:24:01 PM PDT 24 |
| Finished | Mar 14 12:24:02 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-b69047ab-808f-41b2-9cdb-dc9c28e82728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644699101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2644699101 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3907637986 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 42895809 ps |
| CPU time | 0.74 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 202568 kb |
| Host | smart-a976604c-a8d7-48b1-a785-eae9fb59d4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907637986 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3907637986 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3439124836 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 38621642 ps |
| CPU time | 0.73 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 201376 kb |
| Host | smart-de629a52-8f2b-4fae-9bef-402645fdeebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439124836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3439124836 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.3236460975 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 47767436 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 202404 kb |
| Host | smart-0d5aac24-4d48-4402-81d4-990347d9801d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236460975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3236460975 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3503181723 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 60632227 ps |
| CPU time | 1.09 seconds |
| Started | Mar 14 12:24:08 PM PDT 24 |
| Finished | Mar 14 12:24:09 PM PDT 24 |
| Peak memory | 202480 kb |
| Host | smart-ee2b2bc1-9b6a-4e2f-899f-6c861d8f481c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503181723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.3503181723 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1799226514 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 116328237 ps |
| CPU time | 1.94 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:31 PM PDT 24 |
| Peak memory | 201148 kb |
| Host | smart-3dbfbae3-dbd2-490f-85d1-1b031c3c8038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799226514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1799226514 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3255827987 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 21198811 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-36fdc658-7482-4b2e-a42e-26106ccd62ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255827987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3255827987 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.3539240230 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28802066 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-3e89cfa5-1dcc-479c-9985-791d3d5b0512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539240230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3539240230 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.2133900442 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 21324436 ps |
| CPU time | 0.75 seconds |
| Started | Mar 14 12:23:24 PM PDT 24 |
| Finished | Mar 14 12:23:26 PM PDT 24 |
| Peak memory | 202560 kb |
| Host | smart-15373825-bd0f-4aa1-8c7c-b67bfdc04b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133900442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2133900442 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.584805420 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 16634835 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:23:26 PM PDT 24 |
| Finished | Mar 14 12:23:27 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-a00e4b5a-d6dc-43ac-aabb-a3fcde186003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584805420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.584805420 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.495359190 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 19393917 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:23:24 PM PDT 24 |
| Finished | Mar 14 12:23:25 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-28eea322-0813-4276-b2ec-e69c08df3a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495359190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.495359190 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.76025467 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 27629821 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:30 PM PDT 24 |
| Peak memory | 202520 kb |
| Host | smart-767ded42-7a11-4658-93ff-f696ae464c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76025467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.76025467 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.770954652 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 59908285 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 200404 kb |
| Host | smart-66c2cdbf-0c9e-40c1-b4a6-f27358c03b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770954652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.770954652 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.1312583479 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 44782322 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:43 PM PDT 24 |
| Finished | Mar 14 12:24:44 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-df54a0c9-5b39-443f-94c8-bb58af9c5805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312583479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1312583479 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.4081967055 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 42815263 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:24:57 PM PDT 24 |
| Finished | Mar 14 12:24:58 PM PDT 24 |
| Peak memory | 202376 kb |
| Host | smart-7f1fdcee-8e76-49b8-a514-59786069bb36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081967055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4081967055 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3207758766 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 30126095 ps |
| CPU time | 0.79 seconds |
| Started | Mar 14 12:24:01 PM PDT 24 |
| Finished | Mar 14 12:24:02 PM PDT 24 |
| Peak memory | 202600 kb |
| Host | smart-b1b89659-a046-4120-aeb4-8c721f45ab86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207758766 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3207758766 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1021106942 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 70459074 ps |
| CPU time | 0.77 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-6402c6a5-1902-4201-af0f-80ff2f5724e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021106942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1021106942 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2614787322 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 20337323 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:24:13 PM PDT 24 |
| Finished | Mar 14 12:24:14 PM PDT 24 |
| Peak memory | 201540 kb |
| Host | smart-84e4f084-6f37-40da-b080-a2588bf997cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614787322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2614787322 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1197509125 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 36198929 ps |
| CPU time | 0.89 seconds |
| Started | Mar 14 12:24:27 PM PDT 24 |
| Finished | Mar 14 12:24:28 PM PDT 24 |
| Peak memory | 202580 kb |
| Host | smart-abfe4e17-a0ca-47bb-ae54-27fa3c0732ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197509125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.1197509125 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2544848697 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 25915236 ps |
| CPU time | 1.12 seconds |
| Started | Mar 14 12:24:15 PM PDT 24 |
| Finished | Mar 14 12:24:16 PM PDT 24 |
| Peak memory | 202732 kb |
| Host | smart-ecf896bb-b034-4d1c-b1d4-586491783a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544848697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2544848697 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4179489392 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 161790663 ps |
| CPU time | 1.29 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:31 PM PDT 24 |
| Peak memory | 202408 kb |
| Host | smart-bf3f6d7d-e90e-450a-a156-df0dbbe89486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179489392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4179489392 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.883114159 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 27598773 ps |
| CPU time | 1.24 seconds |
| Started | Mar 14 12:24:08 PM PDT 24 |
| Finished | Mar 14 12:24:10 PM PDT 24 |
| Peak memory | 201500 kb |
| Host | smart-adf83e35-51fc-43f4-8978-a68396288a30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883114159 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.883114159 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2737288720 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 45843170 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-ff0dd335-3858-4691-a3ed-87d846092adb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737288720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2737288720 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.1777847805 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 17740025 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:24:07 PM PDT 24 |
| Finished | Mar 14 12:24:08 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-2b26e238-2d6b-4961-9353-a79c6c3ebf68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777847805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1777847805 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.30251493 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 92058637 ps |
| CPU time | 0.86 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:30 PM PDT 24 |
| Peak memory | 201184 kb |
| Host | smart-f99dfb8e-f782-4670-b723-42b9df69be88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outs tanding.30251493 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1678074139 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 81510077 ps |
| CPU time | 1.69 seconds |
| Started | Mar 14 12:24:15 PM PDT 24 |
| Finished | Mar 14 12:24:16 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-33f5d7e4-9d4a-400d-8f2b-d3b51ad081af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678074139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1678074139 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2900127949 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 126195503 ps |
| CPU time | 1.83 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 201696 kb |
| Host | smart-76ab5da4-a8ba-4f65-a717-47b64b941361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900127949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2900127949 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.61160520 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 69745827 ps |
| CPU time | 1.12 seconds |
| Started | Mar 14 12:22:45 PM PDT 24 |
| Finished | Mar 14 12:22:46 PM PDT 24 |
| Peak memory | 202772 kb |
| Host | smart-4384b4e3-b5d5-4be4-b8a0-7fc75d161908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61160520 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.61160520 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1987620705 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 44489747 ps |
| CPU time | 0.74 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 201040 kb |
| Host | smart-9d11a1da-3a37-4c31-bf63-01b7b1f19337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987620705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1987620705 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.1705715237 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 15355094 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:14 PM PDT 24 |
| Finished | Mar 14 12:24:14 PM PDT 24 |
| Peak memory | 202328 kb |
| Host | smart-bbbf4b86-9837-4426-933c-8d75d7e0f87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705715237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1705715237 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3194742195 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 18299266 ps |
| CPU time | 0.73 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-cf3e86df-4357-415d-aa27-7fa909de1ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194742195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.3194742195 |
| Directory | /workspace/7.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.781421337 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 200632582 ps |
| CPU time | 1.35 seconds |
| Started | Mar 14 12:24:21 PM PDT 24 |
| Finished | Mar 14 12:24:23 PM PDT 24 |
| Peak memory | 202664 kb |
| Host | smart-8139d667-a5ad-480f-a312-4337f9a82422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781421337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.781421337 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.87587376 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 50527481 ps |
| CPU time | 1.24 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:31 PM PDT 24 |
| Peak memory | 202400 kb |
| Host | smart-f3ade848-ac60-4ef8-9618-1e213973b175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87587376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.87587376 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1398485013 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 26226526 ps |
| CPU time | 0.89 seconds |
| Started | Mar 14 12:22:41 PM PDT 24 |
| Finished | Mar 14 12:22:42 PM PDT 24 |
| Peak memory | 202608 kb |
| Host | smart-012ec173-143f-4ea5-bc8b-9f95db358793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398485013 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1398485013 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1041261111 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 18968034 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:22:44 PM PDT 24 |
| Finished | Mar 14 12:22:45 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-d7b07250-5527-42b1-82d3-17af35a0a457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041261111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1041261111 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3252352794 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 44740774 ps |
| CPU time | 0.61 seconds |
| Started | Mar 14 12:23:57 PM PDT 24 |
| Finished | Mar 14 12:23:59 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-616342db-2df4-4642-8fe4-00dc7fa33862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252352794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3252352794 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2210633489 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 30052706 ps |
| CPU time | 0.85 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:07 PM PDT 24 |
| Peak memory | 202428 kb |
| Host | smart-0f6512c8-454b-4c49-94d2-d6021dedbf01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210633489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.2210633489 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1676489136 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 113089496 ps |
| CPU time | 2.41 seconds |
| Started | Mar 14 12:22:44 PM PDT 24 |
| Finished | Mar 14 12:22:47 PM PDT 24 |
| Peak memory | 202556 kb |
| Host | smart-ebfc131a-0b5f-47fd-8b7c-cd6be3d0d6e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676489136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1676489136 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.375202628 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 266424042 ps |
| CPU time | 1.92 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:08 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-0694e7fc-bd20-470b-80a9-9388b0f50319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375202628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.375202628 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3554508531 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 79778411 ps |
| CPU time | 0.85 seconds |
| Started | Mar 14 12:22:54 PM PDT 24 |
| Finished | Mar 14 12:22:55 PM PDT 24 |
| Peak memory | 202660 kb |
| Host | smart-7eb08b00-eafe-47e9-9550-0a90060aa17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554508531 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3554508531 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.935332231 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 55094001 ps |
| CPU time | 0.76 seconds |
| Started | Mar 14 12:24:19 PM PDT 24 |
| Finished | Mar 14 12:24:21 PM PDT 24 |
| Peak memory | 201732 kb |
| Host | smart-66baca1f-9cf0-4ba1-89c1-53353ed36fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935332231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.935332231 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1647849157 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 21134263 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202404 kb |
| Host | smart-aa9c3089-9ab8-4436-8ed1-17d2636760ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647849157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1647849157 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1834101035 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 58869406 ps |
| CPU time | 0.75 seconds |
| Started | Mar 14 12:24:36 PM PDT 24 |
| Finished | Mar 14 12:24:37 PM PDT 24 |
| Peak memory | 202436 kb |
| Host | smart-e8bfd4ae-4271-45c9-a670-9031a7de2cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834101035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.1834101035 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.390095294 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 142783470 ps |
| CPU time | 2.09 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:09 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-05b3d55f-4f4e-445e-a451-ad0af6ec78f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390095294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.390095294 |
| Directory | /workspace/9.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.190807278 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 95909015 ps |
| CPU time | 1.42 seconds |
| Started | Mar 14 12:22:40 PM PDT 24 |
| Finished | Mar 14 12:22:42 PM PDT 24 |
| Peak memory | 202624 kb |
| Host | smart-80d0bfcd-9580-48b5-bee9-bbc97d778783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190807278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.190807278 |
| Directory | /workspace/9.i2c_tl_intg_err/latest |
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