Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5347989	1			T1	12		T3	3		T4	1
all_values[1]	5347989	1			T1	12		T3	3		T4	1
all_values[2]	5347989	1			T1	12		T3	3		T4	1
all_values[3]	5347989	1			T1	12		T3	3		T4	1
all_values[4]	5347989	1			T1	12		T3	3		T4	1
all_values[5]	5347989	1			T1	12		T3	3		T4	1
all_values[6]	5347989	1			T1	12		T3	3		T4	1
all_values[7]	5347989	1			T1	12		T3	3		T4	1
all_values[8]	5347989	1			T1	12		T3	3		T4	1
all_values[9]	5347989	1			T1	12		T3	3		T4	1
all_values[10]	5347989	1			T1	12		T3	3		T4	1
all_values[11]	5347989	1			T1	12		T3	3		T4	1
all_values[12]	5347989	1			T1	12		T3	3		T4	1
all_values[13]	5347989	1			T1	12		T3	3		T4	1
all_values[14]	5347989	1			T1	12		T3	3		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68423954

1

T1

180

T3

38

T4

15

auto[1]

11795881

1

T3

7

T18

8

T7

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71374133

1

T1

180

T3

45

T4

15

auto[1]

8845702

1

T40

319427

T36

140199

T37

195

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1271773	1			T1	12		T4	1		T17	7
all_values[0]	auto[0]	auto[1]	45204	1			T40	28		T36	578		T37	12
all_values[0]	auto[1]	auto[0]	3588205	1			T3	3		T18	2		T7	2
all_values[0]	auto[1]	auto[1]	442807	1			T40	21266		T36	8769		T37	8
all_values[1]	auto[0]	auto[0]	4699641	1			T1	12		T3	3		T4	1
all_values[1]	auto[0]	auto[1]	646818	1			T40	21292		T36	9343		T37	18
all_values[1]	auto[1]	auto[0]	1226	1			T26	14		T27	9		T185	2
all_values[1]	auto[1]	auto[1]	304	1			T40	4		T36	4		T37	2
all_values[2]	auto[0]	auto[0]	4712703	1			T1	12		T3	3		T4	1
all_values[2]	auto[0]	auto[1]	635100	1			T40	21292		T36	9342		T122	13
all_values[2]	auto[1]	auto[1]	186	1			T40	4		T36	3		T122	2
all_values[3]	auto[0]	auto[0]	4916805	1			T1	12		T3	3		T4	1
all_values[3]	auto[0]	auto[1]	430964	1			T40	21289		T36	9340		T37	18
all_values[3]	auto[1]	auto[1]	220	1			T40	4		T36	7		T37	2
all_values[4]	auto[0]	auto[0]	4695462	1			T1	12		T3	3		T4	1
all_values[4]	auto[0]	auto[1]	652263	1			T40	21293		T36	9345		T37	16
all_values[4]	auto[1]	auto[0]	50	1			T39	50		-	-		-	-
all_values[4]	auto[1]	auto[1]	214	1			T40	3		T36	1		T37	4
all_values[5]	auto[0]	auto[0]	4695483	1			T1	12		T3	3		T4	1
all_values[5]	auto[0]	auto[1]	652280	1			T40	21292		T36	9344		T37	19
all_values[5]	auto[1]	auto[1]	226	1			T40	3		T36	3		T37	1
all_values[6]	auto[0]	auto[0]	4155967	1			T1	12		T3	3		T4	1
all_values[6]	auto[0]	auto[1]	484919	1			T40	18014		T36	9252		T37	15
all_values[6]	auto[1]	auto[0]	612671	1			T18	1		T9	1		T13	1
all_values[6]	auto[1]	auto[1]	94432	1			T40	3281		T36	95		T37	3
all_values[7]	auto[0]	auto[0]	4639582	1			T1	12		T3	3		T4	1
all_values[7]	auto[0]	auto[1]	476762	1			T40	20984		T36	8211		T123	5464
all_values[7]	auto[1]	auto[0]	220378	1			T18	1		T13	1		T14	1
all_values[7]	auto[1]	auto[1]	11267	1			T40	310		T36	1136		T123	751
all_values[8]	auto[0]	auto[0]	4201648	1			T1	12		T3	3		T4	1
all_values[8]	auto[0]	auto[1]	363748	1			T40	16934		T36	8712		T37	15
all_values[8]	auto[1]	auto[0]	721398	1			T18	1		T13	1		T14	1
all_values[8]	auto[1]	auto[1]	61195	1			T40	4362		T36	635		T37	5
all_values[9]	auto[0]	auto[0]	4100541	1			T1	12		T3	3		T4	1
all_values[9]	auto[0]	auto[1]	551721	1			T40	18019		T36	9281		T122	11
all_values[9]	auto[1]	auto[0]	600325	1			T18	1		T13	1		T14	1
all_values[9]	auto[1]	auto[1]	95402	1			T40	3277		T36	65		T122	4
all_values[10]	auto[0]	auto[0]	4695482	1			T1	12		T3	3		T4	1
all_values[10]	auto[0]	auto[1]	652321	1			T40	21292		T36	9342		T37	17
all_values[10]	auto[1]	auto[1]	186	1			T40	4		T36	5		T37	1
all_values[11]	auto[0]	auto[0]	2988	1			T1	12		T4	1		T17	7
all_values[11]	auto[0]	auto[1]	420	1			T40	4		T36	18		T37	12
all_values[11]	auto[1]	auto[0]	4698444	1			T3	3		T18	2		T7	2
all_values[11]	auto[1]	auto[1]	646137	1			T40	21292		T36	9329		T37	8
all_values[12]	auto[0]	auto[0]	4695503	1			T1	12		T3	3		T4	1
all_values[12]	auto[0]	auto[1]	652287	1			T40	21291		T36	9343		T122	13
all_values[12]	auto[1]	auto[1]	199	1			T40	1		T36	3		T122	2
all_values[13]	auto[0]	auto[0]	4695454	1			T1	12		T3	2		T4	1
all_values[13]	auto[0]	auto[1]	652309	1			T40	21292		T36	9345		T37	16
all_values[13]	auto[1]	auto[0]	9	1			T3	1		T33	1		T53	1
all_values[13]	auto[1]	auto[1]	217	1			T40	4		T36	2		T37	3
all_values[14]	auto[0]	auto[0]	4752395	1			T1	12		T3	3		T4	1
all_values[14]	auto[0]	auto[1]	595411	1			T40	21294		T36	9340		T122	11
all_values[14]	auto[1]	auto[1]	183	1			T40	2		T36	6		T122	3