Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5347989	1			T1	12		T3	3		T4	1
all_pins[1]	5347989	1			T1	12		T3	3		T4	1
all_pins[2]	5347989	1			T1	12		T3	3		T4	1
all_pins[3]	5347989	1			T1	12		T3	3		T4	1
all_pins[4]	5347989	1			T1	12		T3	3		T4	1
all_pins[5]	5347989	1			T1	12		T3	3		T4	1
all_pins[6]	5347989	1			T1	12		T3	3		T4	1
all_pins[7]	5347989	1			T1	12		T3	3		T4	1
all_pins[8]	5347989	1			T1	12		T3	3		T4	1
all_pins[9]	5347989	1			T1	12		T3	3		T4	1
all_pins[10]	5347989	1			T1	12		T3	3		T4	1
all_pins[11]	5347989	1			T1	12		T3	3		T4	1
all_pins[12]	5347989	1			T1	12		T3	3		T4	1
all_pins[13]	5347989	1			T1	12		T3	3		T4	1
all_pins[14]	5347989	1			T1	12		T3	3		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	68386249	1			T1	180		T3	38		T4	15
values[0x1]	11833586	1			T3	7		T18	8		T7	4
transitions[0x0=>0x1]	11086684	1			T3	7		T18	5		T7	4
transitions[0x1=>0x0]	11085695	1			T3	6		T18	4		T7	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1317086	1			T1	12		T4	1		T17	7
all_pins[0]	values[0x1]	4030903	1			T3	3		T18	2		T7	2
all_pins[0]	transitions[0x0=>0x1]	4029302	1			T3	3		T18	2		T7	2
all_pins[0]	transitions[0x1=>0x0]	86	1			T40	2		T122	1		T121	3
all_pins[1]	values[0x0]	5346302	1			T1	12		T3	3		T4	1
all_pins[1]	values[0x1]	1687	1			T26	21		T27	9		T185	3
all_pins[1]	transitions[0x0=>0x1]	1663	1			T26	21		T27	9		T185	3
all_pins[1]	transitions[0x1=>0x0]	65	1			T40	2		T36	1		T122	1
all_pins[2]	values[0x0]	5347900	1			T1	12		T3	3		T4	1
all_pins[2]	values[0x1]	89	1			T40	3		T36	1		T122	1
all_pins[2]	transitions[0x0=>0x1]	70	1			T40	2		T36	1		T123	1
all_pins[2]	transitions[0x1=>0x0]	86	1			T40	1		T36	2		T37	2
all_pins[3]	values[0x0]	5347884	1			T1	12		T3	3		T4	1
all_pins[3]	values[0x1]	105	1			T40	2		T36	2		T37	2
all_pins[3]	transitions[0x0=>0x1]	78	1			T40	2		T36	2		T37	2
all_pins[3]	transitions[0x1=>0x0]	146	1			T37	1		T39	60		T203	3
all_pins[4]	values[0x0]	5347816	1			T1	12		T3	3		T4	1
all_pins[4]	values[0x1]	173	1			T37	1		T39	60		T203	5
all_pins[4]	transitions[0x0=>0x1]	132	1			T39	60		T203	1		T130	1
all_pins[4]	transitions[0x1=>0x0]	69	1			T40	2		T36	1		T122	1
all_pins[5]	values[0x0]	5347879	1			T1	12		T3	3		T4	1
all_pins[5]	values[0x1]	110	1			T40	2		T36	1		T37	1
all_pins[5]	transitions[0x0=>0x1]	80	1			T40	2		T36	1		T37	1
all_pins[5]	transitions[0x1=>0x0]	708342	1			T18	1		T9	1		T13	1
all_pins[6]	values[0x0]	4639617	1			T1	12		T3	3		T4	1
all_pins[6]	values[0x1]	708372	1			T18	1		T9	1		T13	1
all_pins[6]	transitions[0x0=>0x1]	690700	1			T9	1		T15	338		T12	61
all_pins[6]	transitions[0x1=>0x0]	241318	1			T15	1784		T12	2409		T29	208
all_pins[7]	values[0x0]	5088999	1			T1	12		T3	3		T4	1
all_pins[7]	values[0x1]	258990	1			T18	1		T13	1		T14	1
all_pins[7]	transitions[0x0=>0x1]	222897	1			T15	1215		T12	2254		T29	207
all_pins[7]	transitions[0x1=>0x0]	756119	1			T15	351		T12	423		T24	398
all_pins[8]	values[0x0]	4555777	1			T1	12		T3	3		T4	1
all_pins[8]	values[0x1]	792212	1			T18	1		T13	1		T14	1
all_pins[8]	transitions[0x0=>0x1]	100978	1			T15	920		T12	582		T24	398
all_pins[8]	transitions[0x1=>0x0]	4876	1			T41	1		T15	1		T12	42
all_pins[9]	values[0x0]	4651879	1			T1	12		T3	3		T4	1
all_pins[9]	values[0x1]	696110	1			T18	1		T13	1		T14	1
all_pins[9]	transitions[0x0=>0x1]	696089	1			T18	1		T13	1		T14	1
all_pins[9]	transitions[0x1=>0x0]	68	1			T40	2		T37	1		T122	1
all_pins[10]	values[0x0]	5347900	1			T1	12		T3	3		T4	1
all_pins[10]	values[0x1]	89	1			T40	2		T37	1		T122	3
all_pins[10]	transitions[0x0=>0x1]	65	1			T40	1		T37	1		T122	1
all_pins[10]	transitions[0x1=>0x0]	5344428	1			T3	3		T18	2		T7	2
all_pins[11]	values[0x0]	3537	1			T1	12		T4	1		T17	7
all_pins[11]	values[0x1]	5344452	1			T3	3		T18	2		T7	2
all_pins[11]	transitions[0x0=>0x1]	5344420	1			T3	3		T18	2		T7	2
all_pins[11]	transitions[0x1=>0x0]	67	1			T123	1		T121	1		T203	1
all_pins[12]	values[0x0]	5347890	1			T1	12		T3	3		T4	1
all_pins[12]	values[0x1]	99	1			T36	1		T122	1		T123	1
all_pins[12]	transitions[0x0=>0x1]	78	1			T122	1		T123	1		T121	1
all_pins[12]	transitions[0x1=>0x0]	85	1			T3	1		T33	1		T53	1
all_pins[13]	values[0x0]	5347883	1			T1	12		T3	2		T4	1
all_pins[13]	values[0x1]	106	1			T3	1		T33	1		T53	1
all_pins[13]	transitions[0x0=>0x1]	85	1			T3	1		T33	1		T53	1
all_pins[13]	transitions[0x1=>0x0]	68	1			T36	3		T122	1		T121	1
all_pins[14]	values[0x0]	5347900	1			T1	12		T3	3		T4	1
all_pins[14]	values[0x1]	89	1			T40	1		T36	3		T122	1
all_pins[14]	transitions[0x0=>0x1]	47	1			T36	2		T122	1		T121	1
all_pins[14]	transitions[0x1=>0x0]	4029872	1			T3	2		T18	1		T7	1