Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	454	1			T40	7		T36	7		T37	4
all_values[1]	454	1			T40	7		T36	7		T37	4
all_values[2]	454	1			T40	7		T36	7		T37	4
all_values[3]	454	1			T40	7		T36	7		T37	4
all_values[4]	454	1			T40	7		T36	7		T37	4
all_values[5]	454	1			T40	7		T36	7		T37	4
all_values[6]	454	1			T40	7		T36	7		T37	4
all_values[7]	454	1			T40	7		T36	7		T37	4
all_values[8]	454	1			T40	7		T36	7		T37	4
all_values[9]	454	1			T40	7		T36	7		T37	4
all_values[10]	454	1			T40	7		T36	7		T37	4
all_values[11]	454	1			T40	7		T36	7		T37	4
all_values[12]	454	1			T40	7		T36	7		T37	4
all_values[13]	454	1			T40	7		T36	7		T37	4
all_values[14]	454	1			T40	7		T36	7		T37	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3552

1

T40

48

T36

67

T37

16

auto[1]

3258

1

T40

57

T36

38

T37

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T40

13

T36

6

T37

25

auto[1]

5738

1

T40

92

T36

99

T37

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3995

1

T40

57

T36

55

T37

43

auto[1]

2815

1

T40

48

T36

50

T37

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	51	1			T40	2		T122	3		T130	3
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T40	2		T37	1		T203	6
all_values[0]	auto[0]	auto[1]	auto[0]	43	1			T122	1		T203	1		T130	2
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T36	2		T37	1		T123	2
all_values[0]	auto[1]	auto[0]	auto[1]	99	1			T40	2		T36	3		T121	4
all_values[0]	auto[1]	auto[1]	auto[1]	82	1			T40	1		T36	2		T37	2
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T204	1		T136	4		T205	1
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T40	2		T36	3		T121	1
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T121	1		T203	1		T130	2
all_values[1]	auto[0]	auto[1]	auto[1]	96	1			T40	1		T36	1		T37	2
all_values[1]	auto[1]	auto[0]	auto[1]	111	1			T40	1		T36	3		T122	1
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T40	3		T37	2		T122	1
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T36	2		T37	1		T121	4
all_values[2]	auto[0]	auto[0]	auto[1]	110	1			T40	1		T36	2		T122	2
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T37	3		T121	1		T203	1
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T40	2		T203	4		T130	7
all_values[2]	auto[1]	auto[0]	auto[1]	96	1			T36	2		T122	1		T123	1
all_values[2]	auto[1]	auto[1]	auto[1]	90	1			T40	4		T36	1		T122	1
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T130	2		T204	3		T206	1
all_values[3]	auto[0]	auto[0]	auto[1]	103	1			T40	1		T36	2		T37	1
all_values[3]	auto[0]	auto[1]	auto[0]	28	1			T40	3		T123	1		T130	2
all_values[3]	auto[0]	auto[1]	auto[1]	92	1			T40	1		T37	1		T122	1
all_values[3]	auto[1]	auto[0]	auto[1]	99	1			T36	4		T121	2		T203	3
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T40	2		T36	1		T37	2
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T36	1		T203	1		T206	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T40	1		T36	5		T37	2
all_values[4]	auto[0]	auto[1]	auto[0]	42	1			T123	2		T121	1		T203	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T40	1		T122	2		T121	3
all_values[4]	auto[1]	auto[0]	auto[1]	95	1			T40	5		T122	1		T123	1
all_values[4]	auto[1]	auto[1]	auto[1]	93	1			T36	1		T37	2		T203	2
all_values[5]	auto[0]	auto[0]	auto[0]	41	1			T40	1		T204	1		T206	2
all_values[5]	auto[0]	auto[0]	auto[1]	106	1			T40	1		T36	3		T37	2
all_values[5]	auto[0]	auto[1]	auto[0]	18	1			T203	1		T204	1		T201	1
all_values[5]	auto[0]	auto[1]	auto[1]	95	1			T40	2		T36	1		T123	1
all_values[5]	auto[1]	auto[0]	auto[1]	116	1			T40	3		T36	2		T122	1
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T36	1		T37	2		T122	1
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T37	1		T203	1		T205	1
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T36	3		T123	2		T121	1
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T40	1		T37	1		T203	2
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T40	4		T36	3		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T40	1		T36	1		T122	1
all_values[6]	auto[1]	auto[1]	auto[1]	103	1			T40	1		T37	1		T122	1
all_values[7]	auto[0]	auto[0]	auto[0]	47	1			T40	2		T37	1		T122	4
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T40	1		T36	1		T123	2
all_values[7]	auto[0]	auto[1]	auto[0]	32	1			T37	3		T203	1		T130	2
all_values[7]	auto[0]	auto[1]	auto[1]	99	1			T40	3		T36	3		T121	4
all_values[7]	auto[1]	auto[0]	auto[1]	87	1			T36	3		T123	1		T121	2
all_values[7]	auto[1]	auto[1]	auto[1]	93	1			T40	1		T123	1		T203	6
all_values[8]	auto[0]	auto[0]	auto[0]	53	1			T123	2		T130	2		T207	2
all_values[8]	auto[0]	auto[0]	auto[1]	92	1			T40	2		T36	2		T122	2
all_values[8]	auto[0]	auto[1]	auto[0]	40	1			T122	1		T123	2		T203	1
all_values[8]	auto[0]	auto[1]	auto[1]	90	1			T36	3		T37	2		T121	1
all_values[8]	auto[1]	auto[0]	auto[1]	88	1			T40	2		T36	2		T122	1
all_values[8]	auto[1]	auto[1]	auto[1]	91	1			T40	3		T37	2		T121	3
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T36	1		T204	1		T137	4
all_values[9]	auto[0]	auto[0]	auto[1]	99	1			T40	1		T123	1		T121	1
all_values[9]	auto[0]	auto[1]	auto[0]	32	1			T37	4		T123	1		T203	1
all_values[9]	auto[0]	auto[1]	auto[1]	104	1			T40	3		T36	2		T122	3
all_values[9]	auto[1]	auto[0]	auto[1]	95	1			T40	2		T36	3		T122	1
all_values[9]	auto[1]	auto[1]	auto[1]	93	1			T40	1		T36	1		T123	1
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T37	1		T206	2		T205	1
all_values[10]	auto[0]	auto[0]	auto[1]	97	1			T40	1		T36	2		T123	2
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T37	1		T203	1		T130	1
all_values[10]	auto[0]	auto[1]	auto[1]	107	1			T40	2		T37	1		T122	1
all_values[10]	auto[1]	auto[0]	auto[1]	108	1			T40	2		T36	5		T203	2
all_values[10]	auto[1]	auto[1]	auto[1]	78	1			T40	2		T37	1		T122	3
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T206	1		T207	2		T137	1
all_values[11]	auto[0]	auto[0]	auto[1]	103	1			T40	1		T37	3		T122	1
all_values[11]	auto[0]	auto[1]	auto[0]	31	1			T123	1		T204	1		T206	3
all_values[11]	auto[0]	auto[1]	auto[1]	90	1			T40	1		T36	2		T122	1
all_values[11]	auto[1]	auto[0]	auto[1]	96	1			T40	3		T36	1		T121	1
all_values[11]	auto[1]	auto[1]	auto[1]	96	1			T40	2		T36	4		T37	1
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T40	1		T36	1		T37	2
all_values[12]	auto[0]	auto[0]	auto[1]	95	1			T40	2		T122	1		T123	2
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T40	3		T37	2		T123	1
all_values[12]	auto[0]	auto[1]	auto[1]	92	1			T36	3		T122	1		T203	2
all_values[12]	auto[1]	auto[0]	auto[1]	104	1			T40	1		T36	1		T122	1
all_values[12]	auto[1]	auto[1]	auto[1]	95	1			T36	2		T122	1		T121	2
all_values[13]	auto[0]	auto[0]	auto[0]	23	1			T203	1		T208	3		T209	1
all_values[13]	auto[0]	auto[0]	auto[1]	114	1			T36	3		T123	1		T121	2
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T37	1		T123	2		T121	2
all_values[13]	auto[0]	auto[1]	auto[1]	108	1			T40	4		T36	1		T37	1
all_values[13]	auto[1]	auto[0]	auto[1]	104	1			T40	1		T36	2		T37	1
all_values[13]	auto[1]	auto[1]	auto[1]	81	1			T40	2		T36	1		T37	1
all_values[14]	auto[0]	auto[0]	auto[0]	48	1			T36	1		T204	5		T207	2
all_values[14]	auto[0]	auto[0]	auto[1]	100	1			T40	2		T36	1		T122	2
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T37	4		T122	1		T204	2
all_values[14]	auto[0]	auto[1]	auto[1]	111	1			T40	2		T36	1		T123	2
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T40	1		T36	2		T123	1
all_values[14]	auto[1]	auto[1]	auto[1]	76	1			T40	2		T36	2		T122	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal