Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.64 98.70 96.00 100.00 93.04 97.21 100.00 91.49


Total test records in report: 1377
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T101 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.766471605 Mar 17 01:04:33 PM PDT 24 Mar 17 01:04:34 PM PDT 24 46046605 ps
T1279 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1365686203 Mar 17 01:04:31 PM PDT 24 Mar 17 01:04:32 PM PDT 24 17946379 ps
T158 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1886085774 Mar 17 01:04:49 PM PDT 24 Mar 17 01:04:50 PM PDT 24 37109671 ps
T1280 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3241212495 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:26 PM PDT 24 63376993 ps
T1281 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1423094704 Mar 17 01:04:59 PM PDT 24 Mar 17 01:05:01 PM PDT 24 17383802 ps
T120 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3203011889 Mar 17 01:05:01 PM PDT 24 Mar 17 01:05:03 PM PDT 24 53679190 ps
T209 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2865469796 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:33 PM PDT 24 14983174 ps
T111 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.759470146 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:31 PM PDT 24 481229555 ps
T1282 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.616186051 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:30 PM PDT 24 83170693 ps
T187 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1797926245 Mar 17 01:04:55 PM PDT 24 Mar 17 01:04:58 PM PDT 24 129292825 ps
T73 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3008100850 Mar 17 01:04:19 PM PDT 24 Mar 17 01:04:22 PM PDT 24 422703954 ps
T1283 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1747842316 Mar 17 01:04:52 PM PDT 24 Mar 17 01:04:54 PM PDT 24 150954374 ps
T1284 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.700904434 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:30 PM PDT 24 43290360 ps
T1285 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.829807047 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:28 PM PDT 24 44494695 ps
T72 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.222098891 Mar 17 01:04:42 PM PDT 24 Mar 17 01:04:44 PM PDT 24 75462133 ps
T102 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3879710427 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:26 PM PDT 24 43829183 ps
T1286 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1817775728 Mar 17 01:04:47 PM PDT 24 Mar 17 01:04:49 PM PDT 24 45242145 ps
T1287 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1308826701 Mar 17 01:04:19 PM PDT 24 Mar 17 01:04:21 PM PDT 24 19054297 ps
T103 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.207555055 Mar 17 01:05:05 PM PDT 24 Mar 17 01:05:06 PM PDT 24 52665630 ps
T1288 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2619092904 Mar 17 01:04:42 PM PDT 24 Mar 17 01:04:43 PM PDT 24 44373634 ps
T1289 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.143555066 Mar 17 01:04:42 PM PDT 24 Mar 17 01:04:43 PM PDT 24 29218345 ps
T104 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1407170807 Mar 17 01:04:57 PM PDT 24 Mar 17 01:04:58 PM PDT 24 24799955 ps
T1290 /workspace/coverage/cover_reg_top/3.i2c_intr_test.560034141 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:27 PM PDT 24 19196702 ps
T1291 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3588698114 Mar 17 01:04:55 PM PDT 24 Mar 17 01:04:55 PM PDT 24 60760517 ps
T1292 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3957562275 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:30 PM PDT 24 38104700 ps
T77 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3876742114 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:29 PM PDT 24 454889976 ps
T1293 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1230235370 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:32 PM PDT 24 472329216 ps
T1294 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1577252307 Mar 17 01:04:50 PM PDT 24 Mar 17 01:04:53 PM PDT 24 19258946 ps
T86 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2630091325 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:31 PM PDT 24 92633973 ps
T1295 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2917840806 Mar 17 01:04:32 PM PDT 24 Mar 17 01:04:33 PM PDT 24 407748030 ps
T1296 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2804368142 Mar 17 01:05:01 PM PDT 24 Mar 17 01:05:03 PM PDT 24 44583246 ps
T1297 /workspace/coverage/cover_reg_top/17.i2c_intr_test.905726114 Mar 17 01:04:54 PM PDT 24 Mar 17 01:04:55 PM PDT 24 51322230 ps
T1298 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2270010864 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:25 PM PDT 24 44293859 ps
T1299 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2035630521 Mar 17 01:05:01 PM PDT 24 Mar 17 01:05:04 PM PDT 24 43303586 ps
T1300 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2643462897 Mar 17 01:04:45 PM PDT 24 Mar 17 01:04:46 PM PDT 24 51102401 ps
T83 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2698746541 Mar 17 01:04:40 PM PDT 24 Mar 17 01:04:41 PM PDT 24 221614558 ps
T1301 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2902931005 Mar 17 01:04:38 PM PDT 24 Mar 17 01:04:38 PM PDT 24 70575034 ps
T1302 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2315232197 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:28 PM PDT 24 28222169 ps
T1303 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2391814755 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:29 PM PDT 24 485018516 ps
T1304 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.965870526 Mar 17 01:04:50 PM PDT 24 Mar 17 01:04:53 PM PDT 24 21435953 ps
T1305 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2569543619 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:28 PM PDT 24 280425581 ps
T1306 /workspace/coverage/cover_reg_top/26.i2c_intr_test.951704231 Mar 17 01:04:54 PM PDT 24 Mar 17 01:04:55 PM PDT 24 45579476 ps
T1307 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1833864896 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:28 PM PDT 24 107557494 ps
T1308 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3636211072 Mar 17 01:04:47 PM PDT 24 Mar 17 01:04:48 PM PDT 24 259414160 ps
T1309 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3175780209 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:34 PM PDT 24 1270761465 ps
T186 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.622906391 Mar 17 01:04:38 PM PDT 24 Mar 17 01:04:40 PM PDT 24 507289786 ps
T1310 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1454604172 Mar 17 01:04:48 PM PDT 24 Mar 17 01:04:49 PM PDT 24 20695518 ps
T78 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1545303012 Mar 17 01:05:05 PM PDT 24 Mar 17 01:05:07 PM PDT 24 70908274 ps
T79 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1825647444 Mar 17 01:05:00 PM PDT 24 Mar 17 01:05:02 PM PDT 24 90217397 ps
T1311 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3489591678 Mar 17 01:04:20 PM PDT 24 Mar 17 01:04:22 PM PDT 24 46740443 ps
T1312 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1043128445 Mar 17 01:04:47 PM PDT 24 Mar 17 01:04:49 PM PDT 24 60636023 ps
T1313 /workspace/coverage/cover_reg_top/46.i2c_intr_test.744519695 Mar 17 01:04:55 PM PDT 24 Mar 17 01:04:56 PM PDT 24 33462933 ps
T1314 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2034097924 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:28 PM PDT 24 55289066 ps
T188 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1926043085 Mar 17 01:04:35 PM PDT 24 Mar 17 01:04:37 PM PDT 24 405882958 ps
T1315 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2522925952 Mar 17 01:04:49 PM PDT 24 Mar 17 01:04:50 PM PDT 24 21703700 ps
T1316 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1986189676 Mar 17 01:04:49 PM PDT 24 Mar 17 01:04:50 PM PDT 24 23192180 ps
T1317 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.499643848 Mar 17 01:04:20 PM PDT 24 Mar 17 01:04:22 PM PDT 24 67916338 ps
T1318 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1908643619 Mar 17 01:04:57 PM PDT 24 Mar 17 01:04:58 PM PDT 24 47218350 ps
T1319 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2030629219 Mar 17 01:04:57 PM PDT 24 Mar 17 01:04:58 PM PDT 24 49117424 ps
T105 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1675517833 Mar 17 01:04:43 PM PDT 24 Mar 17 01:04:44 PM PDT 24 25761217 ps
T1320 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1983629739 Mar 17 01:04:33 PM PDT 24 Mar 17 01:04:34 PM PDT 24 42184191 ps
T1321 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.102676603 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:29 PM PDT 24 26314846 ps
T1322 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3282749720 Mar 17 01:04:26 PM PDT 24 Mar 17 01:04:28 PM PDT 24 189859007 ps
T1323 /workspace/coverage/cover_reg_top/11.i2c_intr_test.340991271 Mar 17 01:04:37 PM PDT 24 Mar 17 01:04:38 PM PDT 24 35500763 ps
T1324 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1303877947 Mar 17 01:04:56 PM PDT 24 Mar 17 01:04:57 PM PDT 24 30460974 ps
T1325 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.962578086 Mar 17 01:04:31 PM PDT 24 Mar 17 01:04:32 PM PDT 24 61278901 ps
T1326 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1435219719 Mar 17 01:05:02 PM PDT 24 Mar 17 01:05:03 PM PDT 24 25482322 ps
T1327 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.660944646 Mar 17 01:05:03 PM PDT 24 Mar 17 01:05:04 PM PDT 24 16294337 ps
T1328 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3245022362 Mar 17 01:04:41 PM PDT 24 Mar 17 01:04:44 PM PDT 24 28894224 ps
T1329 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3138139987 Mar 17 01:04:38 PM PDT 24 Mar 17 01:04:38 PM PDT 24 24372312 ps
T106 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1392003116 Mar 17 01:04:28 PM PDT 24 Mar 17 01:04:29 PM PDT 24 242001312 ps
T1330 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3946912134 Mar 17 01:04:49 PM PDT 24 Mar 17 01:04:50 PM PDT 24 33473678 ps
T107 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2226578521 Mar 17 01:04:32 PM PDT 24 Mar 17 01:04:33 PM PDT 24 72397226 ps
T1331 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3571074711 Mar 17 01:04:37 PM PDT 24 Mar 17 01:04:38 PM PDT 24 25783601 ps
T1332 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3996873023 Mar 17 01:04:40 PM PDT 24 Mar 17 01:04:41 PM PDT 24 17056397 ps
T1333 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1702438717 Mar 17 01:04:48 PM PDT 24 Mar 17 01:04:48 PM PDT 24 52160439 ps
T1334 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2456049319 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:28 PM PDT 24 37516534 ps
T108 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3797042410 Mar 17 01:05:06 PM PDT 24 Mar 17 01:05:07 PM PDT 24 19621078 ps
T1335 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2686270872 Mar 17 01:04:32 PM PDT 24 Mar 17 01:04:40 PM PDT 24 182231612 ps
T1336 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1793483099 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:29 PM PDT 24 54760223 ps
T1337 /workspace/coverage/cover_reg_top/31.i2c_intr_test.792403024 Mar 17 01:04:39 PM PDT 24 Mar 17 01:04:40 PM PDT 24 36756471 ps
T1338 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2810596620 Mar 17 01:04:33 PM PDT 24 Mar 17 01:04:35 PM PDT 24 95652881 ps
T1339 /workspace/coverage/cover_reg_top/49.i2c_intr_test.4023939 Mar 17 01:05:00 PM PDT 24 Mar 17 01:05:01 PM PDT 24 27434195 ps
T1340 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1962441232 Mar 17 01:04:39 PM PDT 24 Mar 17 01:04:41 PM PDT 24 74506452 ps
T1341 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.518438942 Mar 17 01:04:39 PM PDT 24 Mar 17 01:04:41 PM PDT 24 73469658 ps
T1342 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.34326923 Mar 17 01:04:25 PM PDT 24 Mar 17 01:04:27 PM PDT 24 1499810920 ps
T1343 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1549311482 Mar 17 01:05:01 PM PDT 24 Mar 17 01:05:04 PM PDT 24 480685137 ps
T1344 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1932249428 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:26 PM PDT 24 230690315 ps
T1345 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.815616549 Mar 17 01:04:33 PM PDT 24 Mar 17 01:04:34 PM PDT 24 369458255 ps
T1346 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3987471581 Mar 17 01:04:21 PM PDT 24 Mar 17 01:04:23 PM PDT 24 45590728 ps
T1347 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.415015486 Mar 17 01:04:50 PM PDT 24 Mar 17 01:04:53 PM PDT 24 31191654 ps
T1348 /workspace/coverage/cover_reg_top/10.i2c_intr_test.175732534 Mar 17 01:04:32 PM PDT 24 Mar 17 01:04:32 PM PDT 24 16268259 ps
T81 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3452198163 Mar 17 01:05:00 PM PDT 24 Mar 17 01:05:02 PM PDT 24 591008748 ps
T1349 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1532276349 Mar 17 01:05:02 PM PDT 24 Mar 17 01:05:04 PM PDT 24 51226371 ps
T1350 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3981934765 Mar 17 01:04:23 PM PDT 24 Mar 17 01:04:24 PM PDT 24 52969973 ps
T1351 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3370733636 Mar 17 01:04:59 PM PDT 24 Mar 17 01:05:00 PM PDT 24 46119081 ps
T1352 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3670996923 Mar 17 01:05:04 PM PDT 24 Mar 17 01:05:06 PM PDT 24 76960771 ps
T1353 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4288500601 Mar 17 01:05:06 PM PDT 24 Mar 17 01:05:07 PM PDT 24 20067494 ps
T1354 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1778760160 Mar 17 01:04:28 PM PDT 24 Mar 17 01:04:29 PM PDT 24 123899625 ps
T1355 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1603185653 Mar 17 01:04:42 PM PDT 24 Mar 17 01:04:43 PM PDT 24 40347652 ps
T1356 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3188816741 Mar 17 01:04:50 PM PDT 24 Mar 17 01:04:53 PM PDT 24 14951580 ps
T1357 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3456932518 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:25 PM PDT 24 34737551 ps
T1358 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1983429385 Mar 17 01:04:24 PM PDT 24 Mar 17 01:04:26 PM PDT 24 144470548 ps
T1359 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4191108700 Mar 17 01:04:49 PM PDT 24 Mar 17 01:04:50 PM PDT 24 69232175 ps
T1360 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.423122511 Mar 17 01:04:56 PM PDT 24 Mar 17 01:04:57 PM PDT 24 42605802 ps
T1361 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1083841417 Mar 17 01:04:28 PM PDT 24 Mar 17 01:04:29 PM PDT 24 117696011 ps
T1362 /workspace/coverage/cover_reg_top/39.i2c_intr_test.652627880 Mar 17 01:05:00 PM PDT 24 Mar 17 01:05:01 PM PDT 24 20155007 ps
T1363 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2298556168 Mar 17 01:04:57 PM PDT 24 Mar 17 01:04:58 PM PDT 24 29224970 ps
T80 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3902357697 Mar 17 01:04:59 PM PDT 24 Mar 17 01:05:05 PM PDT 24 46438380 ps
T178 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.436784151 Mar 17 01:04:27 PM PDT 24 Mar 17 01:04:29 PM PDT 24 42741935 ps
T109 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.349709344 Mar 17 01:05:05 PM PDT 24 Mar 17 01:05:06 PM PDT 24 25035965 ps
T1364 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2993470207 Mar 17 01:04:41 PM PDT 24 Mar 17 01:04:45 PM PDT 24 1713222432 ps
T1365 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1729427013 Mar 17 01:04:52 PM PDT 24 Mar 17 01:04:53 PM PDT 24 18076232 ps
T1366 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1532019590 Mar 17 01:04:34 PM PDT 24 Mar 17 01:04:35 PM PDT 24 16468277 ps
T1367 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2261506085 Mar 17 01:04:35 PM PDT 24 Mar 17 01:04:36 PM PDT 24 24108330 ps
T82 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2923749197 Mar 17 01:04:40 PM PDT 24 Mar 17 01:04:42 PM PDT 24 497429117 ps
T1368 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.557210233 Mar 17 01:04:55 PM PDT 24 Mar 17 01:04:56 PM PDT 24 71993004 ps
T1369 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1942896545 Mar 17 01:04:51 PM PDT 24 Mar 17 01:04:53 PM PDT 24 19114172 ps
T1370 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1222699705 Mar 17 01:04:45 PM PDT 24 Mar 17 01:04:47 PM PDT 24 28945489 ps
T1371 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3060486583 Mar 17 01:05:05 PM PDT 24 Mar 17 01:05:07 PM PDT 24 229965034 ps
T1372 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.471801 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:30 PM PDT 24 45483886 ps
T1373 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.700558973 Mar 17 01:05:02 PM PDT 24 Mar 17 01:05:03 PM PDT 24 20992408 ps
T112 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.532545302 Mar 17 01:04:30 PM PDT 24 Mar 17 01:04:31 PM PDT 24 41737726 ps
T1374 /workspace/coverage/cover_reg_top/5.i2c_intr_test.994575715 Mar 17 01:04:29 PM PDT 24 Mar 17 01:04:30 PM PDT 24 16029506 ps
T1375 /workspace/coverage/cover_reg_top/7.i2c_intr_test.629882892 Mar 17 01:04:50 PM PDT 24 Mar 17 01:04:50 PM PDT 24 16505225 ps
T1376 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2924999356 Mar 17 01:04:37 PM PDT 24 Mar 17 01:04:38 PM PDT 24 74810457 ps
T1377 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1410563623 Mar 17 01:04:48 PM PDT 24 Mar 17 01:04:49 PM PDT 24 55775427 ps

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1361582751
Short name T13
Test name
Test status
Simulation time 4553912308 ps
CPU time 117.8 seconds
Started Mar 17 02:55:42 PM PDT 24
Finished Mar 17 02:57:40 PM PDT 24
Peak memory 941232 kb
Host smart-bc9a5bb6-eb94-49b2-a31b-48b0044d61bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361582751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1361582751
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.4010325768
Short name T41
Test name
Test status
Simulation time 17407604577 ps
CPU time 931.1 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 03:10:07 PM PDT 24
Peak memory 4239040 kb
Host smart-356ffd97-0129-491f-b5ea-6af5c6a93378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010325768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.4010325768
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2327187040
Short name T43
Test name
Test status
Simulation time 3295428570 ps
CPU time 13.04 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:13 PM PDT 24
Peak memory 203000 kb
Host smart-eccf3885-03c3-4259-9449-d32ebd399693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327187040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2327187040
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2988227704
Short name T36
Test name
Test status
Simulation time 80286398358 ps
CPU time 898.84 seconds
Started Mar 17 02:54:24 PM PDT 24
Finished Mar 17 03:09:23 PM PDT 24
Peak memory 1299308 kb
Host smart-1cd37cf9-6353-454c-943b-ed653f34940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988227704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2988227704
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.502508739
Short name T8
Test name
Test status
Simulation time 38866540208 ps
CPU time 58.86 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:57:43 PM PDT 24
Peak memory 495520 kb
Host smart-52345108-0ed9-464d-96bb-3acee490bb55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502508739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_stress_all.502508739
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2343845163
Short name T62
Test name
Test status
Simulation time 302819166 ps
CPU time 1.68 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203212 kb
Host smart-5a787899-9957-4783-ab51-d26d52e01fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343845163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2343845163
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/default/13.i2c_host_override.1653354948
Short name T152
Test name
Test status
Simulation time 49953038 ps
CPU time 0.61 seconds
Started Mar 17 02:54:11 PM PDT 24
Finished Mar 17 02:54:12 PM PDT 24
Peak memory 201760 kb
Host smart-88b3fc79-45cc-4ef6-890c-72f354c5dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653354948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1653354948
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.4073845385
Short name T130
Test name
Test status
Simulation time 61084568034 ps
CPU time 1954.08 seconds
Started Mar 17 02:58:33 PM PDT 24
Finished Mar 17 03:31:07 PM PDT 24
Peak memory 1607752 kb
Host smart-abe2ca24-b5e6-4179-bf3f-55425af7afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073845385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.4073845385
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.530695503
Short name T27
Test name
Test status
Simulation time 3183729145 ps
CPU time 40.84 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:54:21 PM PDT 24
Peak memory 275520 kb
Host smart-11f9c5f8-78da-43f9-8cc7-5d25158cd20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530695503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.530695503
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2918628358
Short name T63
Test name
Test status
Simulation time 473339410 ps
CPU time 2.04 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:31 PM PDT 24
Peak memory 203256 kb
Host smart-9b540fa7-9f13-4561-b9ba-05a64b065308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918628358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2918628358
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1518413955
Short name T75
Test name
Test status
Simulation time 45064797 ps
CPU time 0.62 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 201600 kb
Host smart-4bcea858-402d-4d54-bd41-20167305c717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518413955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1518413955
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2980087035
Short name T11
Test name
Test status
Simulation time 266111069 ps
CPU time 0.99 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 202452 kb
Host smart-e1f977d7-2cb4-47e7-a9f2-724ad8c2353e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980087035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2980087035
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1105359953
Short name T100
Test name
Test status
Simulation time 124502502 ps
CPU time 0.77 seconds
Started Mar 17 01:04:19 PM PDT 24
Finished Mar 17 01:04:21 PM PDT 24
Peak memory 202848 kb
Host smart-81d4df60-742e-4496-aebe-2190cb13e864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105359953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1105359953
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.929778983
Short name T7
Test name
Test status
Simulation time 3086694696 ps
CPU time 3.22 seconds
Started Mar 17 02:53:44 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202748 kb
Host smart-02710d28-d45f-43c4-8063-715438983853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929778983 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.929778983
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4267065916
Short name T37
Test name
Test status
Simulation time 39569909666 ps
CPU time 471.74 seconds
Started Mar 17 02:58:02 PM PDT 24
Finished Mar 17 03:05:54 PM PDT 24
Peak memory 1794256 kb
Host smart-3fa113b3-9f27-413a-ade9-33eac8769e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267065916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4267065916
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.687432651
Short name T1044
Test name
Test status
Simulation time 3496393077 ps
CPU time 2.56 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:53:00 PM PDT 24
Peak memory 202820 kb
Host smart-8140e2f3-320d-49a1-866d-d2334f583f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687432651 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.687432651
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1089747290
Short name T215
Test name
Test status
Simulation time 10105729372 ps
CPU time 71.83 seconds
Started Mar 17 02:54:46 PM PDT 24
Finished Mar 17 02:55:58 PM PDT 24
Peak memory 538608 kb
Host smart-31e9dd2c-c4b0-44f9-8ea3-a54065d4d602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089747290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1089747290
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2427120451
Short name T50
Test name
Test status
Simulation time 107683743 ps
CPU time 1.48 seconds
Started Mar 17 02:56:17 PM PDT 24
Finished Mar 17 02:56:18 PM PDT 24
Peak memory 213336 kb
Host smart-28ed6523-2b8f-4ea1-b414-64423d453a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427120451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2427120451
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2186387051
Short name T67
Test name
Test status
Simulation time 328650421 ps
CPU time 0.95 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:58 PM PDT 24
Peak memory 220024 kb
Host smart-a7f3149e-991e-4cdd-bf74-91d06428ac01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186387051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2186387051
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3410629049
Short name T40
Test name
Test status
Simulation time 64177534145 ps
CPU time 1967.9 seconds
Started Mar 17 02:54:08 PM PDT 24
Finished Mar 17 03:26:57 PM PDT 24
Peak memory 2841464 kb
Host smart-4424c463-a9a7-4cd6-ad37-f659667d8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410629049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3410629049
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2035630521
Short name T1299
Test name
Test status
Simulation time 43303586 ps
CPU time 2.04 seconds
Started Mar 17 01:05:01 PM PDT 24
Finished Mar 17 01:05:04 PM PDT 24
Peak memory 203180 kb
Host smart-0c684544-0d08-4bd8-a42c-c2f07cc1012f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035630521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2035630521
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3582161813
Short name T1086
Test name
Test status
Simulation time 14760650975 ps
CPU time 259.55 seconds
Started Mar 17 02:56:22 PM PDT 24
Finished Mar 17 03:00:41 PM PDT 24
Peak memory 1490536 kb
Host smart-20ab5e81-2a79-416d-8225-750edf859cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582161813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3582161813
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_perf.722129884
Short name T39
Test name
Test status
Simulation time 10394106150 ps
CPU time 117.17 seconds
Started Mar 17 02:57:28 PM PDT 24
Finished Mar 17 02:59:25 PM PDT 24
Peak memory 259552 kb
Host smart-4ca49297-4cee-4ce2-9d0a-f11ded42b00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722129884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.722129884
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2941426280
Short name T165
Test name
Test status
Simulation time 543946898 ps
CPU time 3.88 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:01 PM PDT 24
Peak memory 202744 kb
Host smart-ab06a663-f96c-4e5f-ace7-862641343af8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941426280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2941426280
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.727487653
Short name T171
Test name
Test status
Simulation time 403289616 ps
CPU time 0.97 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:54:30 PM PDT 24
Peak memory 202336 kb
Host smart-403cd578-a9ed-4a8b-9d76-55a45eab9cd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727487653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.727487653
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.436784151
Short name T178
Test name
Test status
Simulation time 42741935 ps
CPU time 0.99 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 203132 kb
Host smart-6a928ee4-91d5-4c25-bcf4-f9d1ce896ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436784151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.436784151
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1976048279
Short name T180
Test name
Test status
Simulation time 13162940235 ps
CPU time 3.24 seconds
Started Mar 17 02:55:59 PM PDT 24
Finished Mar 17 02:56:02 PM PDT 24
Peak memory 202908 kb
Host smart-6c47f644-3574-4669-a11e-8d45323a2195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976048279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1976048279
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4215807156
Short name T164
Test name
Test status
Simulation time 10183709432 ps
CPU time 24 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:57:12 PM PDT 24
Peak memory 348288 kb
Host smart-261cf224-b1e1-46d4-90aa-33ce830a1421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215807156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4215807156
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2597857056
Short name T124
Test name
Test status
Simulation time 36238648387 ps
CPU time 84.41 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 1081612 kb
Host smart-64c7393e-b4d3-4ab5-a16f-77343027fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597857056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2597857056
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3896685589
Short name T76
Test name
Test status
Simulation time 77175153 ps
CPU time 1.35 seconds
Started Mar 17 01:04:46 PM PDT 24
Finished Mar 17 01:04:47 PM PDT 24
Peak memory 203140 kb
Host smart-0b7500ef-07a0-4158-87dc-b5f206533184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896685589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3896685589
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3902357697
Short name T80
Test name
Test status
Simulation time 46438380 ps
CPU time 1.22 seconds
Started Mar 17 01:04:59 PM PDT 24
Finished Mar 17 01:05:05 PM PDT 24
Peak memory 203140 kb
Host smart-96aeca54-f781-49b1-9b6b-3ce2430aa6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902357697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3902357697
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1553923711
Short name T208
Test name
Test status
Simulation time 27577449 ps
CPU time 0.71 seconds
Started Mar 17 01:04:19 PM PDT 24
Finished Mar 17 01:04:20 PM PDT 24
Peak memory 202920 kb
Host smart-e04db69f-cafd-4b13-92d4-871b4f6df80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553923711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1553923711
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/default/10.i2c_host_perf.336694283
Short name T25
Test name
Test status
Simulation time 11985559613 ps
CPU time 575.42 seconds
Started Mar 17 02:53:49 PM PDT 24
Finished Mar 17 03:03:26 PM PDT 24
Peak memory 210912 kb
Host smart-9b5217e5-d971-4108-94d2-cde74d4c6bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336694283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.336694283
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2519490424
Short name T948
Test name
Test status
Simulation time 10212737220 ps
CPU time 14.44 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 02:54:38 PM PDT 24
Peak memory 282040 kb
Host smart-a2e860c5-798b-4e81-8008-e6ec4ace1d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519490424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2519490424
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1048793359
Short name T211
Test name
Test status
Simulation time 10255076381 ps
CPU time 13.75 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:43 PM PDT 24
Peak memory 287684 kb
Host smart-7a8b2478-8758-4679-bdf3-f7af821c35bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048793359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1048793359
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_host_override.1690550197
Short name T177
Test name
Test status
Simulation time 26434569 ps
CPU time 0.68 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 201892 kb
Host smart-e00affd0-d073-4a72-a1ba-3897e46380af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690550197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1690550197
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.182217147
Short name T201
Test name
Test status
Simulation time 17711431025 ps
CPU time 955.28 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 03:12:25 PM PDT 24
Peak memory 251712 kb
Host smart-71e74b87-2d4f-44ec-b9c3-e058cc77ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182217147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.182217147
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1286218525
Short name T192
Test name
Test status
Simulation time 651030654 ps
CPU time 27.98 seconds
Started Mar 17 02:58:04 PM PDT 24
Finished Mar 17 02:58:32 PM PDT 24
Peak memory 210828 kb
Host smart-96439fad-3faf-4491-ad5e-312e8f8aad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286218525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1286218525
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2698746541
Short name T83
Test name
Test status
Simulation time 221614558 ps
CPU time 1.33 seconds
Started Mar 17 01:04:40 PM PDT 24
Finished Mar 17 01:04:41 PM PDT 24
Peak memory 203060 kb
Host smart-135a76e6-9f82-4476-acd7-ce29f0ebb614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698746541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2698746541
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3292195612
Short name T35
Test name
Test status
Simulation time 1877771051 ps
CPU time 93.38 seconds
Started Mar 17 02:56:32 PM PDT 24
Finished Mar 17 02:58:06 PM PDT 24
Peak memory 253576 kb
Host smart-b303c6b5-9a6d-4243-ba43-61ac5d138d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292195612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3292195612
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3981934765
Short name T1350
Test name
Test status
Simulation time 52969973 ps
CPU time 1.09 seconds
Started Mar 17 01:04:23 PM PDT 24
Finished Mar 17 01:04:24 PM PDT 24
Peak memory 203056 kb
Host smart-8412d1a9-c80b-445d-8dab-3207870988b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981934765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3981934765
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3175780209
Short name T1309
Test name
Test status
Simulation time 1270761465 ps
CPU time 4.32 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:34 PM PDT 24
Peak memory 202964 kb
Host smart-5396f37b-aac9-48cc-b336-3e3d284f1ca0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175780209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3175780209
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.499643848
Short name T1317
Test name
Test status
Simulation time 67916338 ps
CPU time 0.76 seconds
Started Mar 17 01:04:20 PM PDT 24
Finished Mar 17 01:04:22 PM PDT 24
Peak memory 202752 kb
Host smart-98eec499-03a5-4277-ac21-587ec360034f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499643848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.499643848
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1983429385
Short name T1358
Test name
Test status
Simulation time 144470548 ps
CPU time 1.3 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 203188 kb
Host smart-1f4f0fca-bbcb-42fc-8487-cf194cbc7ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983429385 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1983429385
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3057307090
Short name T114
Test name
Test status
Simulation time 177950978 ps
CPU time 0.75 seconds
Started Mar 17 01:04:25 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 202844 kb
Host smart-ee6cbc3b-26f2-43cf-a599-39e3751041ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057307090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3057307090
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3987471581
Short name T1346
Test name
Test status
Simulation time 45590728 ps
CPU time 0.66 seconds
Started Mar 17 01:04:21 PM PDT 24
Finished Mar 17 01:04:23 PM PDT 24
Peak memory 202952 kb
Host smart-87cdf5c8-6349-4953-bdba-1f3a1f15a574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987471581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3987471581
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3489591678
Short name T1311
Test name
Test status
Simulation time 46740443 ps
CPU time 1.04 seconds
Started Mar 17 01:04:20 PM PDT 24
Finished Mar 17 01:04:22 PM PDT 24
Peak memory 203136 kb
Host smart-8c23e1f1-cb40-41f9-bf12-0b0551bfd57f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489591678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3489591678
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1043128445
Short name T1312
Test name
Test status
Simulation time 60636023 ps
CPU time 1.5 seconds
Started Mar 17 01:04:47 PM PDT 24
Finished Mar 17 01:04:49 PM PDT 24
Peak memory 203104 kb
Host smart-3a7b136e-5367-451a-a8d7-37b5d758df68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043128445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1043128445
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.34326923
Short name T1342
Test name
Test status
Simulation time 1499810920 ps
CPU time 1.85 seconds
Started Mar 17 01:04:25 PM PDT 24
Finished Mar 17 01:04:27 PM PDT 24
Peak memory 203088 kb
Host smart-8b8838e3-3b70-4ab8-91c1-e7dbfeaa6d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.34326923
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1392003116
Short name T106
Test name
Test status
Simulation time 242001312 ps
CPU time 0.92 seconds
Started Mar 17 01:04:28 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 202940 kb
Host smart-c1666212-1aa2-4a2a-a8fd-41046bbefd42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392003116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1392003116
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.928861209
Short name T1271
Test name
Test status
Simulation time 646165473 ps
CPU time 2.56 seconds
Started Mar 17 01:04:32 PM PDT 24
Finished Mar 17 01:04:35 PM PDT 24
Peak memory 203144 kb
Host smart-e67b3b1d-d4e4-490a-a505-f2e61c9fb5d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928861209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.928861209
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2034097924
Short name T1314
Test name
Test status
Simulation time 55289066 ps
CPU time 0.68 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 202848 kb
Host smart-03ac4c5f-5775-4b0f-bb7a-a3254f9102fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034097924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2034097924
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2810596620
Short name T1338
Test name
Test status
Simulation time 95652881 ps
CPU time 1.28 seconds
Started Mar 17 01:04:33 PM PDT 24
Finished Mar 17 01:04:35 PM PDT 24
Peak memory 203180 kb
Host smart-87c8fc32-d182-4430-8b26-8da8c9a15a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810596620 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2810596620
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1962441232
Short name T1340
Test name
Test status
Simulation time 74506452 ps
CPU time 0.76 seconds
Started Mar 17 01:04:39 PM PDT 24
Finished Mar 17 01:04:41 PM PDT 24
Peak memory 202808 kb
Host smart-5cff959f-3c72-418e-9051-a5d4d0f9f3bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962441232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1962441232
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2270010864
Short name T1298
Test name
Test status
Simulation time 44293859 ps
CPU time 0.85 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:25 PM PDT 24
Peak memory 202968 kb
Host smart-ba13b0f5-8eab-4d3e-8522-907e0953414f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270010864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2270010864
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3008100850
Short name T73
Test name
Test status
Simulation time 422703954 ps
CPU time 2.15 seconds
Started Mar 17 01:04:19 PM PDT 24
Finished Mar 17 01:04:22 PM PDT 24
Peak memory 203188 kb
Host smart-4b029a3a-af7a-43f1-b0c8-4d000b6cb980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008100850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3008100850
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1932249428
Short name T1344
Test name
Test status
Simulation time 230690315 ps
CPU time 1.24 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 203264 kb
Host smart-5de42d66-ca37-4513-aa3b-e17349f8b005
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932249428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1932249428
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.616186051
Short name T1282
Test name
Test status
Simulation time 83170693 ps
CPU time 1.12 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:30 PM PDT 24
Peak memory 203252 kb
Host smart-780bfe27-4f68-4f94-9a70-150c6a881513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616186051 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.616186051
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3571074711
Short name T1331
Test name
Test status
Simulation time 25783601 ps
CPU time 0.73 seconds
Started Mar 17 01:04:37 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 202852 kb
Host smart-c00b2c33-473f-49d3-8842-1433ba07a387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571074711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3571074711
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.175732534
Short name T1348
Test name
Test status
Simulation time 16268259 ps
CPU time 0.66 seconds
Started Mar 17 01:04:32 PM PDT 24
Finished Mar 17 01:04:32 PM PDT 24
Peak memory 202904 kb
Host smart-a9eac447-0896-46d2-bdc4-76d1a5c38690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175732534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.175732534
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2321610653
Short name T116
Test name
Test status
Simulation time 90340390 ps
CPU time 1.09 seconds
Started Mar 17 01:04:31 PM PDT 24
Finished Mar 17 01:04:33 PM PDT 24
Peak memory 203184 kb
Host smart-bd3b3400-4f4b-4585-a64d-6e3e4db036e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321610653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2321610653
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3060486583
Short name T1371
Test name
Test status
Simulation time 229965034 ps
CPU time 1.34 seconds
Started Mar 17 01:05:05 PM PDT 24
Finished Mar 17 01:05:07 PM PDT 24
Peak memory 203164 kb
Host smart-4d613206-e6ed-418f-b087-f96e34b10723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060486583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3060486583
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.143555066
Short name T1289
Test name
Test status
Simulation time 29218345 ps
CPU time 0.87 seconds
Started Mar 17 01:04:42 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 203068 kb
Host smart-67fdb7be-f9d0-494a-b5cc-5365bbb58a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143555066 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.143555066
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1083841417
Short name T1361
Test name
Test status
Simulation time 117696011 ps
CPU time 0.75 seconds
Started Mar 17 01:04:28 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 202844 kb
Host smart-e6e2ea97-064f-45eb-8599-1ea25b7435f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083841417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1083841417
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.340991271
Short name T1323
Test name
Test status
Simulation time 35500763 ps
CPU time 0.68 seconds
Started Mar 17 01:04:37 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 202828 kb
Host smart-c814cf58-38f1-4600-8f21-ca04f71d325d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340991271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.340991271
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.4238006404
Short name T119
Test name
Test status
Simulation time 34218331 ps
CPU time 0.81 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:25 PM PDT 24
Peak memory 202968 kb
Host smart-818bc881-7e2e-491b-a547-f2f8727cdb15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238006404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.4238006404
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2569543619
Short name T1305
Test name
Test status
Simulation time 280425581 ps
CPU time 1.59 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203128 kb
Host smart-4516a918-2d09-40b5-8aad-5a71d9b9b27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569543619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2569543619
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.793606194
Short name T61
Test name
Test status
Simulation time 255706438 ps
CPU time 1.31 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 203076 kb
Host smart-09bf16b3-87d9-47fb-bb2d-e6d7f39643a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793606194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.793606194
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1379739131
Short name T85
Test name
Test status
Simulation time 87538458 ps
CPU time 0.88 seconds
Started Mar 17 01:04:47 PM PDT 24
Finished Mar 17 01:04:48 PM PDT 24
Peak memory 203036 kb
Host smart-881a56d2-96d5-4daa-9bc4-700d51b8a6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379739131 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1379739131
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2261506085
Short name T1367
Test name
Test status
Simulation time 24108330 ps
CPU time 0.71 seconds
Started Mar 17 01:04:35 PM PDT 24
Finished Mar 17 01:04:36 PM PDT 24
Peak memory 202776 kb
Host smart-35712a9f-7bc9-435b-8447-6416593d2e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261506085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2261506085
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2865469796
Short name T209
Test name
Test status
Simulation time 14983174 ps
CPU time 0.67 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:33 PM PDT 24
Peak memory 202876 kb
Host smart-ecb52f53-72b6-499b-8164-bf8e6854bf55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865469796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2865469796
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1532276349
Short name T1349
Test name
Test status
Simulation time 51226371 ps
CPU time 1.02 seconds
Started Mar 17 01:05:02 PM PDT 24
Finished Mar 17 01:05:04 PM PDT 24
Peak memory 203084 kb
Host smart-90f75385-c2f4-4fb7-ba0f-e60e0bf1a55a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532276349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1532276349
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2993470207
Short name T1364
Test name
Test status
Simulation time 1713222432 ps
CPU time 2.24 seconds
Started Mar 17 01:04:41 PM PDT 24
Finished Mar 17 01:04:45 PM PDT 24
Peak memory 203192 kb
Host smart-52d6d499-4c0a-42e7-8052-3a8b42d240ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993470207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2993470207
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1825647444
Short name T79
Test name
Test status
Simulation time 90217397 ps
CPU time 1.91 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:02 PM PDT 24
Peak memory 203116 kb
Host smart-fb68eacc-fb19-438c-9b8f-f34a1ea1a7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825647444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1825647444
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1886085774
Short name T158
Test name
Test status
Simulation time 37109671 ps
CPU time 0.76 seconds
Started Mar 17 01:04:49 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 203072 kb
Host smart-d8f913eb-eb6d-49bc-a358-2e0a94a481cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886085774 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1886085774
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3138139987
Short name T1329
Test name
Test status
Simulation time 24372312 ps
CPU time 0.64 seconds
Started Mar 17 01:04:38 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 202772 kb
Host smart-dc08a17c-46ce-4835-aebe-4a54592d727b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138139987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3138139987
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1435219719
Short name T1326
Test name
Test status
Simulation time 25482322 ps
CPU time 0.67 seconds
Started Mar 17 01:05:02 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 202720 kb
Host smart-2923cfcd-416b-4d14-938f-34adbed62b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435219719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1435219719
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.815616549
Short name T1345
Test name
Test status
Simulation time 369458255 ps
CPU time 0.79 seconds
Started Mar 17 01:04:33 PM PDT 24
Finished Mar 17 01:04:34 PM PDT 24
Peak memory 203004 kb
Host smart-4e8a0504-7868-4d8e-839e-3b8055c55441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815616549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.815616549
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1549311482
Short name T1343
Test name
Test status
Simulation time 480685137 ps
CPU time 1.85 seconds
Started Mar 17 01:05:01 PM PDT 24
Finished Mar 17 01:05:04 PM PDT 24
Peak memory 203204 kb
Host smart-10516ce3-e5a0-4ea5-bcda-8e2b8bd10012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549311482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1549311482
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4136046497
Short name T59
Test name
Test status
Simulation time 54387566 ps
CPU time 0.83 seconds
Started Mar 17 01:04:37 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 203104 kb
Host smart-d4c282dc-ad3c-47c0-9c91-70d4309878be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136046497 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4136046497
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.660944646
Short name T1327
Test name
Test status
Simulation time 16294337 ps
CPU time 0.68 seconds
Started Mar 17 01:05:03 PM PDT 24
Finished Mar 17 01:05:04 PM PDT 24
Peak memory 202796 kb
Host smart-f509e94b-e795-4d2a-a5ec-62cc868d889e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660944646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.660944646
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3241212495
Short name T1280
Test name
Test status
Simulation time 63376993 ps
CPU time 0.65 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 202940 kb
Host smart-17951c23-998f-41fa-9a7d-7ded26ef65d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241212495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3241212495
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.415015486
Short name T1347
Test name
Test status
Simulation time 31191654 ps
CPU time 0.81 seconds
Started Mar 17 01:04:50 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 202888 kb
Host smart-63b63f84-dcc3-464f-a4c4-3a358d37039f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415015486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.415015486
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.4097882278
Short name T70
Test name
Test status
Simulation time 82293271 ps
CPU time 2.12 seconds
Started Mar 17 01:04:54 PM PDT 24
Finished Mar 17 01:04:56 PM PDT 24
Peak memory 203304 kb
Host smart-e3a76f3f-6f25-4a0f-9121-f8205fb40eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097882278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.4097882278
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2630091325
Short name T86
Test name
Test status
Simulation time 92633973 ps
CPU time 1.79 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:31 PM PDT 24
Peak memory 203160 kb
Host smart-e941ddf2-90df-4705-b5bd-cb6e22b231f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630091325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2630091325
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.700558973
Short name T1373
Test name
Test status
Simulation time 20992408 ps
CPU time 0.91 seconds
Started Mar 17 01:05:02 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 202992 kb
Host smart-7ad75a06-e4c9-4cd9-a479-1849fb121235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700558973 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.700558973
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1407170807
Short name T104
Test name
Test status
Simulation time 24799955 ps
CPU time 0.69 seconds
Started Mar 17 01:04:57 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 202908 kb
Host smart-8ef7c004-0b62-4fde-a0d6-7f2bdc4f2a44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407170807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1407170807
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1423094704
Short name T1281
Test name
Test status
Simulation time 17383802 ps
CPU time 0.69 seconds
Started Mar 17 01:04:59 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 202828 kb
Host smart-88fc2196-ebf8-4ada-a99c-7f62a2df8634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423094704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1423094704
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1410563623
Short name T1377
Test name
Test status
Simulation time 55775427 ps
CPU time 1.05 seconds
Started Mar 17 01:04:48 PM PDT 24
Finished Mar 17 01:04:49 PM PDT 24
Peak memory 203188 kb
Host smart-c23f6fe3-74ac-49ed-80b3-458f5279121c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410563623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1410563623
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2686270872
Short name T1335
Test name
Test status
Simulation time 182231612 ps
CPU time 2.31 seconds
Started Mar 17 01:04:32 PM PDT 24
Finished Mar 17 01:04:40 PM PDT 24
Peak memory 203236 kb
Host smart-014e3595-6ac6-454b-8a88-7966b53db93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686270872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2686270872
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3670996923
Short name T1352
Test name
Test status
Simulation time 76960771 ps
CPU time 1.38 seconds
Started Mar 17 01:05:04 PM PDT 24
Finished Mar 17 01:05:06 PM PDT 24
Peak memory 203160 kb
Host smart-44e54f53-d7ca-4f92-a5b9-4b76e5ce0094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670996923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3670996923
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.135414868
Short name T98
Test name
Test status
Simulation time 30336290 ps
CPU time 0.83 seconds
Started Mar 17 01:04:37 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 203008 kb
Host smart-fc8eb5cd-e0dd-4e6b-91cb-24a639550e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135414868 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.135414868
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.349709344
Short name T109
Test name
Test status
Simulation time 25035965 ps
CPU time 0.69 seconds
Started Mar 17 01:05:05 PM PDT 24
Finished Mar 17 01:05:06 PM PDT 24
Peak memory 202744 kb
Host smart-3d108c25-2dd3-41dd-986a-064fc40e8009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349709344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.349709344
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3676892748
Short name T1276
Test name
Test status
Simulation time 38239841 ps
CPU time 0.62 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 203016 kb
Host smart-51bc7e15-677a-4654-b207-f3d2d4ce2a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676892748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3676892748
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2233071961
Short name T113
Test name
Test status
Simulation time 32908081 ps
CPU time 0.81 seconds
Started Mar 17 01:04:59 PM PDT 24
Finished Mar 17 01:05:00 PM PDT 24
Peak memory 202976 kb
Host smart-954ed158-53b0-42b2-aa89-166b74801401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233071961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2233071961
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2198579307
Short name T58
Test name
Test status
Simulation time 245514000 ps
CPU time 1.6 seconds
Started Mar 17 01:04:53 PM PDT 24
Finished Mar 17 01:04:55 PM PDT 24
Peak memory 203220 kb
Host smart-013314eb-6c63-4de7-ac89-d50f62b6f161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198579307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2198579307
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.557210233
Short name T1368
Test name
Test status
Simulation time 71993004 ps
CPU time 1.35 seconds
Started Mar 17 01:04:55 PM PDT 24
Finished Mar 17 01:04:56 PM PDT 24
Peak memory 203240 kb
Host smart-31ef35a6-b2cc-4d88-9c7d-fe24d7c9e947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557210233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.557210233
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2924368071
Short name T84
Test name
Test status
Simulation time 126709620 ps
CPU time 0.93 seconds
Started Mar 17 01:04:43 PM PDT 24
Finished Mar 17 01:04:44 PM PDT 24
Peak memory 203080 kb
Host smart-1d1eace3-357a-4559-8ad6-bc17c59109a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924368071 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2924368071
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1675517833
Short name T105
Test name
Test status
Simulation time 25761217 ps
CPU time 0.74 seconds
Started Mar 17 01:04:43 PM PDT 24
Finished Mar 17 01:04:44 PM PDT 24
Peak memory 202896 kb
Host smart-6057c4ab-9214-4a85-9040-ad7c572b3896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675517833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1675517833
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.905726114
Short name T1297
Test name
Test status
Simulation time 51322230 ps
CPU time 0.65 seconds
Started Mar 17 01:04:54 PM PDT 24
Finished Mar 17 01:04:55 PM PDT 24
Peak memory 202848 kb
Host smart-3a3871de-9774-48d8-abe2-fa67b6d25ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905726114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.905726114
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3203011889
Short name T120
Test name
Test status
Simulation time 53679190 ps
CPU time 1.01 seconds
Started Mar 17 01:05:01 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 202976 kb
Host smart-cbc014bf-c897-440d-a38d-f44920c40a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203011889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3203011889
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1817775728
Short name T1286
Test name
Test status
Simulation time 45242145 ps
CPU time 2.26 seconds
Started Mar 17 01:04:47 PM PDT 24
Finished Mar 17 01:04:49 PM PDT 24
Peak memory 203188 kb
Host smart-cdcba785-0fc7-4a87-9bef-c3f2d4ecffe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817775728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1817775728
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1797926245
Short name T187
Test name
Test status
Simulation time 129292825 ps
CPU time 2.06 seconds
Started Mar 17 01:04:55 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 203080 kb
Host smart-133e0f13-d552-45c6-bfc9-30d8077861a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797926245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1797926245
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.423122511
Short name T1360
Test name
Test status
Simulation time 42605802 ps
CPU time 1.12 seconds
Started Mar 17 01:04:56 PM PDT 24
Finished Mar 17 01:04:57 PM PDT 24
Peak memory 203244 kb
Host smart-b5532df4-9565-4010-a6c5-62db74c9b232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423122511 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.423122511
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3797042410
Short name T108
Test name
Test status
Simulation time 19621078 ps
CPU time 0.67 seconds
Started Mar 17 01:05:06 PM PDT 24
Finished Mar 17 01:05:07 PM PDT 24
Peak memory 202188 kb
Host smart-218d5c81-89af-4246-878f-c82de54fea61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797042410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3797042410
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3072481375
Short name T1274
Test name
Test status
Simulation time 25194677 ps
CPU time 0.66 seconds
Started Mar 17 01:04:40 PM PDT 24
Finished Mar 17 01:04:41 PM PDT 24
Peak memory 202920 kb
Host smart-65a9de0d-9a86-4c97-a164-8e1b9218f1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072481375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3072481375
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.965870526
Short name T1304
Test name
Test status
Simulation time 21435953 ps
CPU time 0.78 seconds
Started Mar 17 01:04:50 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 202860 kb
Host smart-183eba87-74d1-47ac-a3ad-78f0895c2c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965870526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.965870526
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1747842316
Short name T1283
Test name
Test status
Simulation time 150954374 ps
CPU time 1.35 seconds
Started Mar 17 01:04:52 PM PDT 24
Finished Mar 17 01:04:54 PM PDT 24
Peak memory 203152 kb
Host smart-0221b121-d8d8-4243-a0b9-c05f2223fd29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747842316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1747842316
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.518438942
Short name T1341
Test name
Test status
Simulation time 73469658 ps
CPU time 0.72 seconds
Started Mar 17 01:04:39 PM PDT 24
Finished Mar 17 01:04:41 PM PDT 24
Peak memory 203060 kb
Host smart-b898e0ec-0c43-4472-9429-7101bcd6dcc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518438942 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.518438942
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3301942914
Short name T115
Test name
Test status
Simulation time 20079541 ps
CPU time 0.66 seconds
Started Mar 17 01:05:01 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 202460 kb
Host smart-e33a01c9-08a7-47de-92a0-4878d72bc11b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301942914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3301942914
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1532019590
Short name T1366
Test name
Test status
Simulation time 16468277 ps
CPU time 0.66 seconds
Started Mar 17 01:04:34 PM PDT 24
Finished Mar 17 01:04:35 PM PDT 24
Peak memory 202832 kb
Host smart-46b76ed5-2b41-458d-9dac-932a3dfc2e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532019590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1532019590
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3946912134
Short name T1330
Test name
Test status
Simulation time 33473678 ps
CPU time 0.8 seconds
Started Mar 17 01:04:49 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 203052 kb
Host smart-414d49f1-3d8c-41d6-8695-57c30fac58f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946912134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3946912134
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3819498628
Short name T68
Test name
Test status
Simulation time 356821300 ps
CPU time 2.06 seconds
Started Mar 17 01:04:48 PM PDT 24
Finished Mar 17 01:04:51 PM PDT 24
Peak memory 203204 kb
Host smart-c718f2f5-4cec-4dda-82ac-5e435a5b8149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819498628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3819498628
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.700904434
Short name T1284
Test name
Test status
Simulation time 43290360 ps
CPU time 1 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:30 PM PDT 24
Peak memory 203012 kb
Host smart-1f29469a-cfd3-4d67-b223-e67eca43e33d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700904434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.700904434
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.759470146
Short name T111
Test name
Test status
Simulation time 481229555 ps
CPU time 4.82 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:31 PM PDT 24
Peak memory 203100 kb
Host smart-8cb27a0e-4f55-4c10-af4e-26fd2661cd8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759470146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.759470146
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4039792995
Short name T174
Test name
Test status
Simulation time 66113777 ps
CPU time 0.68 seconds
Started Mar 17 01:04:20 PM PDT 24
Finished Mar 17 01:04:22 PM PDT 24
Peak memory 202788 kb
Host smart-f62f020f-7996-4b15-8e5a-6ed01b57a245
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039792995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4039792995
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3992725314
Short name T60
Test name
Test status
Simulation time 32775144 ps
CPU time 0.86 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203072 kb
Host smart-813a161f-cb7c-4783-b629-a4fdc851168b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992725314 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3992725314
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3879710427
Short name T102
Test name
Test status
Simulation time 43829183 ps
CPU time 0.67 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 202344 kb
Host smart-3b452c4e-fa18-48fc-a0f5-e1230351113c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879710427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3879710427
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1308826701
Short name T1287
Test name
Test status
Simulation time 19054297 ps
CPU time 0.65 seconds
Started Mar 17 01:04:19 PM PDT 24
Finished Mar 17 01:04:21 PM PDT 24
Peak memory 202948 kb
Host smart-b7a59281-f62d-4b61-959d-c2b8308c8b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308826701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1308826701
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2456049319
Short name T1334
Test name
Test status
Simulation time 37516534 ps
CPU time 0.85 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 202892 kb
Host smart-8cface35-770e-43d4-a055-ae0c3c44b3e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456049319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2456049319
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.471801
Short name T1372
Test name
Test status
Simulation time 45483886 ps
CPU time 1.23 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:30 PM PDT 24
Peak memory 203284 kb
Host smart-9b52280c-2732-4cc0-890b-cd446c02a722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.471801
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.829807047
Short name T1285
Test name
Test status
Simulation time 44494695 ps
CPU time 1.24 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203136 kb
Host smart-968e9e43-8496-4aee-8069-5d99b66f0fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829807047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.829807047
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2804368142
Short name T1296
Test name
Test status
Simulation time 44583246 ps
CPU time 0.62 seconds
Started Mar 17 01:05:01 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 202808 kb
Host smart-d6982eed-fbf3-4a75-8a12-a31dab38630f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804368142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2804368142
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2902931005
Short name T1301
Test name
Test status
Simulation time 70575034 ps
CPU time 0.66 seconds
Started Mar 17 01:04:38 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 202908 kb
Host smart-51171a6f-0a7c-445d-871b-7abe474a2e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902931005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2902931005
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1986189676
Short name T1316
Test name
Test status
Simulation time 23192180 ps
CPU time 0.74 seconds
Started Mar 17 01:04:49 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 202944 kb
Host smart-c2ac9b73-3722-4e9d-8110-b67b66820834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986189676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1986189676
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1729427013
Short name T1365
Test name
Test status
Simulation time 18076232 ps
CPU time 0.67 seconds
Started Mar 17 01:04:52 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 202820 kb
Host smart-b57c2343-5988-4e0f-80d2-db43c8668edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729427013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1729427013
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1942896545
Short name T1369
Test name
Test status
Simulation time 19114172 ps
CPU time 0.7 seconds
Started Mar 17 01:04:51 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 203020 kb
Host smart-b0b532dd-268c-42dd-be7f-ec105474c4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942896545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1942896545
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1303877947
Short name T1324
Test name
Test status
Simulation time 30460974 ps
CPU time 0.67 seconds
Started Mar 17 01:04:56 PM PDT 24
Finished Mar 17 01:04:57 PM PDT 24
Peak memory 202908 kb
Host smart-2c6a9d4c-093a-43ab-919f-6368a9dbe5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303877947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1303877947
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.951704231
Short name T1306
Test name
Test status
Simulation time 45579476 ps
CPU time 0.65 seconds
Started Mar 17 01:04:54 PM PDT 24
Finished Mar 17 01:04:55 PM PDT 24
Peak memory 202884 kb
Host smart-140d54fa-9fed-4adf-a484-5386d7b3eab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951704231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.951704231
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3188816741
Short name T1356
Test name
Test status
Simulation time 14951580 ps
CPU time 0.69 seconds
Started Mar 17 01:04:50 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 202916 kb
Host smart-69153769-baba-455d-a664-1aa3aa5319cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188816741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3188816741
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2619092904
Short name T1288
Test name
Test status
Simulation time 44373634 ps
CPU time 0.73 seconds
Started Mar 17 01:04:42 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 202908 kb
Host smart-01189501-f69a-4d20-b053-f828525d3e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619092904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2619092904
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2643462897
Short name T1300
Test name
Test status
Simulation time 51102401 ps
CPU time 0.65 seconds
Started Mar 17 01:04:45 PM PDT 24
Finished Mar 17 01:04:46 PM PDT 24
Peak memory 202860 kb
Host smart-7281a934-12c2-4fe5-a33f-09a1426dc5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643462897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2643462897
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3456932518
Short name T1357
Test name
Test status
Simulation time 34737551 ps
CPU time 1.02 seconds
Started Mar 17 01:04:24 PM PDT 24
Finished Mar 17 01:04:25 PM PDT 24
Peak memory 203104 kb
Host smart-249a679a-3e3f-4933-a04b-ebee5c92d5b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456932518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3456932518
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3260110446
Short name T110
Test name
Test status
Simulation time 372021561 ps
CPU time 4.14 seconds
Started Mar 17 01:04:18 PM PDT 24
Finished Mar 17 01:04:22 PM PDT 24
Peak memory 203000 kb
Host smart-fa2b9e39-fac1-4a57-8b36-ebf132b471d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260110446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3260110446
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.102676603
Short name T1321
Test name
Test status
Simulation time 26314846 ps
CPU time 0.74 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 202888 kb
Host smart-f1468a97-96f7-41ed-a194-5946c4185cb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102676603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.102676603
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1525862338
Short name T69
Test name
Test status
Simulation time 42603336 ps
CPU time 1 seconds
Started Mar 17 01:04:34 PM PDT 24
Finished Mar 17 01:04:35 PM PDT 24
Peak memory 203068 kb
Host smart-2295de80-bc00-4142-bf41-34e0809e92b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525862338 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1525862338
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.560034141
Short name T1290
Test name
Test status
Simulation time 19196702 ps
CPU time 0.7 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:27 PM PDT 24
Peak memory 202900 kb
Host smart-5b0aa08b-7a23-4ac4-9a60-18cb4a18b48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560034141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.560034141
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3636211072
Short name T1308
Test name
Test status
Simulation time 259414160 ps
CPU time 0.97 seconds
Started Mar 17 01:04:47 PM PDT 24
Finished Mar 17 01:04:48 PM PDT 24
Peak memory 203072 kb
Host smart-2ba7a2f9-e711-4f37-9221-7de8c22f058f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636211072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3636211072
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3282749720
Short name T1322
Test name
Test status
Simulation time 189859007 ps
CPU time 1.35 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203180 kb
Host smart-3853a2d1-f72d-48ff-92b1-fad5a6fa5d92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282749720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3282749720
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3183230583
Short name T1273
Test name
Test status
Simulation time 19406024 ps
CPU time 0.66 seconds
Started Mar 17 01:04:59 PM PDT 24
Finished Mar 17 01:04:59 PM PDT 24
Peak memory 202904 kb
Host smart-b83097f8-3e09-480a-9c3e-d74aae0a027e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183230583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3183230583
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.792403024
Short name T1337
Test name
Test status
Simulation time 36756471 ps
CPU time 0.62 seconds
Started Mar 17 01:04:39 PM PDT 24
Finished Mar 17 01:04:40 PM PDT 24
Peak memory 202900 kb
Host smart-792fdebc-75b0-4820-bcf4-c119604d0b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792403024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.792403024
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1577252307
Short name T1294
Test name
Test status
Simulation time 19258946 ps
CPU time 0.67 seconds
Started Mar 17 01:04:50 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 202884 kb
Host smart-0135a20b-a0c5-4366-ac8c-4f734c6d1d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577252307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1577252307
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1702438717
Short name T1333
Test name
Test status
Simulation time 52160439 ps
CPU time 0.65 seconds
Started Mar 17 01:04:48 PM PDT 24
Finished Mar 17 01:04:48 PM PDT 24
Peak memory 202936 kb
Host smart-352788cd-67ef-424e-9ab2-291bfd5ccac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702438717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1702438717
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3348469383
Short name T1278
Test name
Test status
Simulation time 25709871 ps
CPU time 0.65 seconds
Started Mar 17 01:04:44 PM PDT 24
Finished Mar 17 01:04:44 PM PDT 24
Peak memory 202880 kb
Host smart-b122c572-e626-4aae-9094-cef92c6444e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348469383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3348469383
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1529202524
Short name T1277
Test name
Test status
Simulation time 42780750 ps
CPU time 0.65 seconds
Started Mar 17 01:04:56 PM PDT 24
Finished Mar 17 01:04:56 PM PDT 24
Peak memory 202888 kb
Host smart-8bc10878-aa19-4213-ab7f-0ce9e44d19fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529202524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1529202524
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1454604172
Short name T1310
Test name
Test status
Simulation time 20695518 ps
CPU time 0.62 seconds
Started Mar 17 01:04:48 PM PDT 24
Finished Mar 17 01:04:49 PM PDT 24
Peak memory 202876 kb
Host smart-dcaefbdc-158c-4954-a6f6-cb6e915423ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454604172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1454604172
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3996873023
Short name T1332
Test name
Test status
Simulation time 17056397 ps
CPU time 0.68 seconds
Started Mar 17 01:04:40 PM PDT 24
Finished Mar 17 01:04:41 PM PDT 24
Peak memory 202908 kb
Host smart-de1be12c-ae01-4873-892c-af6f77cecd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996873023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3996873023
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1782841721
Short name T1275
Test name
Test status
Simulation time 28929667 ps
CPU time 0.64 seconds
Started Mar 17 01:04:46 PM PDT 24
Finished Mar 17 01:04:46 PM PDT 24
Peak memory 202828 kb
Host smart-45243ae9-b54b-4e3c-af2b-e1645812318f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782841721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1782841721
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.652627880
Short name T1362
Test name
Test status
Simulation time 20155007 ps
CPU time 0.67 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 202876 kb
Host smart-0e042399-4826-4034-8dc0-947a2f163813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652627880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.652627880
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2226578521
Short name T107
Test name
Test status
Simulation time 72397226 ps
CPU time 1.54 seconds
Started Mar 17 01:04:32 PM PDT 24
Finished Mar 17 01:04:33 PM PDT 24
Peak memory 203112 kb
Host smart-3a6f1dfc-bfed-4936-90d9-a070f1b5302e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226578521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2226578521
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1230235370
Short name T1293
Test name
Test status
Simulation time 472329216 ps
CPU time 4.71 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:32 PM PDT 24
Peak memory 203056 kb
Host smart-89c5132f-92dc-4d25-8e47-b3f34de5dc05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230235370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1230235370
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2315232197
Short name T1302
Test name
Test status
Simulation time 28222169 ps
CPU time 0.68 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 202940 kb
Host smart-d1e26b34-07da-4c87-a099-c919edccb769
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315232197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2315232197
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1793483099
Short name T1336
Test name
Test status
Simulation time 54760223 ps
CPU time 0.95 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 203024 kb
Host smart-03ab1f5d-de24-4070-8762-deb642fc476c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793483099 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1793483099
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3957562275
Short name T1292
Test name
Test status
Simulation time 38104700 ps
CPU time 0.64 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:30 PM PDT 24
Peak memory 202428 kb
Host smart-f60b41f5-5152-4e7e-b112-36a801f6bc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957562275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3957562275
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3762746189
Short name T1270
Test name
Test status
Simulation time 15635000 ps
CPU time 0.67 seconds
Started Mar 17 01:04:18 PM PDT 24
Finished Mar 17 01:04:19 PM PDT 24
Peak memory 202908 kb
Host smart-9ca6119e-5942-4633-83b9-b7a43e2fbb8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762746189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3762746189
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.101757699
Short name T117
Test name
Test status
Simulation time 99297055 ps
CPU time 0.83 seconds
Started Mar 17 01:04:18 PM PDT 24
Finished Mar 17 01:04:19 PM PDT 24
Peak memory 202900 kb
Host smart-91ca689d-7e93-4a14-a94d-ca73cc409158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101757699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.101757699
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3876742114
Short name T77
Test name
Test status
Simulation time 454889976 ps
CPU time 1.99 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 203076 kb
Host smart-e5c8dd35-d656-4c4c-8e57-cf273354e755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876742114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3876742114
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3588698114
Short name T1291
Test name
Test status
Simulation time 60760517 ps
CPU time 0.69 seconds
Started Mar 17 01:04:55 PM PDT 24
Finished Mar 17 01:04:55 PM PDT 24
Peak memory 202840 kb
Host smart-a42656f6-dff3-40d7-b337-f20141f66e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588698114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3588698114
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1908643619
Short name T1318
Test name
Test status
Simulation time 47218350 ps
CPU time 0.64 seconds
Started Mar 17 01:04:57 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 202828 kb
Host smart-08c282f0-c235-4e21-8106-f13faf1ed18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908643619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1908643619
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1603185653
Short name T1355
Test name
Test status
Simulation time 40347652 ps
CPU time 0.64 seconds
Started Mar 17 01:04:42 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 202812 kb
Host smart-1c38df89-82e5-48d1-a615-5542aadb036d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603185653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1603185653
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2522925952
Short name T1315
Test name
Test status
Simulation time 21703700 ps
CPU time 0.75 seconds
Started Mar 17 01:04:49 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 202856 kb
Host smart-8580e0b8-40d3-4d8b-8c4f-fc8eaeca4451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522925952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2522925952
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.4134157775
Short name T1268
Test name
Test status
Simulation time 37021730 ps
CPU time 0.62 seconds
Started Mar 17 01:05:07 PM PDT 24
Finished Mar 17 01:05:08 PM PDT 24
Peak memory 202840 kb
Host smart-a21d14f5-8180-458a-a573-71934ec1f52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134157775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.4134157775
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2298556168
Short name T1363
Test name
Test status
Simulation time 29224970 ps
CPU time 0.7 seconds
Started Mar 17 01:04:57 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 202928 kb
Host smart-60ff8c1e-26a1-40df-a962-05658dc9293b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298556168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2298556168
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.744519695
Short name T1313
Test name
Test status
Simulation time 33462933 ps
CPU time 0.61 seconds
Started Mar 17 01:04:55 PM PDT 24
Finished Mar 17 01:04:56 PM PDT 24
Peak memory 202832 kb
Host smart-3fa362a6-a2be-422f-9154-d397bfd01139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744519695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.744519695
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2030629219
Short name T1319
Test name
Test status
Simulation time 49117424 ps
CPU time 0.62 seconds
Started Mar 17 01:04:57 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 202828 kb
Host smart-67cbe66e-af70-45ac-a76d-db6e8af0bbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030629219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2030629219
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3246634509
Short name T1272
Test name
Test status
Simulation time 53343325 ps
CPU time 0.66 seconds
Started Mar 17 01:04:56 PM PDT 24
Finished Mar 17 01:04:57 PM PDT 24
Peak memory 202948 kb
Host smart-45ea8722-4798-44fe-9672-18f3d83fe115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246634509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3246634509
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.4023939
Short name T1339
Test name
Test status
Simulation time 27434195 ps
CPU time 0.67 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 202888 kb
Host smart-0daf9970-4665-4f6d-8ba9-6843a6ffe493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4023939
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1147585808
Short name T64
Test name
Test status
Simulation time 81693257 ps
CPU time 0.8 seconds
Started Mar 17 01:04:51 PM PDT 24
Finished Mar 17 01:04:53 PM PDT 24
Peak memory 203048 kb
Host smart-d9370bd3-18d7-4093-bc12-20326ddd6b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147585808 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1147585808
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2630988908
Short name T118
Test name
Test status
Simulation time 76393125 ps
CPU time 0.68 seconds
Started Mar 17 01:04:33 PM PDT 24
Finished Mar 17 01:04:33 PM PDT 24
Peak memory 202248 kb
Host smart-58a8cae7-8c8d-4c77-8bf8-accf5e9eb3ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630988908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2630988908
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.994575715
Short name T1374
Test name
Test status
Simulation time 16029506 ps
CPU time 0.68 seconds
Started Mar 17 01:04:29 PM PDT 24
Finished Mar 17 01:04:30 PM PDT 24
Peak memory 202908 kb
Host smart-4567eec6-bce6-441d-9b5a-3d1181b13c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994575715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.994575715
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4191108700
Short name T1359
Test name
Test status
Simulation time 69232175 ps
CPU time 0.94 seconds
Started Mar 17 01:04:49 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 203124 kb
Host smart-54d04d23-add8-4353-bc34-2df792134607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191108700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4191108700
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.962578086
Short name T1325
Test name
Test status
Simulation time 61278901 ps
CPU time 1.41 seconds
Started Mar 17 01:04:31 PM PDT 24
Finished Mar 17 01:04:32 PM PDT 24
Peak memory 203264 kb
Host smart-f5ef2c47-2e00-4aa8-bf49-1741c8b185ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962578086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.962578086
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1545303012
Short name T78
Test name
Test status
Simulation time 70908274 ps
CPU time 1.23 seconds
Started Mar 17 01:05:05 PM PDT 24
Finished Mar 17 01:05:07 PM PDT 24
Peak memory 203040 kb
Host smart-ac00f9b4-f944-4485-b91e-35b771b39eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545303012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1545303012
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1222699705
Short name T1370
Test name
Test status
Simulation time 28945489 ps
CPU time 0.84 seconds
Started Mar 17 01:04:45 PM PDT 24
Finished Mar 17 01:04:47 PM PDT 24
Peak memory 203036 kb
Host smart-f2fa671f-5fd6-4b80-8f27-f149fd96fc4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222699705 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1222699705
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.532545302
Short name T112
Test name
Test status
Simulation time 41737726 ps
CPU time 0.73 seconds
Started Mar 17 01:04:30 PM PDT 24
Finished Mar 17 01:04:31 PM PDT 24
Peak memory 202920 kb
Host smart-8ce67de8-bb21-4f5b-bbfb-c8f8eac884fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532545302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.532545302
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1365686203
Short name T1279
Test name
Test status
Simulation time 17946379 ps
CPU time 0.67 seconds
Started Mar 17 01:04:31 PM PDT 24
Finished Mar 17 01:04:32 PM PDT 24
Peak memory 202832 kb
Host smart-afce2a9b-b902-44db-b32c-b8b9d14a05c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365686203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1365686203
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2917840806
Short name T1295
Test name
Test status
Simulation time 407748030 ps
CPU time 0.78 seconds
Started Mar 17 01:04:32 PM PDT 24
Finished Mar 17 01:04:33 PM PDT 24
Peak memory 202956 kb
Host smart-37d92b39-64ea-41e5-81f9-6bbe6952ab50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917840806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2917840806
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2391814755
Short name T1303
Test name
Test status
Simulation time 485018516 ps
CPU time 2.05 seconds
Started Mar 17 01:04:27 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 203092 kb
Host smart-fa0a9c1e-3763-4c32-bd82-aee44d75fc68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391814755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2391814755
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1926043085
Short name T188
Test name
Test status
Simulation time 405882958 ps
CPU time 2.13 seconds
Started Mar 17 01:04:35 PM PDT 24
Finished Mar 17 01:04:37 PM PDT 24
Peak memory 203164 kb
Host smart-92569595-1c12-45f7-b532-26537c2f7a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926043085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1926043085
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1778760160
Short name T1354
Test name
Test status
Simulation time 123899625 ps
CPU time 0.94 seconds
Started Mar 17 01:04:28 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 203088 kb
Host smart-62dbe196-b8ba-4654-b815-8379f8f838a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778760160 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1778760160
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2924999356
Short name T1376
Test name
Test status
Simulation time 74810457 ps
CPU time 0.79 seconds
Started Mar 17 01:04:37 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 202844 kb
Host smart-b05ba117-6ac4-44b3-a7be-819037824a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924999356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2924999356
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.629882892
Short name T1375
Test name
Test status
Simulation time 16505225 ps
CPU time 0.66 seconds
Started Mar 17 01:04:50 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 202900 kb
Host smart-81e640c4-7af4-4257-89fa-20f913a68485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629882892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.629882892
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3245022362
Short name T1328
Test name
Test status
Simulation time 28894224 ps
CPU time 0.91 seconds
Started Mar 17 01:04:41 PM PDT 24
Finished Mar 17 01:04:44 PM PDT 24
Peak memory 203080 kb
Host smart-65ebe91e-1094-4a18-9012-32aeeffe77f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245022362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3245022362
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3370733636
Short name T1351
Test name
Test status
Simulation time 46119081 ps
CPU time 1.27 seconds
Started Mar 17 01:04:59 PM PDT 24
Finished Mar 17 01:05:00 PM PDT 24
Peak memory 203172 kb
Host smart-5792fa82-61f6-4dd1-be5e-e627d97fcd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370733636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3370733636
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2923749197
Short name T82
Test name
Test status
Simulation time 497429117 ps
CPU time 1.96 seconds
Started Mar 17 01:04:40 PM PDT 24
Finished Mar 17 01:04:42 PM PDT 24
Peak memory 203076 kb
Host smart-21f0094e-4695-4f07-b0f0-2a8369fb1c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923749197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2923749197
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.222098891
Short name T72
Test name
Test status
Simulation time 75462133 ps
CPU time 1.17 seconds
Started Mar 17 01:04:42 PM PDT 24
Finished Mar 17 01:04:44 PM PDT 24
Peak memory 203264 kb
Host smart-5af98462-884f-4b9e-bdd0-470b744747a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222098891 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.222098891
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.207555055
Short name T103
Test name
Test status
Simulation time 52665630 ps
CPU time 0.69 seconds
Started Mar 17 01:05:05 PM PDT 24
Finished Mar 17 01:05:06 PM PDT 24
Peak memory 202780 kb
Host smart-327c8e90-09f8-4a0b-b166-0cb6d2ba8dcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207555055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.207555055
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.4055101170
Short name T1269
Test name
Test status
Simulation time 25122575 ps
CPU time 0.67 seconds
Started Mar 17 01:04:42 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 202880 kb
Host smart-5a307f34-3c11-4a18-af0e-9577a05a08a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055101170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4055101170
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1983629739
Short name T1320
Test name
Test status
Simulation time 42184191 ps
CPU time 1.82 seconds
Started Mar 17 01:04:33 PM PDT 24
Finished Mar 17 01:04:34 PM PDT 24
Peak memory 203184 kb
Host smart-24682095-6996-45aa-80c2-e35ec294a180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983629739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1983629739
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3452198163
Short name T81
Test name
Test status
Simulation time 591008748 ps
CPU time 1.85 seconds
Started Mar 17 01:05:00 PM PDT 24
Finished Mar 17 01:05:02 PM PDT 24
Peak memory 203172 kb
Host smart-b02b3a7f-d1e2-4922-9a59-75a4d6aae7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452198163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3452198163
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1833864896
Short name T1307
Test name
Test status
Simulation time 107557494 ps
CPU time 0.92 seconds
Started Mar 17 01:04:26 PM PDT 24
Finished Mar 17 01:04:28 PM PDT 24
Peak memory 203148 kb
Host smart-4ae42f11-dc3b-4d51-8d99-cb4255e98a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833864896 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1833864896
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.766471605
Short name T101
Test name
Test status
Simulation time 46046605 ps
CPU time 0.73 seconds
Started Mar 17 01:04:33 PM PDT 24
Finished Mar 17 01:04:34 PM PDT 24
Peak memory 202908 kb
Host smart-aa8f01a8-80b1-4ac5-b020-be735be5a442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766471605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.766471605
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4288500601
Short name T1353
Test name
Test status
Simulation time 20067494 ps
CPU time 0.7 seconds
Started Mar 17 01:05:06 PM PDT 24
Finished Mar 17 01:05:07 PM PDT 24
Peak memory 202796 kb
Host smart-a6ae4e99-b2bc-496f-bdc2-3963e903eb20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288500601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4288500601
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2289826468
Short name T71
Test name
Test status
Simulation time 97437149 ps
CPU time 1.19 seconds
Started Mar 17 01:04:35 PM PDT 24
Finished Mar 17 01:04:37 PM PDT 24
Peak memory 203292 kb
Host smart-17f57837-d8fc-48e3-a6c4-faccfb27fdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289826468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2289826468
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.622906391
Short name T186
Test name
Test status
Simulation time 507289786 ps
CPU time 1.94 seconds
Started Mar 17 01:04:38 PM PDT 24
Finished Mar 17 01:04:40 PM PDT 24
Peak memory 203156 kb
Host smart-0603d032-e8f0-4402-8437-a0de4dd43479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622906391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.622906391
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.553580752
Short name T745
Test name
Test status
Simulation time 40766706 ps
CPU time 1.2 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 211092 kb
Host smart-ee5949bd-2728-4fd2-b729-e229486205a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553580752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.553580752
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.514823492
Short name T1063
Test name
Test status
Simulation time 1714125453 ps
CPU time 12.19 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:53:06 PM PDT 24
Peak memory 247792 kb
Host smart-570fda92-c98a-4c74-b4ad-6538c1467456
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514823492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.514823492
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1422761155
Short name T1058
Test name
Test status
Simulation time 32029958935 ps
CPU time 107.59 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 923604 kb
Host smart-a8468745-1386-4efe-85ca-f8f84e5d05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422761155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1422761155
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2047120719
Short name T308
Test name
Test status
Simulation time 6985516939 ps
CPU time 73.7 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 725352 kb
Host smart-8e30b305-0def-4cf5-af45-cefaf2fc8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047120719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2047120719
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3037852603
Short name T837
Test name
Test status
Simulation time 100942538 ps
CPU time 0.9 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 202468 kb
Host smart-f89e1902-b583-48ea-bf5d-3e0f8c25151f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037852603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3037852603
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2988182382
Short name T695
Test name
Test status
Simulation time 2867223992 ps
CPU time 183.48 seconds
Started Mar 17 02:52:55 PM PDT 24
Finished Mar 17 02:55:59 PM PDT 24
Peak memory 802700 kb
Host smart-807111d7-b5e7-4886-a6d3-80eff73c15af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988182382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2988182382
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3613655851
Short name T608
Test name
Test status
Simulation time 2665094928 ps
CPU time 45.48 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:53:43 PM PDT 24
Peak memory 239900 kb
Host smart-1f4d7ecd-23ad-4a04-aabc-1a25dff6aab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613655851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3613655851
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.57299931
Short name T876
Test name
Test status
Simulation time 49194876 ps
CPU time 0.6 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:58 PM PDT 24
Peak memory 201796 kb
Host smart-374c284d-e5bd-4dfb-8804-7aabf8b375ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57299931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.57299931
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1838247467
Short name T1259
Test name
Test status
Simulation time 8248472608 ps
CPU time 147.17 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 219172 kb
Host smart-6beec335-211f-4801-b715-c7c785536979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838247467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1838247467
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.108133983
Short name T496
Test name
Test status
Simulation time 12624580627 ps
CPU time 72.86 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:54:03 PM PDT 24
Peak memory 235532 kb
Host smart-d2d110ee-0d96-4f07-9687-0c62a0e9b9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108133983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.108133983
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1307480146
Short name T1016
Test name
Test status
Simulation time 69302243320 ps
CPU time 1784.62 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 03:22:41 PM PDT 24
Peak memory 1787140 kb
Host smart-7d94b7ec-7461-4a26-8bef-1d8531d56770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307480146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1307480146
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.3616120330
Short name T1005
Test name
Test status
Simulation time 905195802 ps
CPU time 42.17 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 210872 kb
Host smart-8f26632f-9026-41e2-bea5-ad270dd1b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616120330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3616120330
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.4249199343
Short name T583
Test name
Test status
Simulation time 5129391664 ps
CPU time 3.62 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:53:01 PM PDT 24
Peak memory 202868 kb
Host smart-3dfcd27a-2115-499b-bd44-87198072984e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249199343 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.4249199343
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2373781592
Short name T708
Test name
Test status
Simulation time 10120842147 ps
CPU time 75.9 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:54:09 PM PDT 24
Peak memory 611360 kb
Host smart-a67ba421-2ffd-42f9-b23e-c5dbdc9ce444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373781592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2373781592
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2162971100
Short name T467
Test name
Test status
Simulation time 1055267844 ps
CPU time 5.51 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 203140 kb
Host smart-b28c8493-d463-4c3e-903e-28aec587a930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162971100 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2162971100
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3755448494
Short name T97
Test name
Test status
Simulation time 5389227934 ps
CPU time 11.71 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 202692 kb
Host smart-80e259eb-5c2f-4617-9c8c-fd82a6df8628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755448494 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3755448494
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.3444199492
Short name T956
Test name
Test status
Simulation time 1282050976 ps
CPU time 4.26 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:04 PM PDT 24
Peak memory 202676 kb
Host smart-ccaf6896-835f-430b-9f52-0b551ec610ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444199492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.3444199492
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.427370187
Short name T388
Test name
Test status
Simulation time 61874143590 ps
CPU time 42.93 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 229432 kb
Host smart-b6cd8820-37fd-4a5c-861c-40509ade7621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427370187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.427370187
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.268230401
Short name T634
Test name
Test status
Simulation time 53872271180 ps
CPU time 207.91 seconds
Started Mar 17 02:53:02 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 2316648 kb
Host smart-a1292918-6e58-4468-b9f7-7dbe1e9e6dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268230401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.268230401
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3313054877
Short name T897
Test name
Test status
Simulation time 19011549604 ps
CPU time 144.32 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:55:20 PM PDT 24
Peak memory 1498116 kb
Host smart-cb1a6664-5f56-414e-b812-9d9f0d13c485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313054877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3313054877
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.3825687881
Short name T960
Test name
Test status
Simulation time 11907150835 ps
CPU time 6.27 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:53:02 PM PDT 24
Peak memory 205328 kb
Host smart-ae8a2d54-e8c1-45ff-8303-ca5479b4af66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825687881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.3825687881
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.78010815
Short name T828
Test name
Test status
Simulation time 26425895 ps
CPU time 0.71 seconds
Started Mar 17 02:53:11 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 201492 kb
Host smart-b2a43db8-c614-4c64-9fcf-41b5a1538e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78010815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.78010815
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.330031738
Short name T410
Test name
Test status
Simulation time 26326258 ps
CPU time 1.25 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:53:02 PM PDT 24
Peak memory 211004 kb
Host smart-18d7d0bb-648d-4d6c-a6a0-f4a5384e4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330031738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.330031738
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3878463328
Short name T18
Test name
Test status
Simulation time 774801328 ps
CPU time 7.1 seconds
Started Mar 17 02:53:02 PM PDT 24
Finished Mar 17 02:53:10 PM PDT 24
Peak memory 269032 kb
Host smart-ad601895-e19c-442a-a726-55514edaf81e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878463328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3878463328
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.256137367
Short name T1038
Test name
Test status
Simulation time 8940081497 ps
CPU time 61.07 seconds
Started Mar 17 02:52:59 PM PDT 24
Finished Mar 17 02:54:00 PM PDT 24
Peak memory 561208 kb
Host smart-b9eb22f8-5696-4312-8b3e-fcfca46d5a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256137367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.256137367
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1882566555
Short name T1113
Test name
Test status
Simulation time 10780603565 ps
CPU time 85.44 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 807616 kb
Host smart-69a8dd23-dbdd-42f7-b973-a3176610be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882566555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1882566555
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2974963948
Short name T673
Test name
Test status
Simulation time 260839166 ps
CPU time 1.04 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 202856 kb
Host smart-c43e03f6-7a6f-42de-961b-e76afd54864b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974963948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2974963948
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1686021448
Short name T945
Test name
Test status
Simulation time 587192408 ps
CPU time 9.31 seconds
Started Mar 17 02:53:02 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 230228 kb
Host smart-7689bf3f-a04b-486e-8ad4-c8f2fe3e5e0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686021448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1686021448
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1284392521
Short name T497
Test name
Test status
Simulation time 15789193853 ps
CPU time 216.99 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:56:38 PM PDT 24
Peak memory 989080 kb
Host smart-b72afa9d-1647-4a1b-8508-4ee957de40a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284392521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1284392521
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.338392758
Short name T961
Test name
Test status
Simulation time 2580418843 ps
CPU time 56.87 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:54:31 PM PDT 24
Peak memory 302368 kb
Host smart-1bc5c425-40b3-4f0f-a002-94e4674f5e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338392758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.338392758
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1245487077
Short name T248
Test name
Test status
Simulation time 58347922 ps
CPU time 0.69 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 201828 kb
Host smart-a8afb01f-aaad-4770-a4e6-9ec49428474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245487077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1245487077
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2818628821
Short name T768
Test name
Test status
Simulation time 14464367145 ps
CPU time 43.11 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 210964 kb
Host smart-3b240f64-58a6-4a1e-ba51-50718602acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818628821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2818628821
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.481508619
Short name T344
Test name
Test status
Simulation time 9783243003 ps
CPU time 156.57 seconds
Started Mar 17 02:52:59 PM PDT 24
Finished Mar 17 02:55:35 PM PDT 24
Peak memory 269028 kb
Host smart-e1e0607c-f7c3-4103-8aa8-14de1d98089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481508619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.481508619
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.873662441
Short name T864
Test name
Test status
Simulation time 18008475968 ps
CPU time 2096.98 seconds
Started Mar 17 02:53:04 PM PDT 24
Finished Mar 17 03:28:01 PM PDT 24
Peak memory 2705688 kb
Host smart-1b8b3a6e-d6f9-4ba8-83ff-52903fba2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873662441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.873662441
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2410169959
Short name T703
Test name
Test status
Simulation time 994587655 ps
CPU time 14.35 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 219024 kb
Host smart-b939bb39-56db-4160-9c70-a26494374a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410169959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2410169959
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2809567999
Short name T65
Test name
Test status
Simulation time 51430897 ps
CPU time 0.95 seconds
Started Mar 17 02:53:09 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 220096 kb
Host smart-e215ac8f-14e8-4108-91ec-f67fc75fe828
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809567999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2809567999
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1975959413
Short name T617
Test name
Test status
Simulation time 10092873195 ps
CPU time 29.31 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:29 PM PDT 24
Peak memory 381328 kb
Host smart-ae91b5b8-20ab-4716-815b-78adfff3b44c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975959413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1975959413
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1624787894
Short name T1189
Test name
Test status
Simulation time 10271265981 ps
CPU time 13.35 seconds
Started Mar 17 02:53:06 PM PDT 24
Finished Mar 17 02:53:20 PM PDT 24
Peak memory 310132 kb
Host smart-eb270b73-5f23-4390-a6f0-5d0e20caf0c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624787894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1624787894
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3808970260
Short name T42
Test name
Test status
Simulation time 15363660406 ps
CPU time 10.4 seconds
Started Mar 17 02:53:02 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 202984 kb
Host smart-e8546620-eb45-4f27-b580-cd45a14ab2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808970260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3808970260
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2903708658
Short name T400
Test name
Test status
Simulation time 1614565299 ps
CPU time 2.68 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:53:37 PM PDT 24
Peak memory 202764 kb
Host smart-bc9bb453-90b5-4974-8cfc-c602819182d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903708658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2903708658
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3601820465
Short name T1231
Test name
Test status
Simulation time 8322034141 ps
CPU time 5.17 seconds
Started Mar 17 02:53:06 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 204392 kb
Host smart-f1b2c9d8-c356-4bd9-9f93-5b31087cfca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601820465 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3601820465
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2426330082
Short name T390
Test name
Test status
Simulation time 21605124751 ps
CPU time 450.1 seconds
Started Mar 17 02:53:03 PM PDT 24
Finished Mar 17 03:00:33 PM PDT 24
Peak memory 3774576 kb
Host smart-6516715e-d94d-4afd-b07b-b4da23c05ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426330082 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2426330082
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1540290622
Short name T313
Test name
Test status
Simulation time 2388605974 ps
CPU time 3.64 seconds
Started Mar 17 02:53:03 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 202780 kb
Host smart-db277bdc-05a8-4d5b-bb51-3f6f4fb23b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540290622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1540290622
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.1212282757
Short name T651
Test name
Test status
Simulation time 27645206827 ps
CPU time 292.29 seconds
Started Mar 17 02:53:04 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 1769132 kb
Host smart-587a61b1-6d95-45b1-b037-b72b99cf5e85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212282757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.1212282757
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2813785431
Short name T1080
Test name
Test status
Simulation time 843913376 ps
CPU time 12.6 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 207844 kb
Host smart-a78abe89-5b03-47ab-a3e7-7a9d7b762bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813785431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2813785431
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.77093219
Short name T574
Test name
Test status
Simulation time 32062145722 ps
CPU time 248.56 seconds
Started Mar 17 02:53:03 PM PDT 24
Finished Mar 17 02:57:12 PM PDT 24
Peak memory 3031748 kb
Host smart-621e648a-800e-4ee8-bb24-eda51ebe33dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77093219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stress_wr.77093219
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2838177403
Short name T1173
Test name
Test status
Simulation time 7498816600 ps
CPU time 86.28 seconds
Started Mar 17 02:53:05 PM PDT 24
Finished Mar 17 02:54:31 PM PDT 24
Peak memory 561464 kb
Host smart-8345d7e1-6311-4457-8653-317c10216c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838177403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2838177403
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2425740589
Short name T860
Test name
Test status
Simulation time 2182697231 ps
CPU time 7.84 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:53:09 PM PDT 24
Peak memory 202944 kb
Host smart-bb5f4011-4b38-4088-a8d8-a5869e6e7302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425740589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2425740589
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.239721584
Short name T135
Test name
Test status
Simulation time 1067810644 ps
CPU time 5.31 seconds
Started Mar 17 02:53:05 PM PDT 24
Finished Mar 17 02:53:10 PM PDT 24
Peak memory 202728 kb
Host smart-267354e5-ee2e-4efb-a1bb-be268cf8f333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239721584 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_unexp_stop.239721584
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.851735698
Short name T440
Test name
Test status
Simulation time 26108853 ps
CPU time 0.61 seconds
Started Mar 17 02:53:53 PM PDT 24
Finished Mar 17 02:53:54 PM PDT 24
Peak memory 201540 kb
Host smart-89521226-4697-407f-b98f-52d54b102c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851735698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.851735698
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3572336828
Short name T1256
Test name
Test status
Simulation time 38656955 ps
CPU time 1.19 seconds
Started Mar 17 02:53:47 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 213172 kb
Host smart-7d4d4d5d-b17b-45ef-a760-e88c7b35e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572336828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3572336828
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3642379411
Short name T149
Test name
Test status
Simulation time 8265044886 ps
CPU time 9.5 seconds
Started Mar 17 02:53:47 PM PDT 24
Finished Mar 17 02:53:57 PM PDT 24
Peak memory 297496 kb
Host smart-4cf79334-34d9-48fc-b769-e7a0841f3d6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642379411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3642379411
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2266605949
Short name T606
Test name
Test status
Simulation time 2014320679 ps
CPU time 52.4 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:54:42 PM PDT 24
Peak memory 575408 kb
Host smart-737eb6ec-364b-4180-b320-c67fad3c4a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266605949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2266605949
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.670870846
Short name T429
Test name
Test status
Simulation time 1551468603 ps
CPU time 50.03 seconds
Started Mar 17 02:53:46 PM PDT 24
Finished Mar 17 02:54:36 PM PDT 24
Peak memory 571780 kb
Host smart-056b346a-7a9f-477b-87b1-3d4a4a8bb4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670870846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.670870846
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2499249052
Short name T1045
Test name
Test status
Simulation time 94491629 ps
CPU time 0.85 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 202468 kb
Host smart-8ed52df9-85d4-4b3a-8e81-7a99a2451922
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499249052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2499249052
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1672299523
Short name T705
Test name
Test status
Simulation time 172606609 ps
CPU time 4.08 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 233056 kb
Host smart-59375034-f3c1-48e0-b7dd-76b2b5488eae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672299523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1672299523
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_override.3574058170
Short name T342
Test name
Test status
Simulation time 34528903 ps
CPU time 0.63 seconds
Started Mar 17 02:53:49 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 201792 kb
Host smart-0322948c-04bd-414a-a8aa-2b6485a23529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574058170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3574058170
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.503582575
Short name T1226
Test name
Test status
Simulation time 2502241357 ps
CPU time 70.54 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:55:02 PM PDT 24
Peak memory 294852 kb
Host smart-5fba67ae-ddf4-4343-aa67-18be852a6d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503582575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.503582575
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.4095289503
Short name T757
Test name
Test status
Simulation time 2976117933 ps
CPU time 12.66 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:54:02 PM PDT 24
Peak memory 212596 kb
Host smart-bf45d8bd-3092-4a97-840a-83f8846b2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095289503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.4095289503
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3959954106
Short name T1046
Test name
Test status
Simulation time 3729065699 ps
CPU time 4.32 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 202768 kb
Host smart-a7260fbd-54cc-4e65-bbf4-35be69d37736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959954106 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3959954106
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.187359063
Short name T380
Test name
Test status
Simulation time 10316043956 ps
CPU time 30.41 seconds
Started Mar 17 02:53:52 PM PDT 24
Finished Mar 17 02:54:22 PM PDT 24
Peak memory 399320 kb
Host smart-aaeb70a8-5cab-4f9b-9392-07aba0b4ebf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187359063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.187359063
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3508863291
Short name T1196
Test name
Test status
Simulation time 10166174051 ps
CPU time 83.58 seconds
Started Mar 17 02:53:49 PM PDT 24
Finished Mar 17 02:55:13 PM PDT 24
Peak memory 671708 kb
Host smart-f8d49527-8a12-4b2d-b960-deb96982f0f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508863291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3508863291
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.4089877240
Short name T1029
Test name
Test status
Simulation time 648749872 ps
CPU time 2.8 seconds
Started Mar 17 02:53:55 PM PDT 24
Finished Mar 17 02:53:58 PM PDT 24
Peak memory 202788 kb
Host smart-390691e7-b802-4d40-8ebb-51bba5f0bfcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089877240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.4089877240
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.27395987
Short name T256
Test name
Test status
Simulation time 3684507805 ps
CPU time 7.41 seconds
Started Mar 17 02:53:49 PM PDT 24
Finished Mar 17 02:53:57 PM PDT 24
Peak memory 210424 kb
Host smart-1add63da-bc4f-4299-ab11-8007c80408b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27395987 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.27395987
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1439263262
Short name T887
Test name
Test status
Simulation time 12038093690 ps
CPU time 13.58 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:54:05 PM PDT 24
Peak memory 363516 kb
Host smart-72f212ba-23c6-41d5-bca7-30eef733299e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439263262 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1439263262
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2428530122
Short name T552
Test name
Test status
Simulation time 880439702 ps
CPU time 5.45 seconds
Started Mar 17 02:53:54 PM PDT 24
Finished Mar 17 02:54:00 PM PDT 24
Peak memory 212052 kb
Host smart-0aa024d6-ef54-4b89-b241-2cfdf827bb32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428530122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2428530122
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1733141279
Short name T914
Test name
Test status
Simulation time 9466401281 ps
CPU time 94.89 seconds
Started Mar 17 02:53:53 PM PDT 24
Finished Mar 17 02:55:28 PM PDT 24
Peak memory 538028 kb
Host smart-b6f2b9a1-0e4b-4466-a9d9-afc52c0dbf06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733141279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1733141279
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3783315929
Short name T647
Test name
Test status
Simulation time 2673002519 ps
CPU time 6.11 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:53:58 PM PDT 24
Peak memory 209128 kb
Host smart-f4cfe002-4532-4f90-9291-43146e222ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783315929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3783315929
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.2907262771
Short name T893
Test name
Test status
Simulation time 766168102 ps
CPU time 5.96 seconds
Started Mar 17 02:53:50 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 202756 kb
Host smart-794c0108-f642-4639-bf4e-ace96d1251f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907262771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.2907262771
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.861520593
Short name T711
Test name
Test status
Simulation time 44311001 ps
CPU time 0.59 seconds
Started Mar 17 02:54:04 PM PDT 24
Finished Mar 17 02:54:05 PM PDT 24
Peak memory 201668 kb
Host smart-11688cb4-8379-464f-bd86-52ff13538281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861520593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.861520593
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.4264368900
Short name T535
Test name
Test status
Simulation time 36907861 ps
CPU time 1.79 seconds
Started Mar 17 02:54:01 PM PDT 24
Finished Mar 17 02:54:03 PM PDT 24
Peak memory 211020 kb
Host smart-64b7b155-4652-4cdc-995b-d8bfb3efbe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264368900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.4264368900
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.90496229
Short name T625
Test name
Test status
Simulation time 639033028 ps
CPU time 15.63 seconds
Started Mar 17 02:53:54 PM PDT 24
Finished Mar 17 02:54:10 PM PDT 24
Peak memory 267392 kb
Host smart-0e62180e-98d9-49d3-a112-e749af0853f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90496229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty
.90496229
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3611451290
Short name T1258
Test name
Test status
Simulation time 2563221968 ps
CPU time 85.38 seconds
Started Mar 17 02:53:55 PM PDT 24
Finished Mar 17 02:55:20 PM PDT 24
Peak memory 693336 kb
Host smart-eba40ac0-e16a-4f37-a4c2-12d5600a8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611451290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3611451290
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.251454849
Short name T743
Test name
Test status
Simulation time 2073141905 ps
CPU time 141.79 seconds
Started Mar 17 02:53:57 PM PDT 24
Finished Mar 17 02:56:19 PM PDT 24
Peak memory 667316 kb
Host smart-b8f23fcb-b12b-4860-9cc3-0559e7db3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251454849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.251454849
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.429898004
Short name T169
Test name
Test status
Simulation time 788014762 ps
CPU time 1.05 seconds
Started Mar 17 02:53:55 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 202820 kb
Host smart-bee357da-a00d-4233-90d0-273a70647841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429898004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.429898004
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2229458639
Short name T795
Test name
Test status
Simulation time 292559144 ps
CPU time 3.71 seconds
Started Mar 17 02:53:56 PM PDT 24
Finished Mar 17 02:53:59 PM PDT 24
Peak memory 202732 kb
Host smart-33e62a8a-5bba-44b3-ba31-7e6b58dd786b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229458639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2229458639
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.707934781
Short name T125
Test name
Test status
Simulation time 10967265095 ps
CPU time 97.74 seconds
Started Mar 17 02:53:54 PM PDT 24
Finished Mar 17 02:55:32 PM PDT 24
Peak memory 1149888 kb
Host smart-05088757-1d18-4fdc-a8eb-7aa12c5226d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707934781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.707934781
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4250610343
Short name T655
Test name
Test status
Simulation time 26872181502 ps
CPU time 50.94 seconds
Started Mar 17 02:54:06 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 305368 kb
Host smart-6056da8a-915f-4d90-8120-5e97266871a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250610343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4250610343
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.613279279
Short name T519
Test name
Test status
Simulation time 28804654 ps
CPU time 0.71 seconds
Started Mar 17 02:53:55 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 201928 kb
Host smart-2c6f3da2-c6eb-41f7-8cbd-511bd595f62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613279279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.613279279
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2783071869
Short name T567
Test name
Test status
Simulation time 3274590612 ps
CPU time 14.52 seconds
Started Mar 17 02:54:01 PM PDT 24
Finished Mar 17 02:54:16 PM PDT 24
Peak memory 228444 kb
Host smart-e2b76201-37a5-466f-ae70-ec28c0c5434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783071869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2783071869
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2676850632
Short name T381
Test name
Test status
Simulation time 3048319295 ps
CPU time 84.09 seconds
Started Mar 17 02:53:56 PM PDT 24
Finished Mar 17 02:55:20 PM PDT 24
Peak memory 243456 kb
Host smart-38d7567b-edac-4aba-a77a-9eb1074a00ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676850632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2676850632
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.154037496
Short name T204
Test name
Test status
Simulation time 16467115380 ps
CPU time 1652.19 seconds
Started Mar 17 02:54:00 PM PDT 24
Finished Mar 17 03:21:32 PM PDT 24
Peak memory 1624336 kb
Host smart-685cec2a-77aa-47e9-a96c-7352f7b7605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154037496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.154037496
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3206320857
Short name T451
Test name
Test status
Simulation time 1051150502 ps
CPU time 15.76 seconds
Started Mar 17 02:54:00 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 218632 kb
Host smart-46c82257-302e-47c8-8f9b-b3738680a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206320857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3206320857
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3617691255
Short name T669
Test name
Test status
Simulation time 1046924981 ps
CPU time 3.97 seconds
Started Mar 17 02:54:04 PM PDT 24
Finished Mar 17 02:54:08 PM PDT 24
Peak memory 202628 kb
Host smart-61b8c05e-0ba5-4eb5-8d56-586a80c16b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617691255 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3617691255
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2716706034
Short name T824
Test name
Test status
Simulation time 10135752431 ps
CPU time 28.68 seconds
Started Mar 17 02:54:04 PM PDT 24
Finished Mar 17 02:54:32 PM PDT 24
Peak memory 384696 kb
Host smart-4e4e8ef6-d6cf-4b03-9c4e-934a3eac2a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716706034 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2716706034
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.727547419
Short name T238
Test name
Test status
Simulation time 10424863050 ps
CPU time 10.68 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:16 PM PDT 24
Peak memory 309352 kb
Host smart-8b71b93a-e8eb-4c75-b248-6405d6cd66a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727547419 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.727547419
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3499639583
Short name T1004
Test name
Test status
Simulation time 1327515168 ps
CPU time 3.33 seconds
Started Mar 17 02:54:07 PM PDT 24
Finished Mar 17 02:54:11 PM PDT 24
Peak memory 202840 kb
Host smart-c1dd2240-abf6-4efa-a18d-4cc62bd6e198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499639583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3499639583
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2475279711
Short name T1227
Test name
Test status
Simulation time 1333633405 ps
CPU time 6.54 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:11 PM PDT 24
Peak memory 208264 kb
Host smart-5f54b345-245d-4c45-bb50-ee9887f58963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475279711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2475279711
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_perf.1431881712
Short name T232
Test name
Test status
Simulation time 785728895 ps
CPU time 5.05 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:10 PM PDT 24
Peak memory 207772 kb
Host smart-e443b05f-98d3-4840-9529-c72aa61814cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431881712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.1431881712
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3287217381
Short name T754
Test name
Test status
Simulation time 1569161506 ps
CPU time 15.29 seconds
Started Mar 17 02:54:00 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 202712 kb
Host smart-a80cff6a-57c2-4963-83f0-8b331dc8c5dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287217381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3287217381
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3044137832
Short name T1022
Test name
Test status
Simulation time 20976734108 ps
CPU time 5.22 seconds
Started Mar 17 02:53:59 PM PDT 24
Finished Mar 17 02:54:05 PM PDT 24
Peak memory 202660 kb
Host smart-9c294420-0e07-4d67-8671-d8cb76266c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044137832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3044137832
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3403012859
Short name T1235
Test name
Test status
Simulation time 1307982537 ps
CPU time 6.59 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:12 PM PDT 24
Peak memory 210884 kb
Host smart-05f3c59b-02f3-4bd3-acb3-bd431c340753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403012859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3403012859
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2301690386
Short name T334
Test name
Test status
Simulation time 54927592 ps
CPU time 0.61 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:18 PM PDT 24
Peak memory 201580 kb
Host smart-3938e7a2-e16e-47de-9b6f-fb132ff8da81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301690386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2301690386
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3386891582
Short name T636
Test name
Test status
Simulation time 38830687 ps
CPU time 1.15 seconds
Started Mar 17 02:54:03 PM PDT 24
Finished Mar 17 02:54:04 PM PDT 24
Peak memory 210972 kb
Host smart-2a062f4c-fcc3-43b4-a2cd-d0f5b3cfab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386891582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3386891582
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3370143394
Short name T566
Test name
Test status
Simulation time 231876295 ps
CPU time 3.97 seconds
Started Mar 17 02:54:08 PM PDT 24
Finished Mar 17 02:54:12 PM PDT 24
Peak memory 246872 kb
Host smart-c53951dc-ec05-440f-ab9e-ef2b399cb1cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370143394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3370143394
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2146272361
Short name T520
Test name
Test status
Simulation time 3433822133 ps
CPU time 311.1 seconds
Started Mar 17 02:54:04 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 1010804 kb
Host smart-0ef65d63-7411-4cb2-8d23-a56585b3eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146272361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2146272361
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3360534979
Short name T683
Test name
Test status
Simulation time 9961268040 ps
CPU time 90.5 seconds
Started Mar 17 02:54:04 PM PDT 24
Finished Mar 17 02:55:35 PM PDT 24
Peak memory 799708 kb
Host smart-ba5680a6-6678-4a4d-ada0-c33ddb7da1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360534979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3360534979
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3944654435
Short name T338
Test name
Test status
Simulation time 182794997 ps
CPU time 9.02 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:14 PM PDT 24
Peak memory 202680 kb
Host smart-63ec9202-e97e-48cd-b079-d56b4f1240c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944654435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3944654435
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.235637350
Short name T128
Test name
Test status
Simulation time 6558849352 ps
CPU time 69.31 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:55:15 PM PDT 24
Peak memory 931912 kb
Host smart-d90c7bc6-fe8c-4e0d-aa82-e1c4f5032137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235637350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.235637350
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_override.1865491608
Short name T148
Test name
Test status
Simulation time 21226690 ps
CPU time 0.64 seconds
Started Mar 17 02:54:05 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 201892 kb
Host smart-85221071-8c23-46db-be69-a736010fc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865491608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1865491608
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1327737392
Short name T767
Test name
Test status
Simulation time 50925706710 ps
CPU time 694.57 seconds
Started Mar 17 02:54:07 PM PDT 24
Finished Mar 17 03:05:42 PM PDT 24
Peak memory 210960 kb
Host smart-53b39575-138f-45d3-ba4f-772e23846366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327737392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1327737392
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2883972707
Short name T1006
Test name
Test status
Simulation time 7204423008 ps
CPU time 72.06 seconds
Started Mar 17 02:54:03 PM PDT 24
Finished Mar 17 02:55:15 PM PDT 24
Peak memory 333900 kb
Host smart-38b6a69c-6dc5-4834-a6ce-ee394b67ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883972707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2883972707
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2661121846
Short name T990
Test name
Test status
Simulation time 1677465477 ps
CPU time 15.28 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 02:54:39 PM PDT 24
Peak memory 218380 kb
Host smart-b99838b2-fefc-4b1b-ab88-f6b989910b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661121846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2661121846
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2592508413
Short name T614
Test name
Test status
Simulation time 2461574175 ps
CPU time 4.08 seconds
Started Mar 17 02:54:15 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 202804 kb
Host smart-664d9ddb-a7bf-4f14-b3e8-a76b228adc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592508413 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2592508413
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.4226837645
Short name T1156
Test name
Test status
Simulation time 10035865092 ps
CPU time 76.58 seconds
Started Mar 17 02:54:09 PM PDT 24
Finished Mar 17 02:55:26 PM PDT 24
Peak memory 626052 kb
Host smart-325dbc20-f76c-40fd-991a-800bbfbd8e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226837645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.4226837645
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3304271955
Short name T20
Test name
Test status
Simulation time 10156572591 ps
CPU time 98.55 seconds
Started Mar 17 02:54:08 PM PDT 24
Finished Mar 17 02:55:47 PM PDT 24
Peak memory 757836 kb
Host smart-b9128b48-59d6-4fb2-a7d1-808e99a0c294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304271955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3304271955
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3282031431
Short name T674
Test name
Test status
Simulation time 2099400965 ps
CPU time 2.72 seconds
Started Mar 17 02:54:10 PM PDT 24
Finished Mar 17 02:54:13 PM PDT 24
Peak memory 202824 kb
Host smart-e565f179-36a6-4c46-ae2d-8a6aa9c59c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282031431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3282031431
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.645727386
Short name T475
Test name
Test status
Simulation time 742330787 ps
CPU time 4.21 seconds
Started Mar 17 02:54:07 PM PDT 24
Finished Mar 17 02:54:11 PM PDT 24
Peak memory 202720 kb
Host smart-6358ba7f-7c13-4347-ad53-b34dc5c02bd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645727386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.645727386
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2090171019
Short name T570
Test name
Test status
Simulation time 10187447921 ps
CPU time 40.91 seconds
Started Mar 17 02:54:07 PM PDT 24
Finished Mar 17 02:54:48 PM PDT 24
Peak memory 836608 kb
Host smart-c04165a9-5fe0-47b9-97da-0c9144150470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090171019 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2090171019
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3608626676
Short name T633
Test name
Test status
Simulation time 993594059 ps
CPU time 3.21 seconds
Started Mar 17 02:54:09 PM PDT 24
Finished Mar 17 02:54:12 PM PDT 24
Peak memory 203632 kb
Host smart-f08b935c-8d59-45a5-abcf-164ca9e5c004
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608626676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3608626676
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.856011218
Short name T1216
Test name
Test status
Simulation time 3238096343 ps
CPU time 32.61 seconds
Started Mar 17 02:54:12 PM PDT 24
Finished Mar 17 02:54:45 PM PDT 24
Peak memory 202740 kb
Host smart-313fdf26-a8a0-427c-9e19-7ee1c3571a18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856011218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.856011218
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2624081215
Short name T1242
Test name
Test status
Simulation time 2943505773 ps
CPU time 7.09 seconds
Started Mar 17 02:54:09 PM PDT 24
Finished Mar 17 02:54:16 PM PDT 24
Peak memory 212740 kb
Host smart-fc70ac1f-97b9-410b-aab8-2bc4c8e0aa8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624081215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2624081215
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.792269092
Short name T875
Test name
Test status
Simulation time 1032161177 ps
CPU time 4.79 seconds
Started Mar 17 02:54:10 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 207460 kb
Host smart-7813ac10-32d5-4f7e-b156-91dffb88c8e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792269092 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_unexp_stop.792269092
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.569183188
Short name T970
Test name
Test status
Simulation time 43024355 ps
CPU time 0.63 seconds
Started Mar 17 02:54:20 PM PDT 24
Finished Mar 17 02:54:21 PM PDT 24
Peak memory 201664 kb
Host smart-6cbdec10-34be-4611-8a96-35e26c62e5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569183188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.569183188
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1984154565
Short name T921
Test name
Test status
Simulation time 40507633 ps
CPU time 1.34 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 203000 kb
Host smart-40263f61-ca1e-47ca-a1db-d71751ae844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984154565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1984154565
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.4292688034
Short name T967
Test name
Test status
Simulation time 1649172944 ps
CPU time 9.3 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:54:23 PM PDT 24
Peak memory 296500 kb
Host smart-a376b513-3dfb-433d-bf8d-c1d2c25dcee5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292688034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.4292688034
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3312858476
Short name T898
Test name
Test status
Simulation time 8984013483 ps
CPU time 64.67 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:55:18 PM PDT 24
Peak memory 482300 kb
Host smart-218533d8-dfcc-4cd8-b1e8-f582cd5135e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312858476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3312858476
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1432798341
Short name T258
Test name
Test status
Simulation time 2805926764 ps
CPU time 218.11 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:57:52 PM PDT 24
Peak memory 871760 kb
Host smart-eb055f8a-29cf-4e85-b9d4-0d163cb68535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432798341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1432798341
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2982289145
Short name T1037
Test name
Test status
Simulation time 90065313 ps
CPU time 0.9 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:54:14 PM PDT 24
Peak memory 202460 kb
Host smart-96064c47-702e-4918-a4a5-f26db867150e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982289145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2982289145
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2112428717
Short name T1055
Test name
Test status
Simulation time 1717546131 ps
CPU time 4.13 seconds
Started Mar 17 02:54:12 PM PDT 24
Finished Mar 17 02:54:17 PM PDT 24
Peak memory 202740 kb
Host smart-da7ba5a2-da9d-4731-840a-707b51e7b1f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112428717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2112428717
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3374760212
Short name T1104
Test name
Test status
Simulation time 5757392995 ps
CPU time 148.8 seconds
Started Mar 17 02:54:12 PM PDT 24
Finished Mar 17 02:56:41 PM PDT 24
Peak memory 1560432 kb
Host smart-e9f8eb2e-fe2c-4b0d-816b-2fe9e5baf60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374760212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3374760212
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.967175529
Short name T175
Test name
Test status
Simulation time 12391326734 ps
CPU time 114.09 seconds
Started Mar 17 02:54:20 PM PDT 24
Finished Mar 17 02:56:14 PM PDT 24
Peak memory 250024 kb
Host smart-e74a972d-88d1-4bb9-9d54-c0f36bc27c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967175529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.967175529
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_perf.4227633822
Short name T159
Test name
Test status
Simulation time 6151179316 ps
CPU time 111.96 seconds
Started Mar 17 02:54:12 PM PDT 24
Finished Mar 17 02:56:04 PM PDT 24
Peak memory 202860 kb
Host smart-51b3981b-ecc2-4044-996f-60b76eb9ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227633822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.4227633822
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.486333769
Short name T1127
Test name
Test status
Simulation time 6422813499 ps
CPU time 96.64 seconds
Started Mar 17 02:54:18 PM PDT 24
Finished Mar 17 02:55:55 PM PDT 24
Peak memory 259608 kb
Host smart-25281745-20b4-4d46-bd6a-e04ecf5ea150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486333769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.486333769
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.4177756684
Short name T123
Test name
Test status
Simulation time 24484481198 ps
CPU time 685.33 seconds
Started Mar 17 02:54:11 PM PDT 24
Finished Mar 17 03:05:37 PM PDT 24
Peak memory 948176 kb
Host smart-60e0bf62-1e1b-494b-b245-bf97e3aaec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177756684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.4177756684
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.296947800
Short name T276
Test name
Test status
Simulation time 3055146174 ps
CPU time 13.28 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 213308 kb
Host smart-97fdbc7d-f157-45ff-8190-f2b0097d8351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296947800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.296947800
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1695274705
Short name T540
Test name
Test status
Simulation time 3435609839 ps
CPU time 4.22 seconds
Started Mar 17 02:54:16 PM PDT 24
Finished Mar 17 02:54:20 PM PDT 24
Peak memory 202844 kb
Host smart-08704fe3-f847-4d14-b994-c2a45a0237b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695274705 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1695274705
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3940612477
Short name T1264
Test name
Test status
Simulation time 10160276088 ps
CPU time 75.85 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:55:33 PM PDT 24
Peak memory 598048 kb
Host smart-e472b18e-6168-47e3-94f0-03a806cb5f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940612477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3940612477
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1594682413
Short name T1002
Test name
Test status
Simulation time 10172041830 ps
CPU time 14.84 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:32 PM PDT 24
Peak memory 309972 kb
Host smart-b2b9da68-a3a5-4bdc-ae0a-693b635a633d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594682413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1594682413
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3693147850
Short name T1174
Test name
Test status
Simulation time 512505207 ps
CPU time 1.84 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 202692 kb
Host smart-c7100ae3-d30a-4a26-aba0-dad5f4e9df4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693147850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3693147850
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1180573160
Short name T696
Test name
Test status
Simulation time 841144262 ps
CPU time 4.38 seconds
Started Mar 17 02:54:14 PM PDT 24
Finished Mar 17 02:54:18 PM PDT 24
Peak memory 204896 kb
Host smart-60899407-5ee4-4ea1-864b-9f24bbfa5a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180573160 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1180573160
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1081576337
Short name T415
Test name
Test status
Simulation time 13405456905 ps
CPU time 114.63 seconds
Started Mar 17 02:54:13 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 1727360 kb
Host smart-771818e8-fe8e-4108-8a0d-add003173672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081576337 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1081576337
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.255801313
Short name T1012
Test name
Test status
Simulation time 670675541 ps
CPU time 4.27 seconds
Started Mar 17 02:54:15 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 202648 kb
Host smart-5e26d957-0616-4049-b855-a2a89e5b1ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255801313 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_perf.255801313
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2873959356
Short name T236
Test name
Test status
Simulation time 559136697 ps
CPU time 7.13 seconds
Started Mar 17 02:54:15 PM PDT 24
Finished Mar 17 02:54:22 PM PDT 24
Peak memory 203836 kb
Host smart-f04c6bb7-ab22-4f74-8d6a-3ba5185a82e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873959356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2873959356
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2709133539
Short name T141
Test name
Test status
Simulation time 62309122184 ps
CPU time 2183.31 seconds
Started Mar 17 02:54:15 PM PDT 24
Finished Mar 17 03:30:38 PM PDT 24
Peak memory 10479828 kb
Host smart-34b38d57-bd32-40e1-9b76-9585e381bf12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709133539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2709133539
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1444886114
Short name T300
Test name
Test status
Simulation time 48977269134 ps
CPU time 230.02 seconds
Started Mar 17 02:54:14 PM PDT 24
Finished Mar 17 02:58:05 PM PDT 24
Peak memory 840516 kb
Host smart-8f1aa9e1-0de9-4bf5-b97a-fdbd000694f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444886114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1444886114
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1136113753
Short name T873
Test name
Test status
Simulation time 9775926601 ps
CPU time 6.69 seconds
Started Mar 17 02:54:16 PM PDT 24
Finished Mar 17 02:54:22 PM PDT 24
Peak memory 207588 kb
Host smart-a74c263e-d371-42ad-a0f7-0ed2078deae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136113753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1136113753
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.2319008655
Short name T615
Test name
Test status
Simulation time 1203862780 ps
CPU time 6.15 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:23 PM PDT 24
Peak memory 202704 kb
Host smart-e3fdeb55-8f26-43ec-ac75-0d39c26b6a52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319008655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.2319008655
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.764499392
Short name T350
Test name
Test status
Simulation time 18702086 ps
CPU time 0.65 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 02:54:28 PM PDT 24
Peak memory 201624 kb
Host smart-6c0136f5-166f-45cb-b140-de6350160993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764499392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.764499392
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3818624183
Short name T581
Test name
Test status
Simulation time 98448552 ps
CPU time 1.51 seconds
Started Mar 17 02:54:22 PM PDT 24
Finished Mar 17 02:54:24 PM PDT 24
Peak memory 210960 kb
Host smart-8f01a9f4-e022-4325-8ea8-f718253115e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818624183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3818624183
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1085363850
Short name T360
Test name
Test status
Simulation time 571130036 ps
CPU time 7.88 seconds
Started Mar 17 02:54:18 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 277732 kb
Host smart-bda10af8-772b-4a87-bc88-096429ef1366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085363850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1085363850
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.448591916
Short name T270
Test name
Test status
Simulation time 2512282182 ps
CPU time 72.68 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 696068 kb
Host smart-31b8a8c6-87e2-425b-88d2-565ff68e1979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448591916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.448591916
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1012344673
Short name T880
Test name
Test status
Simulation time 3352029203 ps
CPU time 65.18 seconds
Started Mar 17 02:54:15 PM PDT 24
Finished Mar 17 02:55:21 PM PDT 24
Peak memory 645488 kb
Host smart-2e15219c-8594-4108-91b0-6ba7e14f71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012344673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1012344673
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2770215472
Short name T421
Test name
Test status
Simulation time 97258772 ps
CPU time 0.9 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:18 PM PDT 24
Peak memory 202424 kb
Host smart-8a7057f7-740f-4940-8476-d2cc6d4c1962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770215472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2770215472
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4125707966
Short name T422
Test name
Test status
Simulation time 717274228 ps
CPU time 3.73 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:21 PM PDT 24
Peak memory 202728 kb
Host smart-4b5ac9ba-623e-40c0-81b5-f9d8fd61a518
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125707966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4125707966
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.204968698
Short name T714
Test name
Test status
Simulation time 4452715190 ps
CPU time 102.66 seconds
Started Mar 17 02:54:19 PM PDT 24
Finished Mar 17 02:56:02 PM PDT 24
Peak memory 1044020 kb
Host smart-0a27c6b1-6682-4376-8f26-fd1a5483cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204968698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.204968698
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3730958711
Short name T660
Test name
Test status
Simulation time 3544866160 ps
CPU time 50.25 seconds
Started Mar 17 02:54:21 PM PDT 24
Finished Mar 17 02:55:12 PM PDT 24
Peak memory 232492 kb
Host smart-dd45ae53-304d-43df-ae31-bef1e1295948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730958711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3730958711
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1883890920
Short name T560
Test name
Test status
Simulation time 149628771 ps
CPU time 0.63 seconds
Started Mar 17 02:54:17 PM PDT 24
Finished Mar 17 02:54:17 PM PDT 24
Peak memory 201900 kb
Host smart-51e90f33-95bc-4f22-8e06-c39faca242b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883890920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1883890920
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2695593578
Short name T163
Test name
Test status
Simulation time 8041038393 ps
CPU time 40.65 seconds
Started Mar 17 02:54:21 PM PDT 24
Finished Mar 17 02:55:02 PM PDT 24
Peak memory 290856 kb
Host smart-f1aa1c48-8311-4697-8e87-a0d37fb9e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695593578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2695593578
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2088154045
Short name T688
Test name
Test status
Simulation time 2763710437 ps
CPU time 98.02 seconds
Started Mar 17 02:54:21 PM PDT 24
Finished Mar 17 02:55:59 PM PDT 24
Peak memory 346984 kb
Host smart-a4458972-d3c0-44ca-91cc-4e219f118518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088154045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2088154045
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2738157358
Short name T1179
Test name
Test status
Simulation time 4596487735 ps
CPU time 15.51 seconds
Started Mar 17 02:54:21 PM PDT 24
Finished Mar 17 02:54:37 PM PDT 24
Peak memory 213212 kb
Host smart-841b57c2-ad90-44ec-9030-71dce9805c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738157358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2738157358
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2791422520
Short name T1200
Test name
Test status
Simulation time 3585408989 ps
CPU time 4.03 seconds
Started Mar 17 02:54:21 PM PDT 24
Finished Mar 17 02:54:25 PM PDT 24
Peak memory 202760 kb
Host smart-992b879f-387a-476d-9f64-b7ce6cbdf010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791422520 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2791422520
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.783485050
Short name T489
Test name
Test status
Simulation time 10105818747 ps
CPU time 96.61 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 717060 kb
Host smart-5fe57327-9b49-47d0-9212-7f4d0491e116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783485050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.783485050
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1706941563
Short name T852
Test name
Test status
Simulation time 411803440 ps
CPU time 2.45 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 202900 kb
Host smart-13afae92-7b2c-459d-b7aa-a7590d6d876f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706941563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1706941563
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.4291513652
Short name T1159
Test name
Test status
Simulation time 1475263351 ps
CPU time 3.42 seconds
Started Mar 17 02:54:22 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 202740 kb
Host smart-af52ee97-1c31-4446-ade8-069dc724df29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291513652 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.4291513652
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_perf.3168985479
Short name T686
Test name
Test status
Simulation time 2961880348 ps
CPU time 5.04 seconds
Started Mar 17 02:54:22 PM PDT 24
Finished Mar 17 02:54:27 PM PDT 24
Peak memory 202736 kb
Host smart-c08e1e52-e416-4699-b7c8-bb88cb2cf84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168985479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.3168985479
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.715595132
Short name T691
Test name
Test status
Simulation time 35498859696 ps
CPU time 29.51 seconds
Started Mar 17 02:54:22 PM PDT 24
Finished Mar 17 02:54:51 PM PDT 24
Peak memory 730760 kb
Host smart-a622e58c-2745-4beb-b4e1-d762a5617f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715595132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.715595132
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1015892636
Short name T384
Test name
Test status
Simulation time 33504669438 ps
CPU time 1514.57 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 03:19:38 PM PDT 24
Peak memory 3097484 kb
Host smart-203d92ae-a432-4544-bdd9-75fe9e4def92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015892636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1015892636
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_alert_test.105358621
Short name T454
Test name
Test status
Simulation time 17708577 ps
CPU time 0.65 seconds
Started Mar 17 02:54:33 PM PDT 24
Finished Mar 17 02:54:34 PM PDT 24
Peak memory 201592 kb
Host smart-eabf9a1e-dc2b-40fe-b873-89c8fba657e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105358621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.105358621
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2898726961
Short name T726
Test name
Test status
Simulation time 192571733 ps
CPU time 1.69 seconds
Started Mar 17 02:54:25 PM PDT 24
Finished Mar 17 02:54:27 PM PDT 24
Peak memory 210924 kb
Host smart-313fe820-e6ff-4f6a-aa07-aadc8de174b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898726961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2898726961
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2570625984
Short name T883
Test name
Test status
Simulation time 918577787 ps
CPU time 12.05 seconds
Started Mar 17 02:54:25 PM PDT 24
Finished Mar 17 02:54:37 PM PDT 24
Peak memory 245916 kb
Host smart-d89b53d0-a43f-4d3b-9520-7704aea1dd36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570625984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2570625984
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2147207838
Short name T1263
Test name
Test status
Simulation time 3331491801 ps
CPU time 265.77 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:58:55 PM PDT 24
Peak memory 985584 kb
Host smart-a5c85ad7-31a0-403c-b653-ed9b707004e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147207838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2147207838
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.4239511633
Short name T957
Test name
Test status
Simulation time 8114046574 ps
CPU time 131.22 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 02:56:38 PM PDT 24
Peak memory 648292 kb
Host smart-0c8b8963-9999-4a27-ae18-2cb33881ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239511633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.4239511633
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1835667982
Short name T884
Test name
Test status
Simulation time 1021998808 ps
CPU time 9.53 seconds
Started Mar 17 02:54:25 PM PDT 24
Finished Mar 17 02:54:35 PM PDT 24
Peak memory 232104 kb
Host smart-1f4d122c-11ce-4e3c-af9f-c8cba23479f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835667982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1835667982
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3305103566
Short name T784
Test name
Test status
Simulation time 3504995578 ps
CPU time 246.46 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 02:58:30 PM PDT 24
Peak memory 1064772 kb
Host smart-dcad607e-be1e-4ef6-997d-68ab64ee1fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305103566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3305103566
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2211107255
Short name T476
Test name
Test status
Simulation time 3651403711 ps
CPU time 55.03 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:55:31 PM PDT 24
Peak memory 322092 kb
Host smart-25000805-99f4-4fae-9456-9695344b7ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211107255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2211107255
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.736342616
Short name T635
Test name
Test status
Simulation time 42547888 ps
CPU time 0.61 seconds
Started Mar 17 02:54:23 PM PDT 24
Finished Mar 17 02:54:23 PM PDT 24
Peak memory 201792 kb
Host smart-b9f91ae0-6789-4560-aaf6-93262d51881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736342616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.736342616
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1853426273
Short name T561
Test name
Test status
Simulation time 1660218625 ps
CPU time 22.9 seconds
Started Mar 17 02:54:26 PM PDT 24
Finished Mar 17 02:54:49 PM PDT 24
Peak memory 202748 kb
Host smart-0935eba4-d154-4714-941f-15deb245e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853426273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1853426273
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.595241734
Short name T286
Test name
Test status
Simulation time 4870113971 ps
CPU time 89 seconds
Started Mar 17 02:54:24 PM PDT 24
Finished Mar 17 02:55:53 PM PDT 24
Peak memory 346852 kb
Host smart-7e3415a1-98e0-47a1-b529-a0aae0250dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595241734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.595241734
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.173530051
Short name T1245
Test name
Test status
Simulation time 22909888644 ps
CPU time 2317.04 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 03:33:05 PM PDT 24
Peak memory 3759152 kb
Host smart-88e129cb-5684-4bf3-8be9-81d9558c57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173530051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.173530051
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3295671868
Short name T927
Test name
Test status
Simulation time 22199150253 ps
CPU time 20.8 seconds
Started Mar 17 02:54:26 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 227260 kb
Host smart-6d4b9a22-531c-4806-aaeb-01bfbf8cf567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295671868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3295671868
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1006343159
Short name T613
Test name
Test status
Simulation time 4765847969 ps
CPU time 4.84 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:54:34 PM PDT 24
Peak memory 202648 kb
Host smart-ea5ffe09-158a-44be-8dcc-57834a8d7df7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006343159 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1006343159
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3021853194
Short name T1247
Test name
Test status
Simulation time 10148314083 ps
CPU time 14.13 seconds
Started Mar 17 02:54:30 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 293160 kb
Host smart-a6ef2526-bfe7-4dbf-98fe-9b561bf3bb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021853194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3021853194
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.85256377
Short name T1077
Test name
Test status
Simulation time 10463418882 ps
CPU time 15.6 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 327220 kb
Host smart-cffa62e9-1324-4657-b06a-b8c7e6f81bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85256377 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_fifo_reset_tx.85256377
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.363935120
Short name T930
Test name
Test status
Simulation time 1555881604 ps
CPU time 2.33 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:54:31 PM PDT 24
Peak memory 202704 kb
Host smart-a9e4ba75-a2aa-49e6-97ca-76e0bc3e7e06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363935120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.363935120
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_perf.2601793743
Short name T261
Test name
Test status
Simulation time 2320646568 ps
CPU time 3.31 seconds
Started Mar 17 02:54:26 PM PDT 24
Finished Mar 17 02:54:29 PM PDT 24
Peak memory 202820 kb
Host smart-3bc50821-6ef1-4cd2-9e48-bb03db12ab9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601793743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.2601793743
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1762330701
Short name T1144
Test name
Test status
Simulation time 1594248834 ps
CPU time 45.93 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 02:55:13 PM PDT 24
Peak memory 202668 kb
Host smart-e2606242-e427-4ee6-a2f1-c06d97082c55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762330701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1762330701
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.81068288
Short name T146
Test name
Test status
Simulation time 58494504707 ps
CPU time 1915.34 seconds
Started Mar 17 02:54:27 PM PDT 24
Finished Mar 17 03:26:23 PM PDT 24
Peak memory 9827448 kb
Host smart-432f283e-3c98-4781-9d3e-f22f54e7b0b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81068288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stress_wr.81068288
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.273867802
Short name T924
Test name
Test status
Simulation time 29105507908 ps
CPU time 139.24 seconds
Started Mar 17 02:54:29 PM PDT 24
Finished Mar 17 02:56:48 PM PDT 24
Peak memory 1464504 kb
Host smart-7e30cac7-8bee-4584-bee9-ff92926fa456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273867802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.273867802
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3447233132
Short name T1195
Test name
Test status
Simulation time 4732451099 ps
CPU time 6.49 seconds
Started Mar 17 02:54:26 PM PDT 24
Finished Mar 17 02:54:32 PM PDT 24
Peak memory 208280 kb
Host smart-d45fe6ed-7a4c-478c-9abc-3329d74fff58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447233132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3447233132
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1820706310
Short name T94
Test name
Test status
Simulation time 57294360 ps
CPU time 0.6 seconds
Started Mar 17 02:54:42 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 201516 kb
Host smart-543de37c-fa10-4c54-84f7-6298894befea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820706310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1820706310
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3665762087
Short name T17
Test name
Test status
Simulation time 69498656 ps
CPU time 1.13 seconds
Started Mar 17 02:54:34 PM PDT 24
Finished Mar 17 02:54:36 PM PDT 24
Peak memory 219188 kb
Host smart-029602d6-c957-4fee-bf43-ab8023840902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665762087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3665762087
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1861505324
Short name T704
Test name
Test status
Simulation time 530919549 ps
CPU time 21.17 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:54:56 PM PDT 24
Peak memory 266688 kb
Host smart-7817fafc-4a17-4fdd-bda4-2948cdb4a70c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861505324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1861505324
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.671187787
Short name T226
Test name
Test status
Simulation time 10286210973 ps
CPU time 191.26 seconds
Started Mar 17 02:54:34 PM PDT 24
Finished Mar 17 02:57:45 PM PDT 24
Peak memory 818464 kb
Host smart-ec72d375-fd57-4ada-a224-9763932c9d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671187787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.671187787
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.619509302
Short name T979
Test name
Test status
Simulation time 3925976664 ps
CPU time 146.93 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:57:03 PM PDT 24
Peak memory 691932 kb
Host smart-2da1b25e-0859-4c1c-8db6-4a0c87febdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619509302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.619509302
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3943023435
Short name T1024
Test name
Test status
Simulation time 123148353 ps
CPU time 1.07 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:54:37 PM PDT 24
Peak memory 202856 kb
Host smart-9d4cf219-08b0-4c97-926a-1f999c2753c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943023435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3943023435
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3855820847
Short name T1191
Test name
Test status
Simulation time 171961147 ps
CPU time 8.91 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 202692 kb
Host smart-87f47cc8-0eb1-4600-87f1-621ce64dbfcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855820847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3855820847
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.552174627
Short name T1157
Test name
Test status
Simulation time 12691222779 ps
CPU time 121.39 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:56:38 PM PDT 24
Peak memory 1372208 kb
Host smart-01ae6a08-e80d-4c10-8149-da64a412540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552174627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.552174627
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3526406617
Short name T237
Test name
Test status
Simulation time 2358690247 ps
CPU time 139.63 seconds
Started Mar 17 02:54:45 PM PDT 24
Finished Mar 17 02:57:05 PM PDT 24
Peak memory 263644 kb
Host smart-fb599892-64a3-46c4-8378-437617c36be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526406617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3526406617
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.823989813
Short name T154
Test name
Test status
Simulation time 19074110 ps
CPU time 0.62 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:54:36 PM PDT 24
Peak memory 201808 kb
Host smart-c8cfbed0-9f56-4146-b3e9-1f5c2ce73185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823989813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.823989813
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1780924895
Short name T982
Test name
Test status
Simulation time 1811781936 ps
CPU time 7.25 seconds
Started Mar 17 02:54:34 PM PDT 24
Finished Mar 17 02:54:42 PM PDT 24
Peak memory 222816 kb
Host smart-2ff5a27e-44b8-4d17-b37e-45f94bc9ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780924895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1780924895
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3311311427
Short name T269
Test name
Test status
Simulation time 2674697356 ps
CPU time 37.74 seconds
Started Mar 17 02:54:34 PM PDT 24
Finished Mar 17 02:55:12 PM PDT 24
Peak memory 267048 kb
Host smart-bb1b9bcb-36d1-4cf7-8615-934e87894487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311311427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3311311427
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.958676807
Short name T1067
Test name
Test status
Simulation time 19291516389 ps
CPU time 1615.32 seconds
Started Mar 17 02:54:33 PM PDT 24
Finished Mar 17 03:21:29 PM PDT 24
Peak memory 3071164 kb
Host smart-a89aa227-cbeb-4dba-92bd-9e1d928769df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958676807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.958676807
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3081684088
Short name T1036
Test name
Test status
Simulation time 1455952704 ps
CPU time 12.81 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:54:49 PM PDT 24
Peak memory 211868 kb
Host smart-cfadb94f-99a2-4160-a2b0-f212cf4f25e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081684088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3081684088
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2985226384
Short name T1119
Test name
Test status
Simulation time 10214494397 ps
CPU time 15.42 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:54:51 PM PDT 24
Peak memory 299736 kb
Host smart-fdfff40f-030b-4f89-8d77-76f55344250c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985226384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2985226384
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1358886917
Short name T392
Test name
Test status
Simulation time 10107962426 ps
CPU time 95.76 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 716192 kb
Host smart-051b9c83-b397-487f-889d-5de479aedf66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358886917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1358886917
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1461454962
Short name T221
Test name
Test status
Simulation time 3695993886 ps
CPU time 2.42 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 202800 kb
Host smart-f5194716-8321-4d60-b0ea-2714a002dcf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461454962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1461454962
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.589966170
Short name T282
Test name
Test status
Simulation time 28574679043 ps
CPU time 7.15 seconds
Started Mar 17 02:54:36 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 202748 kb
Host smart-7dd5c50b-901e-48c9-b07b-64b1a90bb4c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589966170 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.589966170
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.1587519025
Short name T890
Test name
Test status
Simulation time 2103243245 ps
CPU time 3.63 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 202764 kb
Host smart-1c6a10eb-d5ce-4ed2-a124-f577a36f9c3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587519025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.1587519025
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3587919856
Short name T594
Test name
Test status
Simulation time 4446958799 ps
CPU time 30.31 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:55:06 PM PDT 24
Peak memory 202752 kb
Host smart-d28caa12-6650-48a5-8487-54f6da60121c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587919856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3587919856
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2860550899
Short name T1017
Test name
Test status
Simulation time 12731060607 ps
CPU time 26.53 seconds
Started Mar 17 02:54:30 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 202732 kb
Host smart-865d7b45-e6c2-49d8-a75a-6ba436d950f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860550899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2860550899
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2799763412
Short name T1190
Test name
Test status
Simulation time 3387224762 ps
CPU time 8.04 seconds
Started Mar 17 02:54:35 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 215724 kb
Host smart-2da7be2e-4d18-49de-a316-3d071c662ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799763412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2799763412
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1600486332
Short name T862
Test name
Test status
Simulation time 31253263 ps
CPU time 0.62 seconds
Started Mar 17 02:54:45 PM PDT 24
Finished Mar 17 02:54:46 PM PDT 24
Peak memory 201524 kb
Host smart-e811f912-acb0-4fb2-bb18-d352e75349ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600486332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1600486332
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2936938051
Short name T868
Test name
Test status
Simulation time 96749768 ps
CPU time 1.5 seconds
Started Mar 17 02:54:41 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 211044 kb
Host smart-129d9fa2-f482-491b-a37a-5211d03daa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936938051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2936938051
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2514954161
Short name T1167
Test name
Test status
Simulation time 1415388406 ps
CPU time 12.14 seconds
Started Mar 17 02:54:41 PM PDT 24
Finished Mar 17 02:54:53 PM PDT 24
Peak memory 319660 kb
Host smart-7e2484e4-c1c9-415a-872b-19bede0122e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514954161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2514954161
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3116696855
Short name T298
Test name
Test status
Simulation time 1888411437 ps
CPU time 96.32 seconds
Started Mar 17 02:54:42 PM PDT 24
Finished Mar 17 02:56:19 PM PDT 24
Peak memory 372952 kb
Host smart-70b32d1c-c24a-456e-92c9-53f7d0e0a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116696855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3116696855
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.104541653
Short name T1228
Test name
Test status
Simulation time 4446618398 ps
CPU time 79.77 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:56:03 PM PDT 24
Peak memory 719492 kb
Host smart-25f00a29-e46b-4579-8ced-34fad6ddff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104541653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.104541653
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3901903475
Short name T518
Test name
Test status
Simulation time 324810101 ps
CPU time 0.93 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 202492 kb
Host smart-5b1bd057-6f50-4238-84b5-85f2ecfd8c69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901903475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3901903475
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.68661941
Short name T780
Test name
Test status
Simulation time 1218122309 ps
CPU time 3.12 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 202704 kb
Host smart-9ab3f02a-2a3b-4d8b-a734-7332716faeff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68661941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.68661941
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1869047952
Short name T602
Test name
Test status
Simulation time 8085959599 ps
CPU time 111.6 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:56:35 PM PDT 24
Peak memory 250380 kb
Host smart-c4855712-2fe6-4076-b638-adc03e2361bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869047952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1869047952
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2075169811
Short name T736
Test name
Test status
Simulation time 61480279 ps
CPU time 0.67 seconds
Started Mar 17 02:54:42 PM PDT 24
Finished Mar 17 02:54:43 PM PDT 24
Peak memory 201868 kb
Host smart-2b251ca8-c624-43fb-9514-0f4cd4f76e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075169811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2075169811
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.584872835
Short name T1008
Test name
Test status
Simulation time 1639708184 ps
CPU time 24.19 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:55:04 PM PDT 24
Peak memory 210908 kb
Host smart-ac38b779-d0a2-4ead-8a98-9a7dcdd17501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584872835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.584872835
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3398058464
Short name T227
Test name
Test status
Simulation time 1639658812 ps
CPU time 90.79 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:56:15 PM PDT 24
Peak memory 235356 kb
Host smart-72e99507-1cae-4a2c-ad5e-3bde99b32fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398058464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3398058464
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.4105778042
Short name T1249
Test name
Test status
Simulation time 43236127193 ps
CPU time 1004.12 seconds
Started Mar 17 02:54:45 PM PDT 24
Finished Mar 17 03:11:30 PM PDT 24
Peak memory 2013196 kb
Host smart-6e5190ec-8d2b-487e-8753-f4d033185dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105778042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4105778042
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2300569430
Short name T1143
Test name
Test status
Simulation time 389975924 ps
CPU time 15.67 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:54:55 PM PDT 24
Peak memory 210856 kb
Host smart-6732de7f-dc01-4998-8e81-a0e278d4c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300569430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2300569430
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3161121656
Short name T682
Test name
Test status
Simulation time 767238760 ps
CPU time 3.36 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 202676 kb
Host smart-f1c8e020-8fa1-4df0-9fc2-b126a801e038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161121656 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3161121656
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.407717591
Short name T859
Test name
Test status
Simulation time 10074870980 ps
CPU time 66.02 seconds
Started Mar 17 02:54:47 PM PDT 24
Finished Mar 17 02:55:53 PM PDT 24
Peak memory 617624 kb
Host smart-efc96903-9951-4679-807b-c4bfdf44e9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407717591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.407717591
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1873401558
Short name T938
Test name
Test status
Simulation time 1384138559 ps
CPU time 2.05 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:54:45 PM PDT 24
Peak memory 202756 kb
Host smart-e9602363-0d49-4079-b6cd-8f47de68556d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873401558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1873401558
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3079811001
Short name T825
Test name
Test status
Simulation time 1414121525 ps
CPU time 6.38 seconds
Started Mar 17 02:54:41 PM PDT 24
Finished Mar 17 02:54:48 PM PDT 24
Peak memory 202712 kb
Host smart-b34eafd2-f8e0-4320-8628-52143d44b9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079811001 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3079811001
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.920651577
Short name T781
Test name
Test status
Simulation time 9153528806 ps
CPU time 30.29 seconds
Started Mar 17 02:54:41 PM PDT 24
Finished Mar 17 02:55:12 PM PDT 24
Peak memory 602272 kb
Host smart-4df42098-27e6-4645-bab8-29d4c037b2a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920651577 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.920651577
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.482564011
Short name T1112
Test name
Test status
Simulation time 2734053546 ps
CPU time 4.03 seconds
Started Mar 17 02:54:46 PM PDT 24
Finished Mar 17 02:54:51 PM PDT 24
Peak memory 203452 kb
Host smart-7fe4518e-5f09-4d10-948a-30a1645a4a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482564011 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_perf.482564011
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.89937270
Short name T798
Test name
Test status
Simulation time 2850077471 ps
CPU time 42.19 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:55:21 PM PDT 24
Peak memory 202724 kb
Host smart-79b85c52-ce1c-4d83-b51f-b8bd00cd0b69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89937270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_targ
et_smoke.89937270
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.3330500048
Short name T1065
Test name
Test status
Simulation time 17762214420 ps
CPU time 114.69 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:56:38 PM PDT 24
Peak memory 514172 kb
Host smart-ed247f56-1b90-4fdd-982a-657507f581d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330500048 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.3330500048
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.4294776159
Short name T1075
Test name
Test status
Simulation time 39966883278 ps
CPU time 219.61 seconds
Started Mar 17 02:54:40 PM PDT 24
Finished Mar 17 02:58:20 PM PDT 24
Peak memory 2569420 kb
Host smart-79e7647f-0ca7-4d2f-be9a-66d6d39f6be4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294776159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.4294776159
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3378147228
Short name T1049
Test name
Test status
Simulation time 6835129431 ps
CPU time 35.93 seconds
Started Mar 17 02:54:39 PM PDT 24
Finished Mar 17 02:55:16 PM PDT 24
Peak memory 574252 kb
Host smart-dbf47863-8604-455f-963f-a32135791dc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378147228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3378147228
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1021662208
Short name T353
Test name
Test status
Simulation time 1706971518 ps
CPU time 7.91 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:54:51 PM PDT 24
Peak memory 211444 kb
Host smart-580023d2-3f4d-49d3-a4ba-b4d3782d3d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021662208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1021662208
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.3161130797
Short name T335
Test name
Test status
Simulation time 3007753118 ps
CPU time 5.3 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:54:50 PM PDT 24
Peak memory 202756 kb
Host smart-702a34d4-f262-4949-967e-b9b4becfb0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161130797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.3161130797
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3611362285
Short name T609
Test name
Test status
Simulation time 57687792 ps
CPU time 0.6 seconds
Started Mar 17 02:54:54 PM PDT 24
Finished Mar 17 02:54:54 PM PDT 24
Peak memory 201652 kb
Host smart-19278839-0c27-41f5-8e67-2958e223a312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611362285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3611362285
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.4258114634
Short name T732
Test name
Test status
Simulation time 139192473 ps
CPU time 1.23 seconds
Started Mar 17 02:54:49 PM PDT 24
Finished Mar 17 02:54:51 PM PDT 24
Peak memory 202692 kb
Host smart-4b5fe9d6-8bc9-41c1-b812-634600b89247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258114634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.4258114634
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3635311084
Short name T885
Test name
Test status
Simulation time 3770456883 ps
CPU time 9.34 seconds
Started Mar 17 02:54:48 PM PDT 24
Finished Mar 17 02:54:58 PM PDT 24
Peak memory 316464 kb
Host smart-17ffe4f0-5190-404f-b6f0-4a1777b73901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635311084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3635311084
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4178848187
Short name T1021
Test name
Test status
Simulation time 4991312440 ps
CPU time 61.75 seconds
Started Mar 17 02:54:49 PM PDT 24
Finished Mar 17 02:55:51 PM PDT 24
Peak memory 713176 kb
Host smart-5a3befec-faf1-40f6-a149-68d200f08410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178848187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4178848187
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3050110642
Short name T947
Test name
Test status
Simulation time 1924792859 ps
CPU time 67.17 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:55:52 PM PDT 24
Peak memory 666396 kb
Host smart-406b9512-b13f-400f-bc8b-24c75825c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050110642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3050110642
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1894401522
Short name T449
Test name
Test status
Simulation time 237068191 ps
CPU time 1.06 seconds
Started Mar 17 02:54:46 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 202636 kb
Host smart-cb7b189d-ba92-424e-94ae-f7799a932858
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894401522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1894401522
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.4048875348
Short name T1203
Test name
Test status
Simulation time 472554885 ps
CPU time 3.31 seconds
Started Mar 17 02:54:48 PM PDT 24
Finished Mar 17 02:54:52 PM PDT 24
Peak memory 224900 kb
Host smart-e02caafe-6846-4b21-9398-686f485bd36a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048875348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.4048875348
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.408417929
Short name T565
Test name
Test status
Simulation time 14074519775 ps
CPU time 303.27 seconds
Started Mar 17 02:54:46 PM PDT 24
Finished Mar 17 02:59:49 PM PDT 24
Peak memory 1119188 kb
Host smart-d52ae4ef-8337-4be6-bf63-72cda4c969d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408417929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.408417929
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2136343418
Short name T978
Test name
Test status
Simulation time 12653293333 ps
CPU time 52.53 seconds
Started Mar 17 02:54:52 PM PDT 24
Finished Mar 17 02:55:45 PM PDT 24
Peak memory 280604 kb
Host smart-16de9b3b-a55b-4b8c-8848-35d1e562d3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136343418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2136343418
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.3109033613
Short name T1095
Test name
Test status
Simulation time 26487283 ps
CPU time 0.65 seconds
Started Mar 17 02:54:43 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 201856 kb
Host smart-a14bf7f6-4287-4bbb-92ab-69a22d12bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109033613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3109033613
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.894683167
Short name T680
Test name
Test status
Simulation time 6401669805 ps
CPU time 126.55 seconds
Started Mar 17 02:54:50 PM PDT 24
Finished Mar 17 02:56:57 PM PDT 24
Peak memory 275592 kb
Host smart-cb72b452-b086-49ad-bc9c-ff9b676d7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894683167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.894683167
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1033549726
Short name T853
Test name
Test status
Simulation time 4308504978 ps
CPU time 82.45 seconds
Started Mar 17 02:54:44 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 347356 kb
Host smart-e42c85c1-0e00-4bd0-9770-122c060ce189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033549726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1033549726
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2838977282
Short name T1175
Test name
Test status
Simulation time 44525865108 ps
CPU time 1803.19 seconds
Started Mar 17 02:54:47 PM PDT 24
Finished Mar 17 03:24:51 PM PDT 24
Peak memory 1566224 kb
Host smart-644cdd4a-c33b-45fe-9ab9-e4c3ffc33727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838977282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2838977282
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3770407651
Short name T590
Test name
Test status
Simulation time 1662049786 ps
CPU time 10.07 seconds
Started Mar 17 02:54:50 PM PDT 24
Finished Mar 17 02:55:00 PM PDT 24
Peak memory 218408 kb
Host smart-2607d9f2-0b7b-486f-aaf5-0db8fc3ed454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770407651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3770407651
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3081755960
Short name T214
Test name
Test status
Simulation time 10226571082 ps
CPU time 19.5 seconds
Started Mar 17 02:54:48 PM PDT 24
Finished Mar 17 02:55:08 PM PDT 24
Peak memory 301312 kb
Host smart-a2cec435-31bf-47ae-abe2-d9e34b96c000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081755960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3081755960
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3069717868
Short name T749
Test name
Test status
Simulation time 10405897852 ps
CPU time 13.53 seconds
Started Mar 17 02:54:49 PM PDT 24
Finished Mar 17 02:55:02 PM PDT 24
Peak memory 310460 kb
Host smart-eff77645-4409-4ee8-a8f2-725ee2690e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069717868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3069717868
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_perf.2758379718
Short name T620
Test name
Test status
Simulation time 2655430137 ps
CPU time 4.07 seconds
Started Mar 17 02:54:49 PM PDT 24
Finished Mar 17 02:54:54 PM PDT 24
Peak memory 203828 kb
Host smart-bd571d8b-320b-4ac5-bc2b-dbac42312fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758379718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.2758379718
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1572149519
Short name T501
Test name
Test status
Simulation time 13422419156 ps
CPU time 7.4 seconds
Started Mar 17 02:54:50 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 202816 kb
Host smart-eea360af-6b9b-4f23-aaf7-f9b7a0610c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572149519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1572149519
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.682970033
Short name T638
Test name
Test status
Simulation time 22507862699 ps
CPU time 422.94 seconds
Started Mar 17 02:54:50 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 2602788 kb
Host smart-8d811500-3e00-4777-9433-b92870a24ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682970033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t
arget_stretch.682970033
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.454782725
Short name T91
Test name
Test status
Simulation time 5345490098 ps
CPU time 6.97 seconds
Started Mar 17 02:54:50 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 212672 kb
Host smart-b7c83123-11f2-427e-9d7b-1f12db5020c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454782725 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.454782725
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2128566407
Short name T684
Test name
Test status
Simulation time 17882891 ps
CPU time 0.62 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:54:58 PM PDT 24
Peak memory 201496 kb
Host smart-c37142ce-395b-4310-8549-da7144292d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128566407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2128566407
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3642749307
Short name T366
Test name
Test status
Simulation time 220755059 ps
CPU time 1.41 seconds
Started Mar 17 02:54:52 PM PDT 24
Finished Mar 17 02:54:54 PM PDT 24
Peak memory 211012 kb
Host smart-a34d50c2-fa0d-487c-a474-44ac39cdb8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642749307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3642749307
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1571965240
Short name T462
Test name
Test status
Simulation time 166600477 ps
CPU time 6.51 seconds
Started Mar 17 02:54:53 PM PDT 24
Finished Mar 17 02:54:59 PM PDT 24
Peak memory 221012 kb
Host smart-6857ba40-41a2-4dd4-be4d-e45dc93e0000
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571965240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1571965240
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2345466770
Short name T305
Test name
Test status
Simulation time 2233214525 ps
CPU time 61.77 seconds
Started Mar 17 02:54:54 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 657484 kb
Host smart-0a3f882d-2c93-414b-ae75-55bc4d9afa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345466770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2345466770
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3290098302
Short name T463
Test name
Test status
Simulation time 8100978757 ps
CPU time 73.74 seconds
Started Mar 17 02:54:53 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 708560 kb
Host smart-aa8b5a7c-e9ea-4075-b088-aa7e60c5699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290098302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3290098302
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1444728125
Short name T980
Test name
Test status
Simulation time 206319252 ps
CPU time 0.92 seconds
Started Mar 17 02:54:54 PM PDT 24
Finished Mar 17 02:54:55 PM PDT 24
Peak memory 202472 kb
Host smart-d6a16868-54a1-45c8-996b-1dbda638ee77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444728125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1444728125
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1882618640
Short name T166
Test name
Test status
Simulation time 758408672 ps
CPU time 4.96 seconds
Started Mar 17 02:54:54 PM PDT 24
Finished Mar 17 02:54:59 PM PDT 24
Peak memory 202684 kb
Host smart-5ae99f64-48ce-4dc6-9a15-f474241bbb79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882618640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1882618640
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2765547222
Short name T382
Test name
Test status
Simulation time 9444733528 ps
CPU time 130.32 seconds
Started Mar 17 02:54:56 PM PDT 24
Finished Mar 17 02:57:06 PM PDT 24
Peak memory 242132 kb
Host smart-c44df2c3-c27d-40ef-91c1-06288049ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765547222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2765547222
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3470876379
Short name T619
Test name
Test status
Simulation time 17788511 ps
CPU time 0.66 seconds
Started Mar 17 02:54:51 PM PDT 24
Finished Mar 17 02:54:52 PM PDT 24
Peak memory 201908 kb
Host smart-277cec43-33bd-4796-a0f5-c38f93bd8bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470876379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3470876379
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.843737956
Short name T179
Test name
Test status
Simulation time 6125945022 ps
CPU time 27.62 seconds
Started Mar 17 02:54:52 PM PDT 24
Finished Mar 17 02:55:20 PM PDT 24
Peak memory 219112 kb
Host smart-8470b57d-af27-417b-9f0f-95545058d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843737956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.843737956
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.4244792899
Short name T375
Test name
Test status
Simulation time 3781405082 ps
CPU time 89.78 seconds
Started Mar 17 02:54:59 PM PDT 24
Finished Mar 17 02:56:29 PM PDT 24
Peak memory 367048 kb
Host smart-a0534598-ee15-4da2-8fbf-107e34a08da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244792899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.4244792899
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.4030281597
Short name T738
Test name
Test status
Simulation time 523564839 ps
CPU time 21.8 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:55:20 PM PDT 24
Peak memory 210828 kb
Host smart-1fdcb95a-e126-4c21-a869-a9e22ce6a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030281597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.4030281597
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3838677029
Short name T401
Test name
Test status
Simulation time 4063334202 ps
CPU time 4.18 seconds
Started Mar 17 02:55:04 PM PDT 24
Finished Mar 17 02:55:09 PM PDT 24
Peak memory 202852 kb
Host smart-2634c2f8-3c7b-4adf-b56c-c5910673d656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838677029 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3838677029
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2227222594
Short name T882
Test name
Test status
Simulation time 10098804052 ps
CPU time 78.02 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 610384 kb
Host smart-1edb5773-1c2c-4af1-8b0f-daef67c824b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227222594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2227222594
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.247104198
Short name T786
Test name
Test status
Simulation time 10087413491 ps
CPU time 16.92 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:55:15 PM PDT 24
Peak memory 370796 kb
Host smart-1be8b3e4-4d2b-456c-8158-bfef6c8efc08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247104198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.247104198
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4162158699
Short name T46
Test name
Test status
Simulation time 669879208 ps
CPU time 1.98 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:54:59 PM PDT 24
Peak memory 202708 kb
Host smart-ca07fbc3-4c7a-454a-9cf0-76b678acee5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162158699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4162158699
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_perf.366611581
Short name T1199
Test name
Test status
Simulation time 692745432 ps
CPU time 4.44 seconds
Started Mar 17 02:54:56 PM PDT 24
Finished Mar 17 02:55:01 PM PDT 24
Peak memory 202708 kb
Host smart-16a8e88e-4b59-4568-af2e-3ae44c046122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366611581 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_perf.366611581
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1691115066
Short name T807
Test name
Test status
Simulation time 1853005025 ps
CPU time 36.87 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:55:34 PM PDT 24
Peak memory 202668 kb
Host smart-2317bc4b-e7a7-4150-944b-a58f3f7d8227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691115066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1691115066
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2508402942
Short name T264
Test name
Test status
Simulation time 31847375868 ps
CPU time 257.2 seconds
Started Mar 17 02:54:53 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 3092232 kb
Host smart-f8ebb00e-94b4-4aab-8e92-cc52226675d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508402942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2508402942
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1276214583
Short name T679
Test name
Test status
Simulation time 9929952775 ps
CPU time 137.79 seconds
Started Mar 17 02:54:53 PM PDT 24
Finished Mar 17 02:57:11 PM PDT 24
Peak memory 736240 kb
Host smart-a41a9bc8-cf9f-4d76-8f06-aba7ca5f311e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276214583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1276214583
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2750851949
Short name T22
Test name
Test status
Simulation time 2932641043 ps
CPU time 6.9 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:55:05 PM PDT 24
Peak memory 202748 kb
Host smart-fd69bbdc-a3d6-4a43-825b-02214ff56bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750851949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2750851949
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.2403961208
Short name T641
Test name
Test status
Simulation time 5177385990 ps
CPU time 6.4 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:55:03 PM PDT 24
Peak memory 206988 kb
Host smart-c0d07eae-f27e-4e35-80eb-a6d90e96fe11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403961208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.2403961208
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3272843118
Short name T1083
Test name
Test status
Simulation time 17763402 ps
CPU time 0.63 seconds
Started Mar 17 02:53:27 PM PDT 24
Finished Mar 17 02:53:28 PM PDT 24
Peak memory 201540 kb
Host smart-408033d8-5df5-4c94-8578-6ae20f45e617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272843118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3272843118
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.435074880
Short name T418
Test name
Test status
Simulation time 47445465 ps
CPU time 2.1 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:36 PM PDT 24
Peak memory 210976 kb
Host smart-b6ba281b-e2e6-4cf4-9cef-191027724600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435074880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.435074880
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1189404454
Short name T1178
Test name
Test status
Simulation time 459566090 ps
CPU time 23.92 seconds
Started Mar 17 02:53:10 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 303548 kb
Host smart-89563f51-94a6-4433-9752-0b9b11dd3ff1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189404454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1189404454
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.942103863
Short name T194
Test name
Test status
Simulation time 12999012297 ps
CPU time 102 seconds
Started Mar 17 02:53:08 PM PDT 24
Finished Mar 17 02:54:50 PM PDT 24
Peak memory 938732 kb
Host smart-585e818d-326e-437a-b151-e205d7782ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942103863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.942103863
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2615035341
Short name T1172
Test name
Test status
Simulation time 2567378712 ps
CPU time 77.28 seconds
Started Mar 17 02:53:10 PM PDT 24
Finished Mar 17 02:54:29 PM PDT 24
Peak memory 740680 kb
Host smart-dd391179-a4c2-4760-95b9-f4bf80a8f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615035341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2615035341
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.922579219
Short name T267
Test name
Test status
Simulation time 405408336 ps
CPU time 1.05 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:53:37 PM PDT 24
Peak memory 202688 kb
Host smart-9275e268-c986-4183-bbeb-879c8b05692c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922579219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.922579219
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3393288269
Short name T569
Test name
Test status
Simulation time 1572570829 ps
CPU time 5.46 seconds
Started Mar 17 02:53:07 PM PDT 24
Finished Mar 17 02:53:13 PM PDT 24
Peak memory 202720 kb
Host smart-adbe213c-edd4-4281-ab2a-2c9217434241
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393288269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3393288269
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2935240436
Short name T871
Test name
Test status
Simulation time 5682635954 ps
CPU time 191.94 seconds
Started Mar 17 02:53:06 PM PDT 24
Finished Mar 17 02:56:18 PM PDT 24
Peak memory 1588696 kb
Host smart-fa1ef868-3e9e-42b1-b19d-1fcb2d632933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935240436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2935240436
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1829037164
Short name T951
Test name
Test status
Simulation time 1514342209 ps
CPU time 29.94 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:54:13 PM PDT 24
Peak memory 259512 kb
Host smart-24d30953-bbd9-4660-be6c-4024b3959e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829037164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1829037164
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1205774687
Short name T364
Test name
Test status
Simulation time 43183006 ps
CPU time 0.6 seconds
Started Mar 17 02:53:19 PM PDT 24
Finished Mar 17 02:53:20 PM PDT 24
Peak memory 201796 kb
Host smart-404d0f33-4066-4a71-b20d-3a1d030eb950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205774687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1205774687
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2634014736
Short name T1101
Test name
Test status
Simulation time 49606508426 ps
CPU time 270.09 seconds
Started Mar 17 02:53:09 PM PDT 24
Finished Mar 17 02:57:39 PM PDT 24
Peak memory 291600 kb
Host smart-aebe88e1-6904-4944-8262-69ca193209f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634014736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2634014736
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.712666985
Short name T328
Test name
Test status
Simulation time 3700976779 ps
CPU time 44.2 seconds
Started Mar 17 02:53:07 PM PDT 24
Finished Mar 17 02:53:51 PM PDT 24
Peak memory 259880 kb
Host smart-cccda001-cb31-466b-922e-41b657c52c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712666985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.712666985
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3201918369
Short name T1246
Test name
Test status
Simulation time 1224082434 ps
CPU time 26.3 seconds
Started Mar 17 02:53:06 PM PDT 24
Finished Mar 17 02:53:33 PM PDT 24
Peak memory 210852 kb
Host smart-6f9c5e6c-a089-45e8-b95e-1c7a03793d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201918369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3201918369
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2666756432
Short name T87
Test name
Test status
Simulation time 367115093 ps
CPU time 0.98 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 221204 kb
Host smart-b838d712-b696-48ec-862e-c1a2202a13c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666756432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2666756432
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1354592621
Short name T1134
Test name
Test status
Simulation time 10059351340 ps
CPU time 95.3 seconds
Started Mar 17 02:53:11 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 746140 kb
Host smart-204a9d45-bffe-4a85-97bc-79410ff27ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354592621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1354592621
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1006446486
Short name T823
Test name
Test status
Simulation time 1256630429 ps
CPU time 5.46 seconds
Started Mar 17 02:53:09 PM PDT 24
Finished Mar 17 02:53:15 PM PDT 24
Peak memory 206660 kb
Host smart-d304c26e-bf32-4522-a6df-4045e7e0a091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006446486 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1006446486
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1110984165
Short name T1251
Test name
Test status
Simulation time 14402308169 ps
CPU time 142.4 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 1983888 kb
Host smart-dba0b802-da3d-45ea-ad57-c9be68ca6071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110984165 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1110984165
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2291049878
Short name T346
Test name
Test status
Simulation time 2424073241 ps
CPU time 3.96 seconds
Started Mar 17 02:53:11 PM PDT 24
Finished Mar 17 02:53:16 PM PDT 24
Peak memory 207308 kb
Host smart-ee620ab6-8071-4f93-9b7c-8d51e09cded7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291049878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2291049878
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.584498762
Short name T184
Test name
Test status
Simulation time 4834897421 ps
CPU time 21.91 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 248780 kb
Host smart-b36db8de-6257-47fd-9313-749647815e1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584498762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_stress_all.584498762
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.4115560768
Short name T506
Test name
Test status
Simulation time 468382068 ps
CPU time 20.35 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:53:54 PM PDT 24
Peak memory 202680 kb
Host smart-151caa23-3254-4ce9-affc-1bbf3cf23bf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115560768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.4115560768
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1445111059
Short name T526
Test name
Test status
Simulation time 12223274295 ps
CPU time 522.54 seconds
Started Mar 17 02:53:07 PM PDT 24
Finished Mar 17 03:01:49 PM PDT 24
Peak memory 3050460 kb
Host smart-ee2a7daf-1cf8-4d7f-bd2a-0fc6ac0420ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445111059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1445111059
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1576689261
Short name T923
Test name
Test status
Simulation time 1797553594 ps
CPU time 7.49 seconds
Started Mar 17 02:53:09 PM PDT 24
Finished Mar 17 02:53:17 PM PDT 24
Peak memory 202660 kb
Host smart-60f07118-3a10-4f42-b14f-6978fe99c130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576689261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1576689261
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.3404844973
Short name T304
Test name
Test status
Simulation time 652822538 ps
CPU time 5.18 seconds
Started Mar 17 02:53:08 PM PDT 24
Finished Mar 17 02:53:13 PM PDT 24
Peak memory 202696 kb
Host smart-c8c61064-a45d-4eab-b005-51505a4dccab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404844973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.3404844973
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2194084165
Short name T863
Test name
Test status
Simulation time 40969241 ps
CPU time 0.61 seconds
Started Mar 17 02:55:06 PM PDT 24
Finished Mar 17 02:55:07 PM PDT 24
Peak memory 201580 kb
Host smart-cdf75b0b-4e77-4a14-a331-0997e8289398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194084165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2194084165
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3284644030
Short name T772
Test name
Test status
Simulation time 38385172 ps
CPU time 1.24 seconds
Started Mar 17 02:55:01 PM PDT 24
Finished Mar 17 02:55:03 PM PDT 24
Peak memory 219060 kb
Host smart-24bf680c-fc5d-4261-8464-2fe5469de781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284644030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3284644030
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2508982188
Short name T1163
Test name
Test status
Simulation time 323516246 ps
CPU time 16.69 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:55:15 PM PDT 24
Peak memory 271772 kb
Host smart-6442a703-d8a9-4e4e-86d6-d31dafd9f41d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508982188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2508982188
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3971687151
Short name T976
Test name
Test status
Simulation time 6167133013 ps
CPU time 50.24 seconds
Started Mar 17 02:55:01 PM PDT 24
Finished Mar 17 02:55:52 PM PDT 24
Peak memory 559228 kb
Host smart-f0eee676-c2c2-4c0b-8118-99c21a6bbeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971687151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3971687151
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1350694851
Short name T494
Test name
Test status
Simulation time 10419764681 ps
CPU time 100.51 seconds
Started Mar 17 02:55:04 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 853676 kb
Host smart-81c881d0-cc56-4b88-9551-3a30f59493f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350694851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1350694851
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.609261811
Short name T430
Test name
Test status
Simulation time 286503885 ps
CPU time 0.83 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:54:59 PM PDT 24
Peak memory 202492 kb
Host smart-ff4cd61d-5301-4a91-9c59-80282d2df28c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609261811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.609261811
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2405321778
Short name T612
Test name
Test status
Simulation time 693398258 ps
CPU time 8.99 seconds
Started Mar 17 02:55:05 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 202708 kb
Host smart-82a7016c-e1f8-4399-a7ee-1f03291cf1a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405321778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2405321778
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2636894790
Short name T826
Test name
Test status
Simulation time 3576763421 ps
CPU time 92.78 seconds
Started Mar 17 02:54:57 PM PDT 24
Finished Mar 17 02:56:31 PM PDT 24
Peak memory 1091340 kb
Host smart-485dc388-6e81-40da-be0d-652259b85dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636894790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2636894790
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.747133994
Short name T279
Test name
Test status
Simulation time 8901447118 ps
CPU time 119 seconds
Started Mar 17 02:55:07 PM PDT 24
Finished Mar 17 02:57:06 PM PDT 24
Peak memory 276052 kb
Host smart-95166788-7277-4a14-8c32-f59829c6fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747133994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.747133994
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1201391070
Short name T521
Test name
Test status
Simulation time 47050347 ps
CPU time 0.64 seconds
Started Mar 17 02:54:58 PM PDT 24
Finished Mar 17 02:54:59 PM PDT 24
Peak memory 201792 kb
Host smart-0f3b6fe4-f61b-4dd7-a7eb-99005028a9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201391070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1201391070
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.61703922
Short name T161
Test name
Test status
Simulation time 28367637853 ps
CPU time 216.46 seconds
Started Mar 17 02:55:02 PM PDT 24
Finished Mar 17 02:58:39 PM PDT 24
Peak memory 211032 kb
Host smart-21221f20-65a7-4059-a7bf-c1bb4f3d8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61703922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.61703922
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.4113622942
Short name T949
Test name
Test status
Simulation time 1975969455 ps
CPU time 107.42 seconds
Started Mar 17 02:54:59 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 235364 kb
Host smart-2519c3ea-1ee7-431d-851e-54f65c9cff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113622942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.4113622942
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.420235622
Short name T195
Test name
Test status
Simulation time 1343402224 ps
CPU time 29.6 seconds
Started Mar 17 02:55:04 PM PDT 24
Finished Mar 17 02:55:34 PM PDT 24
Peak memory 210812 kb
Host smart-8cee5dbf-43a2-440b-a12b-4b5d24b602e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420235622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.420235622
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2698158558
Short name T652
Test name
Test status
Simulation time 1602826186 ps
CPU time 3.93 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 202704 kb
Host smart-66adba01-7d44-438e-9879-5ce3301dc76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698158558 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2698158558
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2854064388
Short name T902
Test name
Test status
Simulation time 10056036733 ps
CPU time 77.55 seconds
Started Mar 17 02:55:01 PM PDT 24
Finished Mar 17 02:56:19 PM PDT 24
Peak memory 544872 kb
Host smart-5058f7a3-3a9f-4929-852d-dde2b18c8ef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854064388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2854064388
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3553965303
Short name T1053
Test name
Test status
Simulation time 11470509786 ps
CPU time 7.06 seconds
Started Mar 17 02:55:07 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 265256 kb
Host smart-96713342-6ba6-49c6-91c5-68bf9d7a8d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553965303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3553965303
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2338258300
Short name T785
Test name
Test status
Simulation time 2390280431 ps
CPU time 2.66 seconds
Started Mar 17 02:55:06 PM PDT 24
Finished Mar 17 02:55:09 PM PDT 24
Peak memory 202796 kb
Host smart-6d6bb163-71cd-44c6-b9f8-9336f485de3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338258300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2338258300
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3151759634
Short name T503
Test name
Test status
Simulation time 4868284740 ps
CPU time 4.27 seconds
Started Mar 17 02:55:05 PM PDT 24
Finished Mar 17 02:55:10 PM PDT 24
Peak memory 202796 kb
Host smart-890e635a-32b7-40cc-926b-07e1717c096f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151759634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3151759634
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_perf.1991216768
Short name T906
Test name
Test status
Simulation time 818354339 ps
CPU time 4.38 seconds
Started Mar 17 02:55:05 PM PDT 24
Finished Mar 17 02:55:09 PM PDT 24
Peak memory 206060 kb
Host smart-453a0a9f-b516-415c-9f9a-08052cbb192c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991216768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.1991216768
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.573681962
Short name T1056
Test name
Test status
Simulation time 25582844954 ps
CPU time 40.92 seconds
Started Mar 17 02:55:07 PM PDT 24
Finished Mar 17 02:55:48 PM PDT 24
Peak memory 765552 kb
Host smart-d09a2b2b-9117-4f4d-9542-f44cf7ad7241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573681962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.573681962
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.4101620845
Short name T855
Test name
Test status
Simulation time 8508635123 ps
CPU time 300.29 seconds
Started Mar 17 02:55:01 PM PDT 24
Finished Mar 17 03:00:02 PM PDT 24
Peak memory 2131496 kb
Host smart-3371842e-3ca3-46d3-97bf-af5688a3d9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101620845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.4101620845
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1501970786
Short name T1054
Test name
Test status
Simulation time 6206489486 ps
CPU time 7.24 seconds
Started Mar 17 02:55:05 PM PDT 24
Finished Mar 17 02:55:13 PM PDT 24
Peak memory 207516 kb
Host smart-dc2ba7c8-6fc1-4f1e-85b4-edc4668e8518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501970786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1501970786
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.70956472
Short name T1209
Test name
Test status
Simulation time 1425194598 ps
CPU time 7.79 seconds
Started Mar 17 02:55:07 PM PDT 24
Finished Mar 17 02:55:15 PM PDT 24
Peak memory 202728 kb
Host smart-ff7b3e92-b43a-4a3d-aa59-6424e01c25b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70956472 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_unexp_stop.70956472
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2934506086
Short name T791
Test name
Test status
Simulation time 22315570 ps
CPU time 0.59 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:21 PM PDT 24
Peak memory 201388 kb
Host smart-0b2f83c4-f050-4eec-868f-35399438690d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934506086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2934506086
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1803850717
Short name T937
Test name
Test status
Simulation time 119512541 ps
CPU time 1.53 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:55:12 PM PDT 24
Peak memory 211056 kb
Host smart-1020b682-cd94-4ea7-b3a6-7b9840274c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803850717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1803850717
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.661749383
Short name T989
Test name
Test status
Simulation time 1706976368 ps
CPU time 7.83 seconds
Started Mar 17 02:55:08 PM PDT 24
Finished Mar 17 02:55:16 PM PDT 24
Peak memory 299072 kb
Host smart-c45d054b-3562-44db-9ad9-37f02624d3d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661749383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.661749383
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.378428956
Short name T699
Test name
Test status
Simulation time 8923994912 ps
CPU time 168.97 seconds
Started Mar 17 02:55:09 PM PDT 24
Finished Mar 17 02:57:58 PM PDT 24
Peak memory 759276 kb
Host smart-f74287d1-17a0-4a16-ad01-fd0beced2a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378428956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.378428956
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.201765238
Short name T299
Test name
Test status
Simulation time 12654644329 ps
CPU time 59.15 seconds
Started Mar 17 02:55:08 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 676688 kb
Host smart-5f1ffbed-7629-4b4e-9763-5c658a0f2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201765238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.201765238
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4120355903
Short name T1133
Test name
Test status
Simulation time 494725965 ps
CPU time 1.02 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:55:11 PM PDT 24
Peak memory 202384 kb
Host smart-3023d97b-01f5-4eea-87e0-6f37865a2890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120355903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4120355903
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2485951643
Short name T402
Test name
Test status
Simulation time 1063997096 ps
CPU time 4.77 seconds
Started Mar 17 02:55:06 PM PDT 24
Finished Mar 17 02:55:11 PM PDT 24
Peak memory 229596 kb
Host smart-21b9a617-d476-4e7e-a9a2-ce8ee1642a90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485951643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2485951643
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.951253554
Short name T251
Test name
Test status
Simulation time 4091064776 ps
CPU time 297.95 seconds
Started Mar 17 02:55:09 PM PDT 24
Finished Mar 17 03:00:07 PM PDT 24
Peak memory 1136000 kb
Host smart-e02dc8c0-aa0f-4298-a864-cd7301ed8eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951253554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.951253554
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3826678308
Short name T523
Test name
Test status
Simulation time 17577691901 ps
CPU time 52.56 seconds
Started Mar 17 02:55:15 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 296940 kb
Host smart-0e770755-8cf7-42b3-802b-c33a389d423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826678308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3826678308
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.620035417
Short name T153
Test name
Test status
Simulation time 78143630 ps
CPU time 0.63 seconds
Started Mar 17 02:55:08 PM PDT 24
Finished Mar 17 02:55:09 PM PDT 24
Peak memory 201880 kb
Host smart-ff834ef8-34d3-44d5-9391-bdd4d6b35f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620035417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.620035417
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3240095615
Short name T987
Test name
Test status
Simulation time 1543393417 ps
CPU time 82.61 seconds
Started Mar 17 02:55:09 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 247192 kb
Host smart-758c2422-66c6-4774-a1ac-4d25520f57b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240095615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3240095615
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3657080411
Short name T295
Test name
Test status
Simulation time 3481507579 ps
CPU time 11.84 seconds
Started Mar 17 02:55:05 PM PDT 24
Finished Mar 17 02:55:18 PM PDT 24
Peak memory 219104 kb
Host smart-cb9d1b24-3abb-4918-9dca-032138690668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657080411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3657080411
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2922895244
Short name T458
Test name
Test status
Simulation time 6297284997 ps
CPU time 4.02 seconds
Started Mar 17 02:55:14 PM PDT 24
Finished Mar 17 02:55:19 PM PDT 24
Peak memory 202844 kb
Host smart-75f6740f-f9f0-41d2-9e65-d2cddf3f3ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922895244 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2922895244
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.765566155
Short name T1233
Test name
Test status
Simulation time 10091091829 ps
CPU time 92.61 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:56:43 PM PDT 24
Peak memory 683728 kb
Host smart-4a36be76-35f8-4892-88e8-eac1e2ce42b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765566155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.765566155
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3504385827
Short name T797
Test name
Test status
Simulation time 1390220565 ps
CPU time 2.35 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:23 PM PDT 24
Peak memory 202688 kb
Host smart-ec85ed32-f8c9-4bd3-a7a8-2a5dfebc639f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504385827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3504385827
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2107336897
Short name T314
Test name
Test status
Simulation time 1441532359 ps
CPU time 7.45 seconds
Started Mar 17 02:55:11 PM PDT 24
Finished Mar 17 02:55:18 PM PDT 24
Peak memory 215836 kb
Host smart-52984d15-4195-487d-b10e-c0c7f008a591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107336897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2107336897
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3958372968
Short name T822
Test name
Test status
Simulation time 3504836780 ps
CPU time 2.82 seconds
Started Mar 17 02:55:13 PM PDT 24
Finished Mar 17 02:55:17 PM PDT 24
Peak memory 202760 kb
Host smart-eccfb38e-f04d-466b-9cfa-56e1de28a85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958372968 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3958372968
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3470197758
Short name T761
Test name
Test status
Simulation time 1467846560 ps
CPU time 4.85 seconds
Started Mar 17 02:55:13 PM PDT 24
Finished Mar 17 02:55:19 PM PDT 24
Peak memory 208908 kb
Host smart-be04bafa-c8de-4518-8fc5-ccbe88d5c33e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470197758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3470197758
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1577261423
Short name T642
Test name
Test status
Simulation time 361176213 ps
CPU time 6.55 seconds
Started Mar 17 02:55:09 PM PDT 24
Finished Mar 17 02:55:16 PM PDT 24
Peak memory 202680 kb
Host smart-ab06d619-d9ef-4c32-902f-a30dc03b24c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577261423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1577261423
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4268286296
Short name T93
Test name
Test status
Simulation time 37896976162 ps
CPU time 69.16 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:56:19 PM PDT 24
Peak memory 1319048 kb
Host smart-97b2f522-2413-4176-8490-7dac7000830f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268286296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4268286296
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3984475678
Short name T659
Test name
Test status
Simulation time 37041979183 ps
CPU time 46.25 seconds
Started Mar 17 02:55:10 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 505552 kb
Host smart-390ba515-6131-4c0f-83e4-a5cd98a029d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984475678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3984475678
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2974311292
Short name T690
Test name
Test status
Simulation time 17950259799 ps
CPU time 6.8 seconds
Started Mar 17 02:55:12 PM PDT 24
Finished Mar 17 02:55:19 PM PDT 24
Peak memory 208164 kb
Host smart-42d4fdd1-28d7-4d4e-8ecd-fa9b247d1074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974311292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2974311292
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.2759868801
Short name T1015
Test name
Test status
Simulation time 811658387 ps
CPU time 4.31 seconds
Started Mar 17 02:55:09 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 202784 kb
Host smart-fcfcfae7-3063-4285-8aaa-2850f8a43df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759868801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.2759868801
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3884307575
Short name T74
Test name
Test status
Simulation time 27504823 ps
CPU time 0.62 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:55:24 PM PDT 24
Peak memory 201648 kb
Host smart-a6249d23-006a-4c34-a352-e26222d3e5bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884307575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3884307575
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1299054147
Short name T361
Test name
Test status
Simulation time 89508302 ps
CPU time 1.6 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:23 PM PDT 24
Peak memory 210988 kb
Host smart-1c892f64-4e5b-46ab-91ac-de504a271762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299054147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1299054147
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.4059623134
Short name T729
Test name
Test status
Simulation time 500979924 ps
CPU time 9.31 seconds
Started Mar 17 02:55:19 PM PDT 24
Finished Mar 17 02:55:28 PM PDT 24
Peak memory 313708 kb
Host smart-48faa462-e5d0-4a54-805d-7e66167d0b60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059623134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.4059623134
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3911401314
Short name T240
Test name
Test status
Simulation time 2275565784 ps
CPU time 59.21 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:56:20 PM PDT 24
Peak memory 588500 kb
Host smart-52a13aab-a7b9-4f1a-b880-412a870a9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911401314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3911401314
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2048740195
Short name T694
Test name
Test status
Simulation time 2703090401 ps
CPU time 89.37 seconds
Started Mar 17 02:55:17 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 848684 kb
Host smart-b021d039-ad1d-4fa0-8083-c022cc67a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048740195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2048740195
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.1556006828
Short name T760
Test name
Test status
Simulation time 127378146 ps
CPU time 1.08 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:22 PM PDT 24
Peak memory 202716 kb
Host smart-ea717db6-9914-42a4-93a8-c31b6962789f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556006828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.1556006828
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3611426145
Short name T959
Test name
Test status
Simulation time 258313375 ps
CPU time 3.89 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:55:24 PM PDT 24
Peak memory 223548 kb
Host smart-5ab707c1-f551-4451-8607-7f0f54f84bf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611426145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3611426145
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3650440916
Short name T881
Test name
Test status
Simulation time 9757318441 ps
CPU time 77.7 seconds
Started Mar 17 02:55:25 PM PDT 24
Finished Mar 17 02:56:43 PM PDT 24
Peak memory 313372 kb
Host smart-78094f73-ed94-4bee-9a7c-d516e2a556b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650440916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3650440916
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.404322033
Short name T4
Test name
Test status
Simulation time 52183498 ps
CPU time 0.65 seconds
Started Mar 17 02:55:16 PM PDT 24
Finished Mar 17 02:55:17 PM PDT 24
Peak memory 201816 kb
Host smart-54b6fb94-5685-4d30-a7ef-bd46d6749b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404322033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.404322033
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3558568589
Short name T1031
Test name
Test status
Simulation time 29313537885 ps
CPU time 636.12 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 03:05:56 PM PDT 24
Peak memory 210944 kb
Host smart-163f6649-4c28-403f-b6c1-f1c7d3d87438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558568589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3558568589
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3885660941
Short name T472
Test name
Test status
Simulation time 2246056587 ps
CPU time 26.49 seconds
Started Mar 17 02:55:14 PM PDT 24
Finished Mar 17 02:55:42 PM PDT 24
Peak memory 251072 kb
Host smart-040baf63-bc11-4234-b1ee-454fbabf7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885660941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3885660941
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1169341332
Short name T1151
Test name
Test status
Simulation time 64427692156 ps
CPU time 1528.86 seconds
Started Mar 17 02:55:17 PM PDT 24
Finished Mar 17 03:20:47 PM PDT 24
Peak memory 2865624 kb
Host smart-4bdf592e-adcd-47a0-85c7-343cf273ecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169341332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1169341332
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.746995607
Short name T968
Test name
Test status
Simulation time 974300248 ps
CPU time 17.01 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:55:37 PM PDT 24
Peak memory 213656 kb
Host smart-f479ff57-1e39-431d-9aa9-3edb51246156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746995607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.746995607
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2172294751
Short name T715
Test name
Test status
Simulation time 1057429835 ps
CPU time 4.34 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:25 PM PDT 24
Peak memory 202812 kb
Host smart-a3871deb-7588-4be0-b35a-7ed8fdf329f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172294751 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2172294751
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.333602176
Short name T1208
Test name
Test status
Simulation time 10091528864 ps
CPU time 72.05 seconds
Started Mar 17 02:55:19 PM PDT 24
Finished Mar 17 02:56:31 PM PDT 24
Peak memory 573692 kb
Host smart-6f990298-5821-415c-9de8-220759abedee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333602176 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.333602176
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.250708644
Short name T1081
Test name
Test status
Simulation time 10585959475 ps
CPU time 12.01 seconds
Started Mar 17 02:55:18 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 302116 kb
Host smart-4a55185f-b535-4750-ad0f-77807ed5b118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250708644 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.250708644
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2575906656
Short name T1180
Test name
Test status
Simulation time 423954656 ps
CPU time 2.41 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:55:23 PM PDT 24
Peak memory 202952 kb
Host smart-0ad57f8b-7722-4523-904c-c7441652737d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575906656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2575906656
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.55947527
Short name T445
Test name
Test status
Simulation time 9745241564 ps
CPU time 5.68 seconds
Started Mar 17 02:55:22 PM PDT 24
Finished Mar 17 02:55:28 PM PDT 24
Peak memory 202764 kb
Host smart-6ef19ce1-1780-4a33-86d7-6b22167c7ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55947527 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.55947527
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3155947171
Short name T289
Test name
Test status
Simulation time 14316825966 ps
CPU time 51.95 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:56:12 PM PDT 24
Peak memory 1005172 kb
Host smart-6a846e1a-4e06-415b-9011-06ee2a04406d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155947171 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3155947171
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.893043242
Short name T550
Test name
Test status
Simulation time 4798955541 ps
CPU time 4.8 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:26 PM PDT 24
Peak memory 202736 kb
Host smart-232e7d02-86c5-490b-a7fd-8e2fd8725277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893043242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_perf.893043242
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.734870440
Short name T1188
Test name
Test status
Simulation time 6832429674 ps
CPU time 30.38 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:51 PM PDT 24
Peak memory 219116 kb
Host smart-b3746dcf-ef89-4d9b-90fb-6971fd8a33df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734870440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_target_stress_all.734870440
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1988475457
Short name T324
Test name
Test status
Simulation time 656155207 ps
CPU time 26.23 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:49 PM PDT 24
Peak memory 202644 kb
Host smart-79b0ac9d-d2d5-4c38-981b-07c9331666d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988475457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1988475457
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3973730478
Short name T490
Test name
Test status
Simulation time 17965355722 ps
CPU time 6.38 seconds
Started Mar 17 02:55:21 PM PDT 24
Finished Mar 17 02:55:28 PM PDT 24
Peak memory 202800 kb
Host smart-e4482774-ecfe-4001-89ee-edcde1e2767d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973730478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3973730478
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2374777863
Short name T1218
Test name
Test status
Simulation time 13456879454 ps
CPU time 58.83 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:56:22 PM PDT 24
Peak memory 799908 kb
Host smart-b7c6385d-a5a5-4f1e-803d-804787fbe11a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374777863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2374777863
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1757564657
Short name T513
Test name
Test status
Simulation time 7674819191 ps
CPU time 8.8 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:32 PM PDT 24
Peak memory 214508 kb
Host smart-363b267e-dc24-4e7f-8e18-345ff757a03a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757564657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1757564657
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.3695830887
Short name T997
Test name
Test status
Simulation time 4653295799 ps
CPU time 6.94 seconds
Started Mar 17 02:55:20 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 212940 kb
Host smart-51765006-55af-4783-823d-680bdb0e9e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695830887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.3695830887
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2724872295
Short name T981
Test name
Test status
Simulation time 16288081 ps
CPU time 0.6 seconds
Started Mar 17 02:55:28 PM PDT 24
Finished Mar 17 02:55:29 PM PDT 24
Peak memory 201656 kb
Host smart-04275613-7906-45be-afa1-9a6cd8c0db14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724872295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2724872295
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.31891424
Short name T507
Test name
Test status
Simulation time 108944885 ps
CPU time 1.45 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:24 PM PDT 24
Peak memory 210960 kb
Host smart-f3f8295d-3354-42c0-b2fd-14790725f0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31891424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.31891424
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2079631499
Short name T872
Test name
Test status
Simulation time 442316152 ps
CPU time 8.45 seconds
Started Mar 17 02:55:22 PM PDT 24
Finished Mar 17 02:55:31 PM PDT 24
Peak memory 297380 kb
Host smart-0aec25cf-858f-4c50-85af-24e951f3aa0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079631499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2079631499
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.4251368485
Short name T854
Test name
Test status
Simulation time 2792738565 ps
CPU time 92.45 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:56:56 PM PDT 24
Peak memory 898032 kb
Host smart-1c1977d0-d0e7-4052-9968-09e6ba0496c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251368485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.4251368485
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3868360947
Short name T1109
Test name
Test status
Simulation time 4027951967 ps
CPU time 41.85 seconds
Started Mar 17 02:55:26 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 531288 kb
Host smart-6c930f7c-72e5-4187-8b0d-0b2dcfd59e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868360947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3868360947
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3414262448
Short name T870
Test name
Test status
Simulation time 285565125 ps
CPU time 0.85 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:55:25 PM PDT 24
Peak memory 202404 kb
Host smart-da3ab509-d80f-472f-845d-f70c67630a3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414262448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3414262448
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2942224719
Short name T306
Test name
Test status
Simulation time 166850907 ps
CPU time 4.05 seconds
Started Mar 17 02:55:25 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 231228 kb
Host smart-f6890752-2cfe-4885-9101-55e376f2ddc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942224719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2942224719
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1542819614
Short name T1039
Test name
Test status
Simulation time 6287653993 ps
CPU time 216.3 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:59:01 PM PDT 24
Peak memory 1733124 kb
Host smart-3fc04822-ece7-4cd0-8d04-21403321796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542819614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1542819614
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3546054875
Short name T1164
Test name
Test status
Simulation time 2199235416 ps
CPU time 191.02 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 02:58:40 PM PDT 24
Peak memory 346176 kb
Host smart-d09718d2-4da9-4092-a91c-f5162410db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546054875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3546054875
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.755385416
Short name T533
Test name
Test status
Simulation time 23773279 ps
CPU time 0.61 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:23 PM PDT 24
Peak memory 201936 kb
Host smart-5decb948-81c2-4d3e-b077-f990ca9fdcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755385416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.755385416
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1218823041
Short name T316
Test name
Test status
Simulation time 3087803854 ps
CPU time 30.37 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:54 PM PDT 24
Peak memory 218300 kb
Host smart-f71b6903-5f0e-4a83-868d-0c5248e047e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218823041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1218823041
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3225895930
Short name T812
Test name
Test status
Simulation time 7328685152 ps
CPU time 42.95 seconds
Started Mar 17 02:55:22 PM PDT 24
Finished Mar 17 02:56:05 PM PDT 24
Peak memory 259696 kb
Host smart-1284c992-cc98-4905-a4cd-2352d2f3504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225895930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3225895930
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1505402656
Short name T30
Test name
Test status
Simulation time 38972393955 ps
CPU time 677.16 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 03:06:41 PM PDT 24
Peak memory 1483380 kb
Host smart-0e42f758-24e1-4a39-8fbc-66077d619fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505402656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1505402656
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1855360635
Short name T522
Test name
Test status
Simulation time 739632801 ps
CPU time 33.77 seconds
Started Mar 17 02:55:25 PM PDT 24
Finished Mar 17 02:55:59 PM PDT 24
Peak memory 210856 kb
Host smart-163994ba-7a1d-45d5-9512-f5ef133431a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855360635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1855360635
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.4160281984
Short name T707
Test name
Test status
Simulation time 10072155981 ps
CPU time 76.34 seconds
Started Mar 17 02:55:22 PM PDT 24
Finished Mar 17 02:56:39 PM PDT 24
Peak memory 576144 kb
Host smart-1e4d6422-d071-47d4-a5f3-2e3de1f5f02c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160281984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.4160281984
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4275431875
Short name T782
Test name
Test status
Simulation time 10070544821 ps
CPU time 87.61 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 02:56:57 PM PDT 24
Peak memory 658880 kb
Host smart-1ef9f93a-3ead-4c3d-a7e9-a36fbedfad21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275431875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4275431875
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.69338414
Short name T495
Test name
Test status
Simulation time 395415942 ps
CPU time 2.25 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 02:55:31 PM PDT 24
Peak memory 202796 kb
Host smart-c4f45e53-a10a-4ebd-a9c1-92cc6a8d12ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69338414 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.i2c_target_hrst.69338414
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3282727341
Short name T1001
Test name
Test status
Simulation time 4420084080 ps
CPU time 3.5 seconds
Started Mar 17 02:55:23 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 202716 kb
Host smart-ee6f99e9-75cc-4d77-ac87-298d2bdb5307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282727341 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3282727341
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.4180154272
Short name T437
Test name
Test status
Simulation time 17379512427 ps
CPU time 236.93 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:59:21 PM PDT 24
Peak memory 2595580 kb
Host smart-b572fab9-ce65-4a25-a6b0-8717a2b49bc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180154272 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.4180154272
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3777412237
Short name T746
Test name
Test status
Simulation time 1712262062 ps
CPU time 4.44 seconds
Started Mar 17 02:55:28 PM PDT 24
Finished Mar 17 02:55:33 PM PDT 24
Peak memory 208992 kb
Host smart-b7a01303-9d9e-4e07-afed-3fc914b09dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777412237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3777412237
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.3631106289
Short name T23
Test name
Test status
Simulation time 7675292575 ps
CPU time 40.82 seconds
Started Mar 17 02:55:26 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 221448 kb
Host smart-148ed212-1b6b-4381-a699-5e635c3b34f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631106289 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.3631106289
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4039137555
Short name T962
Test name
Test status
Simulation time 59631016431 ps
CPU time 2125.74 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 03:30:50 PM PDT 24
Peak memory 10056680 kb
Host smart-5b13b24a-9921-4d72-ac60-c49044d9bca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039137555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4039137555
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3039577306
Short name T1025
Test name
Test status
Simulation time 37698669024 ps
CPU time 254.12 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:59:38 PM PDT 24
Peak memory 1985872 kb
Host smart-192dc7e2-38a4-436a-ad3b-90b26d2a5786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039577306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3039577306
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3135548252
Short name T99
Test name
Test status
Simulation time 5339768345 ps
CPU time 6.58 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:55:31 PM PDT 24
Peak memory 202756 kb
Host smart-fc509258-2a08-4ffb-82a9-cf80ada53b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135548252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3135548252
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.2939822138
Short name T794
Test name
Test status
Simulation time 5892678205 ps
CPU time 6.62 seconds
Started Mar 17 02:55:24 PM PDT 24
Finished Mar 17 02:55:31 PM PDT 24
Peak memory 209568 kb
Host smart-67e73b2d-1799-4d60-ab89-1284cd9860f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939822138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.2939822138
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2399551751
Short name T1116
Test name
Test status
Simulation time 16171209 ps
CPU time 0.63 seconds
Started Mar 17 02:55:36 PM PDT 24
Finished Mar 17 02:55:36 PM PDT 24
Peak memory 201648 kb
Host smart-df98b7e6-a7de-4410-9f72-f0e258d76743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399551751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2399551751
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.600362509
Short name T38
Test name
Test status
Simulation time 41317079 ps
CPU time 1.15 seconds
Started Mar 17 02:55:32 PM PDT 24
Finished Mar 17 02:55:34 PM PDT 24
Peak memory 211016 kb
Host smart-7bd19ae7-a9c1-4808-91cc-6af1f550f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600362509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.600362509
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2483369003
Short name T222
Test name
Test status
Simulation time 4542851280 ps
CPU time 6.6 seconds
Started Mar 17 02:55:27 PM PDT 24
Finished Mar 17 02:55:34 PM PDT 24
Peak memory 262468 kb
Host smart-e4b21049-5f7b-478c-8c53-bb5597752506
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483369003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2483369003
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2265348168
Short name T654
Test name
Test status
Simulation time 2576110951 ps
CPU time 179.25 seconds
Started Mar 17 02:55:30 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 727896 kb
Host smart-0970d4b0-6b18-44a7-99f9-f7ad07791327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265348168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2265348168
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3692380053
Short name T1236
Test name
Test status
Simulation time 2889603200 ps
CPU time 236.3 seconds
Started Mar 17 02:55:28 PM PDT 24
Finished Mar 17 02:59:24 PM PDT 24
Peak memory 891468 kb
Host smart-63c74a2e-64b5-44cc-a570-672a40b19499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692380053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3692380053
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1471262685
Short name T398
Test name
Test status
Simulation time 276762589 ps
CPU time 1.03 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 202492 kb
Host smart-4cedc17e-fd0e-4307-98e3-b72b39e1826f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471262685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1471262685
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1502835104
Short name T554
Test name
Test status
Simulation time 289930038 ps
CPU time 7.68 seconds
Started Mar 17 02:55:27 PM PDT 24
Finished Mar 17 02:55:35 PM PDT 24
Peak memory 202744 kb
Host smart-488e3c52-38c0-4bb5-93ae-9637f4244df3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502835104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1502835104
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1141337031
Short name T920
Test name
Test status
Simulation time 19721156610 ps
CPU time 385.83 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 03:01:55 PM PDT 24
Peak memory 1283720 kb
Host smart-585bde38-ab81-4ca3-81a3-9c9092cef7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141337031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1141337031
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3713837897
Short name T12
Test name
Test status
Simulation time 4885949795 ps
CPU time 226.06 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:59:26 PM PDT 24
Peak memory 359644 kb
Host smart-1c4e87d2-d9db-4408-ba8e-581b6ad40898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713837897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3713837897
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2147596481
Short name T420
Test name
Test status
Simulation time 43942224 ps
CPU time 0.62 seconds
Started Mar 17 02:55:29 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 201796 kb
Host smart-6f9a0625-14ab-4e85-afcb-ef21763ddc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147596481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2147596481
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2955265297
Short name T89
Test name
Test status
Simulation time 16322337351 ps
CPU time 101.31 seconds
Started Mar 17 02:55:35 PM PDT 24
Finished Mar 17 02:57:17 PM PDT 24
Peak memory 202740 kb
Host smart-ecc75d78-5a6a-4e9f-ac44-28e4c1c547bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955265297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2955265297
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3294770325
Short name T243
Test name
Test status
Simulation time 11742981089 ps
CPU time 107.1 seconds
Started Mar 17 02:55:31 PM PDT 24
Finished Mar 17 02:57:18 PM PDT 24
Peak memory 226808 kb
Host smart-9e727204-51c5-4ce6-a35e-66431ca53a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294770325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3294770325
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1521577417
Short name T972
Test name
Test status
Simulation time 970643597 ps
CPU time 16.29 seconds
Started Mar 17 02:55:32 PM PDT 24
Finished Mar 17 02:55:49 PM PDT 24
Peak memory 219148 kb
Host smart-c9bd993b-16c8-41be-b450-b252fea91fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521577417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1521577417
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.40034362
Short name T168
Test name
Test status
Simulation time 10319448792 ps
CPU time 27.48 seconds
Started Mar 17 02:55:32 PM PDT 24
Finished Mar 17 02:56:00 PM PDT 24
Peak memory 371888 kb
Host smart-b0bf2001-d9de-4a9d-be3f-aff3caf84574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40034362 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_acq.40034362
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2275061898
Short name T1118
Test name
Test status
Simulation time 2599268494 ps
CPU time 2.23 seconds
Started Mar 17 02:55:39 PM PDT 24
Finished Mar 17 02:55:41 PM PDT 24
Peak memory 202828 kb
Host smart-ae1d987d-9f45-4c00-8074-bfded45c34e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275061898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2275061898
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1283716465
Short name T844
Test name
Test status
Simulation time 5141660439 ps
CPU time 5.99 seconds
Started Mar 17 02:55:33 PM PDT 24
Finished Mar 17 02:55:39 PM PDT 24
Peak memory 202796 kb
Host smart-bb30b63b-5eee-4085-8e6d-ac1b84c3d282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283716465 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1283716465
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1919033593
Short name T1011
Test name
Test status
Simulation time 5714603686 ps
CPU time 6.87 seconds
Started Mar 17 02:55:31 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 202760 kb
Host smart-e8a29210-a01b-42b2-8e19-29f16a1c2965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919033593 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1919033593
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2161536459
Short name T865
Test name
Test status
Simulation time 1457092218 ps
CPU time 3.64 seconds
Started Mar 17 02:55:34 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 204684 kb
Host smart-37ad7524-566b-4cf3-bc9c-1f611c021684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161536459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2161536459
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2311584767
Short name T835
Test name
Test status
Simulation time 2080010881 ps
CPU time 42.14 seconds
Started Mar 17 02:55:34 PM PDT 24
Finished Mar 17 02:56:17 PM PDT 24
Peak memory 202700 kb
Host smart-03a2a649-e88e-4074-a509-645061cb2dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311584767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2311584767
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3630887112
Short name T290
Test name
Test status
Simulation time 1121963026 ps
CPU time 22.36 seconds
Started Mar 17 02:55:36 PM PDT 24
Finished Mar 17 02:55:59 PM PDT 24
Peak memory 202664 kb
Host smart-5989a3db-a31c-4768-8d57-2bc3ddcc0e61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630887112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3630887112
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1590672900
Short name T143
Test name
Test status
Simulation time 59186449749 ps
CPU time 24.06 seconds
Started Mar 17 02:55:37 PM PDT 24
Finished Mar 17 02:56:01 PM PDT 24
Peak memory 500816 kb
Host smart-c9cacdd5-82e8-4bcc-bd76-4f73e052e09e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590672900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1590672900
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.977838959
Short name T386
Test name
Test status
Simulation time 37886929886 ps
CPU time 2566.86 seconds
Started Mar 17 02:55:31 PM PDT 24
Finished Mar 17 03:38:18 PM PDT 24
Peak memory 4377196 kb
Host smart-4e91875a-6ef6-4de2-aae4-32a3db4a4f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977838959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.977838959
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.42267911
Short name T667
Test name
Test status
Simulation time 5274354680 ps
CPU time 5.53 seconds
Started Mar 17 02:55:33 PM PDT 24
Finished Mar 17 02:55:39 PM PDT 24
Peak memory 202776 kb
Host smart-c8485603-5899-43d9-b73b-3615cb98b5ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267911 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_unexp_stop.42267911
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1254555100
Short name T367
Test name
Test status
Simulation time 35779256 ps
CPU time 0.57 seconds
Started Mar 17 02:55:47 PM PDT 24
Finished Mar 17 02:55:47 PM PDT 24
Peak memory 201600 kb
Host smart-e056d996-dc74-4fce-b241-fb2874a6e65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254555100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1254555100
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2233157755
Short name T631
Test name
Test status
Simulation time 136226772 ps
CPU time 1.78 seconds
Started Mar 17 02:55:42 PM PDT 24
Finished Mar 17 02:55:44 PM PDT 24
Peak memory 210996 kb
Host smart-0ff894ee-3b3f-46a8-b1bd-cccfdd417e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233157755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2233157755
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.68827283
Short name T735
Test name
Test status
Simulation time 726303192 ps
CPU time 8.06 seconds
Started Mar 17 02:55:43 PM PDT 24
Finished Mar 17 02:55:51 PM PDT 24
Peak memory 270068 kb
Host smart-860b8d96-afd6-40d2-93cb-ba4c174c422c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68827283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty
.68827283
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.435865134
Short name T459
Test name
Test status
Simulation time 5665746255 ps
CPU time 100.55 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:57:21 PM PDT 24
Peak memory 519836 kb
Host smart-f31fc3df-808c-49f7-b2cb-8d0f6526456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435865134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.435865134
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.540356431
Short name T10
Test name
Test status
Simulation time 320430546 ps
CPU time 0.9 seconds
Started Mar 17 02:55:37 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 202108 kb
Host smart-5699f30d-1c88-455a-8efd-6aab6f22cf64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540356431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.540356431
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.653337165
Short name T1158
Test name
Test status
Simulation time 640033438 ps
CPU time 3.6 seconds
Started Mar 17 02:55:41 PM PDT 24
Finished Mar 17 02:55:44 PM PDT 24
Peak memory 202752 kb
Host smart-30af6415-fc73-406c-9f70-999ae9de4fce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653337165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
653337165
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3532858916
Short name T210
Test name
Test status
Simulation time 3679255623 ps
CPU time 101.56 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:57:22 PM PDT 24
Peak memory 1062228 kb
Host smart-79f5c146-fe61-411f-8e6d-0f8fe845108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532858916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3532858916
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1538447233
Short name T687
Test name
Test status
Simulation time 5863584324 ps
CPU time 33.21 seconds
Started Mar 17 02:55:46 PM PDT 24
Finished Mar 17 02:56:19 PM PDT 24
Peak memory 268452 kb
Host smart-74021a31-dcac-46e6-91ac-9db675bd5a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538447233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1538447233
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2166627892
Short name T144
Test name
Test status
Simulation time 88967673 ps
CPU time 0.63 seconds
Started Mar 17 02:55:37 PM PDT 24
Finished Mar 17 02:55:38 PM PDT 24
Peak memory 201872 kb
Host smart-e5b15e09-4d23-4d84-adee-65cb5b332875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166627892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2166627892
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.58770599
Short name T1096
Test name
Test status
Simulation time 12334687880 ps
CPU time 236.24 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:59:36 PM PDT 24
Peak memory 348136 kb
Host smart-c5eb6ad0-3c55-4e83-83ff-d7d23e0990c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58770599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.58770599
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2042858877
Short name T801
Test name
Test status
Simulation time 2334364486 ps
CPU time 66.29 seconds
Started Mar 17 02:55:39 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 319560 kb
Host smart-ff2505b2-4b70-447f-8dbc-9ab2a6cc5390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042858877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2042858877
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1679323575
Short name T280
Test name
Test status
Simulation time 465117590 ps
CPU time 20.68 seconds
Started Mar 17 02:55:43 PM PDT 24
Finished Mar 17 02:56:03 PM PDT 24
Peak memory 210912 kb
Host smart-e3731d66-7c80-4537-afba-a3a31a4c108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679323575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1679323575
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.595194209
Short name T572
Test name
Test status
Simulation time 1716640488 ps
CPU time 3.81 seconds
Started Mar 17 02:55:46 PM PDT 24
Finished Mar 17 02:55:50 PM PDT 24
Peak memory 202696 kb
Host smart-bd5674d6-22f0-473f-9bec-17980e3a73bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595194209 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.595194209
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1807509630
Short name T19
Test name
Test status
Simulation time 10116045822 ps
CPU time 96.35 seconds
Started Mar 17 02:55:47 PM PDT 24
Finished Mar 17 02:57:23 PM PDT 24
Peak memory 756084 kb
Host smart-58760885-12d3-4962-9b30-1421e1bc87e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807509630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1807509630
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.60720236
Short name T857
Test name
Test status
Simulation time 11368869899 ps
CPU time 11.39 seconds
Started Mar 17 02:55:47 PM PDT 24
Finished Mar 17 02:55:58 PM PDT 24
Peak memory 332788 kb
Host smart-ca09c6ab-217c-4369-b8f3-64422b3ec842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60720236 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.60720236
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.2637626003
Short name T1013
Test name
Test status
Simulation time 846082515 ps
CPU time 5.1 seconds
Started Mar 17 02:55:47 PM PDT 24
Finished Mar 17 02:55:52 PM PDT 24
Peak memory 210336 kb
Host smart-046e06bf-8fed-431f-890d-21aba5298ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637626003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.2637626003
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3183493991
Short name T145
Test name
Test status
Simulation time 8826869499 ps
CPU time 5.27 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:55:46 PM PDT 24
Peak memory 202816 kb
Host smart-cd6cb773-d985-4656-8c27-d9fb31457a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183493991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3183493991
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2062948098
Short name T321
Test name
Test status
Simulation time 13990481414 ps
CPU time 47.65 seconds
Started Mar 17 02:55:40 PM PDT 24
Finished Mar 17 02:56:28 PM PDT 24
Peak memory 735240 kb
Host smart-409d4604-c8b7-4473-a008-2e1e412d2de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062948098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2062948098
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3738638489
Short name T985
Test name
Test status
Simulation time 1356030856 ps
CPU time 6.08 seconds
Started Mar 17 02:55:45 PM PDT 24
Finished Mar 17 02:55:51 PM PDT 24
Peak memory 202704 kb
Host smart-8aeb6519-69ef-4b92-9e93-9bd4499f87d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738638489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3738638489
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.3994035678
Short name T1206
Test name
Test status
Simulation time 2929929042 ps
CPU time 7.56 seconds
Started Mar 17 02:55:49 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 208768 kb
Host smart-48c5ce3e-38c2-4a36-a73d-4831e9881f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994035678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.3994035678
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1652027777
Short name T514
Test name
Test status
Simulation time 17811759 ps
CPU time 0.62 seconds
Started Mar 17 02:55:50 PM PDT 24
Finished Mar 17 02:55:50 PM PDT 24
Peak memory 201652 kb
Host smart-10557e88-10cb-4055-918f-27ca8fa1362c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652027777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1652027777
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1636200421
Short name T792
Test name
Test status
Simulation time 45702584 ps
CPU time 1.33 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:55:54 PM PDT 24
Peak memory 211004 kb
Host smart-bba2e588-37ee-47dc-afa9-3e4e7be23ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636200421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1636200421
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.142586753
Short name T1027
Test name
Test status
Simulation time 291607802 ps
CPU time 14.39 seconds
Started Mar 17 02:55:46 PM PDT 24
Finished Mar 17 02:56:00 PM PDT 24
Peak memory 258868 kb
Host smart-b3d6c3f7-dc3d-4a71-8c06-7b44463270e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142586753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.142586753
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2408308838
Short name T461
Test name
Test status
Simulation time 4237232536 ps
CPU time 76.44 seconds
Started Mar 17 02:55:51 PM PDT 24
Finished Mar 17 02:57:08 PM PDT 24
Peak memory 731388 kb
Host smart-2708fb6e-66da-4d92-b2ab-1ef34caaee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408308838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2408308838
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.396833246
Short name T834
Test name
Test status
Simulation time 4519137980 ps
CPU time 153.98 seconds
Started Mar 17 02:55:47 PM PDT 24
Finished Mar 17 02:58:22 PM PDT 24
Peak memory 642584 kb
Host smart-133a8100-5090-4eff-992e-8f3617cb859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396833246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.396833246
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1410517970
Short name T481
Test name
Test status
Simulation time 1044251575 ps
CPU time 1.08 seconds
Started Mar 17 02:55:46 PM PDT 24
Finished Mar 17 02:55:47 PM PDT 24
Peak memory 202728 kb
Host smart-dae81ca8-d802-4f5c-834e-b5000a90ae30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410517970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1410517970
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3781026261
Short name T1064
Test name
Test status
Simulation time 404946215 ps
CPU time 11.35 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:56:04 PM PDT 24
Peak memory 241428 kb
Host smart-46f7bac5-943c-45e2-82ea-9e69248b4786
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781026261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3781026261
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1640745819
Short name T720
Test name
Test status
Simulation time 22557392115 ps
CPU time 448.94 seconds
Started Mar 17 02:55:46 PM PDT 24
Finished Mar 17 03:03:15 PM PDT 24
Peak memory 1502384 kb
Host smart-2d4ebc29-cd58-40fb-aac3-de0953e88eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640745819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1640745819
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2890944692
Short name T52
Test name
Test status
Simulation time 6015400480 ps
CPU time 118.77 seconds
Started Mar 17 02:55:58 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 308648 kb
Host smart-a53be2df-f28f-4521-b5d7-8ccf1df703ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890944692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2890944692
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.435201603
Short name T156
Test name
Test status
Simulation time 38649799 ps
CPU time 0.63 seconds
Started Mar 17 02:55:48 PM PDT 24
Finished Mar 17 02:55:49 PM PDT 24
Peak memory 201868 kb
Host smart-b3137f6c-57c2-4d5a-b1b8-6d257d1a81d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435201603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.435201603
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1881887387
Short name T1074
Test name
Test status
Simulation time 7407493622 ps
CPU time 169.08 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:58:41 PM PDT 24
Peak memory 202788 kb
Host smart-4e895da5-d754-41c8-86bb-25091cbe4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881887387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1881887387
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1757356562
Short name T1103
Test name
Test status
Simulation time 2065019701 ps
CPU time 54.15 seconds
Started Mar 17 02:55:48 PM PDT 24
Finished Mar 17 02:56:42 PM PDT 24
Peak memory 292204 kb
Host smart-2575e7e7-7baf-4ea8-aa0d-f4a61024fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757356562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1757356562
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3992163397
Short name T559
Test name
Test status
Simulation time 60614700851 ps
CPU time 1184.89 seconds
Started Mar 17 02:55:58 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 2428264 kb
Host smart-6e34754e-16f8-4b28-8f11-78b61ace0661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992163397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3992163397
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3021811151
Short name T486
Test name
Test status
Simulation time 4732892721 ps
CPU time 31.39 seconds
Started Mar 17 02:55:51 PM PDT 24
Finished Mar 17 02:56:22 PM PDT 24
Peak memory 210876 kb
Host smart-961c95a3-513e-4ee9-a2a9-d960d6e87dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021811151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3021811151
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2367746141
Short name T803
Test name
Test status
Simulation time 2140214088 ps
CPU time 3.1 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 202656 kb
Host smart-e142cab8-5e55-49b4-86a9-fd203d0ca2e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367746141 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2367746141
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.4024190723
Short name T302
Test name
Test status
Simulation time 10515252963 ps
CPU time 5.46 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:56:03 PM PDT 24
Peak memory 236648 kb
Host smart-ab9a593c-d9bf-4a55-a1b3-aa3829ecc205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024190723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.4024190723
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1797483819
Short name T766
Test name
Test status
Simulation time 10023715542 ps
CPU time 78.3 seconds
Started Mar 17 02:55:53 PM PDT 24
Finished Mar 17 02:57:11 PM PDT 24
Peak memory 741104 kb
Host smart-ba1e3732-2053-47e9-a71a-276c4ee81c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797483819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1797483819
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.715999427
Short name T47
Test name
Test status
Simulation time 1605697541 ps
CPU time 2.51 seconds
Started Mar 17 02:55:51 PM PDT 24
Finished Mar 17 02:55:54 PM PDT 24
Peak memory 202820 kb
Host smart-9ff0bd0f-cab0-431c-8eda-0dc794e867e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715999427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.715999427
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2030845720
Short name T1114
Test name
Test status
Simulation time 4667088028 ps
CPU time 2.38 seconds
Started Mar 17 02:55:50 PM PDT 24
Finished Mar 17 02:55:53 PM PDT 24
Peak memory 202780 kb
Host smart-758f4248-1028-4830-8288-82ecf2388b82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030845720 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2030845720
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.2982733623
Short name T376
Test name
Test status
Simulation time 1890176000 ps
CPU time 3.05 seconds
Started Mar 17 02:55:51 PM PDT 24
Finished Mar 17 02:55:54 PM PDT 24
Peak memory 204028 kb
Host smart-24febdf1-d550-4e1e-8320-202aa2143104
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982733623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.2982733623
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3773787587
Short name T815
Test name
Test status
Simulation time 43568449258 ps
CPU time 80.62 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 794480 kb
Host smart-642f34be-2693-460d-a93e-a5d4ee724f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773787587 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3773787587
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3209855207
Short name T698
Test name
Test status
Simulation time 17938026461 ps
CPU time 9.58 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:56:02 PM PDT 24
Peak memory 202768 kb
Host smart-5200c579-ce2d-45f9-9059-597d219d7ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209855207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3209855207
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3263150434
Short name T252
Test name
Test status
Simulation time 12956224058 ps
CPU time 56.25 seconds
Started Mar 17 02:55:51 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 683496 kb
Host smart-7691f3f7-f03e-4016-b299-a2a30e631365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263150434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3263150434
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2622903992
Short name T1132
Test name
Test status
Simulation time 1825757711 ps
CPU time 7.67 seconds
Started Mar 17 02:55:53 PM PDT 24
Finished Mar 17 02:56:00 PM PDT 24
Peak memory 202760 kb
Host smart-74f45ec5-675e-4fae-a36c-500d25e7c2b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622903992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2622903992
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.4246291433
Short name T315
Test name
Test status
Simulation time 2261392905 ps
CPU time 2.99 seconds
Started Mar 17 02:55:56 PM PDT 24
Finished Mar 17 02:56:00 PM PDT 24
Peak memory 202776 kb
Host smart-d5ae973a-03f9-48f2-be18-397036e2691f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246291433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.4246291433
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2936287174
Short name T1181
Test name
Test status
Simulation time 17253059 ps
CPU time 0.64 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:55:58 PM PDT 24
Peak memory 201608 kb
Host smart-7c6c3047-1c4d-4a49-9fa8-9f6ef08d26fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936287174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2936287174
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1030810644
Short name T296
Test name
Test status
Simulation time 34596958 ps
CPU time 1.61 seconds
Started Mar 17 02:55:53 PM PDT 24
Finished Mar 17 02:55:55 PM PDT 24
Peak memory 213448 kb
Host smart-d5393087-0511-4217-a94f-54f2dff6f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030810644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1030810644
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.4112830940
Short name T512
Test name
Test status
Simulation time 1321316823 ps
CPU time 18.31 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 276056 kb
Host smart-b1a61e16-3ea7-40d1-9e3e-8da68ce18143
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112830940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.4112830940
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1470610144
Short name T199
Test name
Test status
Simulation time 10310009626 ps
CPU time 69.67 seconds
Started Mar 17 02:55:58 PM PDT 24
Finished Mar 17 02:57:08 PM PDT 24
Peak memory 666732 kb
Host smart-f4c3e0eb-9919-40f0-9387-5ee608bde012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470610144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1470610144
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2765967655
Short name T16
Test name
Test status
Simulation time 3137855086 ps
CPU time 84.47 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:57:22 PM PDT 24
Peak memory 778732 kb
Host smart-0350b60e-fe7b-4f96-9b57-567fedd98be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765967655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2765967655
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.595298354
Short name T551
Test name
Test status
Simulation time 121518752 ps
CPU time 1.13 seconds
Started Mar 17 02:55:55 PM PDT 24
Finished Mar 17 02:55:56 PM PDT 24
Peak memory 202752 kb
Host smart-875c0d4d-889f-43b1-87ed-b90606394e5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595298354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.595298354
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2329270571
Short name T677
Test name
Test status
Simulation time 234973520 ps
CPU time 3.6 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:56:01 PM PDT 24
Peak memory 202744 kb
Host smart-584b93d3-adb4-456b-bd2b-b0b37a9ddda9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329270571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2329270571
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3143960775
Short name T480
Test name
Test status
Simulation time 6305131598 ps
CPU time 234.72 seconds
Started Mar 17 02:55:56 PM PDT 24
Finished Mar 17 02:59:51 PM PDT 24
Peak memory 1768960 kb
Host smart-fe64de48-0191-4309-8121-40be4c82469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143960775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3143960775
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1065371532
Short name T839
Test name
Test status
Simulation time 1646119625 ps
CPU time 45.29 seconds
Started Mar 17 02:56:00 PM PDT 24
Finished Mar 17 02:56:46 PM PDT 24
Peak memory 291828 kb
Host smart-fadc8f3f-8056-455c-9d09-fa8d28cf4f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065371532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1065371532
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3602402091
Short name T469
Test name
Test status
Simulation time 16767137 ps
CPU time 0.6 seconds
Started Mar 17 02:55:54 PM PDT 24
Finished Mar 17 02:55:55 PM PDT 24
Peak memory 201844 kb
Host smart-f3895079-294e-49bb-9eea-ba8c83f359a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602402091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3602402091
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1595274140
Short name T162
Test name
Test status
Simulation time 944455485 ps
CPU time 2.14 seconds
Started Mar 17 02:55:55 PM PDT 24
Finished Mar 17 02:55:57 PM PDT 24
Peak memory 210968 kb
Host smart-90c2729c-47fc-4784-8d36-1a9e6707d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595274140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1595274140
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4015839426
Short name T1084
Test name
Test status
Simulation time 4097705851 ps
CPU time 87.39 seconds
Started Mar 17 02:55:52 PM PDT 24
Finished Mar 17 02:57:20 PM PDT 24
Peak memory 383084 kb
Host smart-7060ee30-738b-4bb2-aa5c-cba9f2a89052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015839426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4015839426
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3695015515
Short name T203
Test name
Test status
Simulation time 21306072169 ps
CPU time 258.7 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 03:00:16 PM PDT 24
Peak memory 267428 kb
Host smart-1003e039-5711-407d-b41b-987ac110dbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695015515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3695015515
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1660586593
Short name T670
Test name
Test status
Simulation time 1882789146 ps
CPU time 14.3 seconds
Started Mar 17 02:55:56 PM PDT 24
Finished Mar 17 02:56:11 PM PDT 24
Peak memory 227248 kb
Host smart-0da1740e-6dfc-4331-bcf5-32630d9b817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660586593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1660586593
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.253769776
Short name T1076
Test name
Test status
Simulation time 679918438 ps
CPU time 3.21 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 202724 kb
Host smart-630abef7-67f9-4af8-afb8-e43cd44431dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253769776 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.253769776
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2034268506
Short name T453
Test name
Test status
Simulation time 10137902213 ps
CPU time 15 seconds
Started Mar 17 02:55:53 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 301944 kb
Host smart-6c5250ea-50b6-4383-842e-c1923c7ac687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034268506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2034268506
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.678510306
Short name T534
Test name
Test status
Simulation time 10067951745 ps
CPU time 77.24 seconds
Started Mar 17 02:55:55 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 755160 kb
Host smart-bb8b17b2-d5ed-4741-9d21-b6a72ca12a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678510306 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.678510306
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2488069640
Short name T600
Test name
Test status
Simulation time 6758407828 ps
CPU time 9.66 seconds
Started Mar 17 02:55:59 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 202756 kb
Host smart-e0b1d28c-b716-46c7-b649-f79632d4786f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488069640 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2488069640
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.4134939216
Short name T499
Test name
Test status
Simulation time 1201397859 ps
CPU time 3.64 seconds
Started Mar 17 02:55:55 PM PDT 24
Finished Mar 17 02:55:59 PM PDT 24
Peak memory 205864 kb
Host smart-c68d45f3-dc1e-4fe9-b864-d2ddafe36549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134939216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.4134939216
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1870273039
Short name T969
Test name
Test status
Simulation time 1859457685 ps
CPU time 25.95 seconds
Started Mar 17 02:55:55 PM PDT 24
Finished Mar 17 02:56:21 PM PDT 24
Peak memory 202640 kb
Host smart-8ae593c5-fa5d-4e0a-9afa-a5974dbbc951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870273039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1870273039
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.802398178
Short name T946
Test name
Test status
Simulation time 3543338507 ps
CPU time 69.49 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:57:07 PM PDT 24
Peak memory 203172 kb
Host smart-5a97436f-4982-42ab-b7af-de7cf735d8b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802398178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.802398178
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3333495860
Short name T1170
Test name
Test status
Simulation time 44170842939 ps
CPU time 104.29 seconds
Started Mar 17 02:55:54 PM PDT 24
Finished Mar 17 02:57:39 PM PDT 24
Peak memory 1726688 kb
Host smart-321cf77d-4c58-4a14-8953-caa8acad9380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333495860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3333495860
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2858801027
Short name T712
Test name
Test status
Simulation time 6594341962 ps
CPU time 7.65 seconds
Started Mar 17 02:55:57 PM PDT 24
Finished Mar 17 02:56:05 PM PDT 24
Peak memory 207216 kb
Host smart-98c39d57-c998-4bec-978b-4b4e4c20221b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858801027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2858801027
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.282635267
Short name T621
Test name
Test status
Simulation time 1738435393 ps
CPU time 8.03 seconds
Started Mar 17 02:55:59 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 206120 kb
Host smart-d4e14162-0718-4ea1-8dd2-79a85edc13f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282635267 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_unexp_stop.282635267
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3379265018
Short name T993
Test name
Test status
Simulation time 110784286 ps
CPU time 0.64 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:04 PM PDT 24
Peak memory 201660 kb
Host smart-5d0f91e8-ffa8-4c85-a60b-989c4bd55788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379265018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3379265018
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1574946810
Short name T748
Test name
Test status
Simulation time 129982558 ps
CPU time 1.59 seconds
Started Mar 17 02:56:07 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 210976 kb
Host smart-2594b184-d253-481e-a032-5673c6151f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574946810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1574946810
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2612396538
Short name T403
Test name
Test status
Simulation time 627392345 ps
CPU time 4.15 seconds
Started Mar 17 02:55:58 PM PDT 24
Finished Mar 17 02:56:03 PM PDT 24
Peak memory 237112 kb
Host smart-ba3fc729-0d0e-496f-bca7-1bd3bfd7ab1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612396538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2612396538
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2239638884
Short name T394
Test name
Test status
Simulation time 9231767603 ps
CPU time 82.63 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:57:27 PM PDT 24
Peak memory 636744 kb
Host smart-c42ccbf8-9f96-47b0-b1eb-817a8be3ff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239638884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2239638884
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2581246
Short name T14
Test name
Test status
Simulation time 1766112331 ps
CPU time 46.47 seconds
Started Mar 17 02:56:00 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 610436 kb
Host smart-a7ccdb12-ea1e-4b10-be35-18c62331aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2581246
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2687911385
Short name T1111
Test name
Test status
Simulation time 140619581 ps
CPU time 1.1 seconds
Started Mar 17 02:56:02 PM PDT 24
Finished Mar 17 02:56:03 PM PDT 24
Peak memory 202628 kb
Host smart-78bf0b22-09fc-44a8-beb2-b50f17e2a218
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687911385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2687911385
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.603504060
Short name T1050
Test name
Test status
Simulation time 304799444 ps
CPU time 9.04 seconds
Started Mar 17 02:55:59 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 229028 kb
Host smart-a43ba1eb-d2ea-4f89-a7d0-f1a5c03ba6ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603504060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
603504060
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3556832097
Short name T819
Test name
Test status
Simulation time 86096326925 ps
CPU time 153.52 seconds
Started Mar 17 02:56:01 PM PDT 24
Finished Mar 17 02:58:35 PM PDT 24
Peak memory 1518736 kb
Host smart-ef75c92e-fb3c-4619-bd88-0740e0b7aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556832097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3556832097
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.366290832
Short name T1137
Test name
Test status
Simulation time 8770423578 ps
CPU time 54.65 seconds
Started Mar 17 02:56:05 PM PDT 24
Finished Mar 17 02:57:00 PM PDT 24
Peak memory 295928 kb
Host smart-3db42aa8-f96a-48e0-ae2d-df35f4aaa5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366290832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.366290832
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1441955518
Short name T775
Test name
Test status
Simulation time 54865423 ps
CPU time 0.63 seconds
Started Mar 17 02:56:07 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 201820 kb
Host smart-7c1252b1-c44b-49e0-9fac-e6b516888658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441955518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1441955518
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1133473187
Short name T223
Test name
Test status
Simulation time 7018128496 ps
CPU time 71.34 seconds
Started Mar 17 02:56:00 PM PDT 24
Finished Mar 17 02:57:12 PM PDT 24
Peak memory 328176 kb
Host smart-8140f993-a9ce-4851-90e1-4da459df2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133473187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1133473187
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.891776017
Short name T1219
Test name
Test status
Simulation time 4236695306 ps
CPU time 127.35 seconds
Started Mar 17 02:56:01 PM PDT 24
Finished Mar 17 02:58:09 PM PDT 24
Peak memory 261076 kb
Host smart-ca1f6690-bdf8-42a8-b455-63439b2abbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891776017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.891776017
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3449979226
Short name T439
Test name
Test status
Simulation time 74495659787 ps
CPU time 844.05 seconds
Started Mar 17 02:56:02 PM PDT 24
Finished Mar 17 03:10:06 PM PDT 24
Peak memory 1361044 kb
Host smart-208d0f5a-9e00-4181-afba-1c2354f313f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449979226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3449979226
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.201475945
Short name T1260
Test name
Test status
Simulation time 1526509124 ps
CPU time 13.28 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 218864 kb
Host smart-62a47cc4-bfc9-407b-8891-e44d6c469bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201475945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.201475945
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.192358765
Short name T830
Test name
Test status
Simulation time 971257262 ps
CPU time 4.68 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:08 PM PDT 24
Peak memory 202764 kb
Host smart-2c427c17-7220-4e4d-baaa-0367ca767817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192358765 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.192358765
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3014752881
Short name T348
Test name
Test status
Simulation time 10044823787 ps
CPU time 78.78 seconds
Started Mar 17 02:56:05 PM PDT 24
Finished Mar 17 02:57:24 PM PDT 24
Peak memory 678056 kb
Host smart-f504e306-8c55-4132-b55a-d8b7413d6d6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014752881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3014752881
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3537474237
Short name T777
Test name
Test status
Simulation time 1151556296 ps
CPU time 1.81 seconds
Started Mar 17 02:56:05 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 202776 kb
Host smart-021be2c1-56ec-4724-a387-ac485fb2b1e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537474237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3537474237
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1511998359
Short name T896
Test name
Test status
Simulation time 15974491245 ps
CPU time 6.71 seconds
Started Mar 17 02:56:02 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 202716 kb
Host smart-ec0f0233-d08d-4791-84c7-ad99562a85ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511998359 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1511998359
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.569365279
Short name T1141
Test name
Test status
Simulation time 16002126240 ps
CPU time 183.58 seconds
Started Mar 17 02:56:02 PM PDT 24
Finished Mar 17 02:59:06 PM PDT 24
Peak memory 2303856 kb
Host smart-191502d2-5fe4-468d-a31a-6ffb6ca339fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569365279 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.569365279
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.1586708366
Short name T488
Test name
Test status
Simulation time 894799066 ps
CPU time 5.44 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 202684 kb
Host smart-90d5c8e7-8203-4d2d-b2d3-da49d019acef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586708366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.1586708366
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2496991651
Short name T637
Test name
Test status
Simulation time 919518491 ps
CPU time 26.15 seconds
Started Mar 17 02:56:02 PM PDT 24
Finished Mar 17 02:56:28 PM PDT 24
Peak memory 202692 kb
Host smart-3f0b8edc-a43b-4d7b-b0c6-0e5d37627310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496991651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2496991651
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.717191804
Short name T818
Test name
Test status
Simulation time 17862710013 ps
CPU time 66.31 seconds
Started Mar 17 02:56:06 PM PDT 24
Finished Mar 17 02:57:12 PM PDT 24
Peak memory 307968 kb
Host smart-b669d75b-2cf5-4298-abcd-0788e65df8b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717191804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.717191804
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1666207024
Short name T505
Test name
Test status
Simulation time 63768694171 ps
CPU time 2574.38 seconds
Started Mar 17 02:56:01 PM PDT 24
Finished Mar 17 03:38:55 PM PDT 24
Peak memory 11158244 kb
Host smart-0fb0753a-3e81-411c-be09-aee191391438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666207024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1666207024
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.423922952
Short name T259
Test name
Test status
Simulation time 1260753362 ps
CPU time 6.2 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:09 PM PDT 24
Peak memory 202836 kb
Host smart-5c3c4174-eaf2-42d7-bee2-d9347fec8320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423922952 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.423922952
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.1630854352
Short name T371
Test name
Test status
Simulation time 2467065473 ps
CPU time 3.97 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:07 PM PDT 24
Peak memory 202712 kb
Host smart-e180ceeb-a52c-4db5-89e3-ed119f968b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630854352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.1630854352
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3180234703
Short name T913
Test name
Test status
Simulation time 17346494 ps
CPU time 0.61 seconds
Started Mar 17 02:56:19 PM PDT 24
Finished Mar 17 02:56:20 PM PDT 24
Peak memory 201596 kb
Host smart-5d689ae1-5f3e-40a1-bf9c-7044678b6f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180234703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3180234703
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2162185340
Short name T423
Test name
Test status
Simulation time 27953916 ps
CPU time 1.21 seconds
Started Mar 17 02:56:09 PM PDT 24
Finished Mar 17 02:56:10 PM PDT 24
Peak memory 202824 kb
Host smart-95e64052-702f-4487-80c1-e75bdf737734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162185340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2162185340
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1350727149
Short name T250
Test name
Test status
Simulation time 1841974950 ps
CPU time 8.91 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:56:13 PM PDT 24
Peak memory 307552 kb
Host smart-869b9451-2f0d-4b4b-bbcb-63ef4e256fb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350727149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1350727149
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3789503999
Short name T1040
Test name
Test status
Simulation time 2649807392 ps
CPU time 62.02 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:57:06 PM PDT 24
Peak memory 366040 kb
Host smart-9393c664-89e1-4162-a960-cd60bbf32379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789503999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3789503999
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3860002172
Short name T432
Test name
Test status
Simulation time 11698602086 ps
CPU time 108.62 seconds
Started Mar 17 02:56:05 PM PDT 24
Finished Mar 17 02:57:54 PM PDT 24
Peak memory 825712 kb
Host smart-1a9f3fb4-7ff9-426b-8457-0eb251e2af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860002172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3860002172
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1145222805
Short name T838
Test name
Test status
Simulation time 224967073 ps
CPU time 0.91 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:56:05 PM PDT 24
Peak memory 202432 kb
Host smart-6cd7388e-b101-4a2a-9655-a47ec3d8701b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145222805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1145222805
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2242994793
Short name T1142
Test name
Test status
Simulation time 1602414982 ps
CPU time 11.7 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:56:17 PM PDT 24
Peak memory 202664 kb
Host smart-a86fe1b4-4b9c-4830-b98f-72a20c804745
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242994793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2242994793
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2909362312
Short name T676
Test name
Test status
Simulation time 5155317840 ps
CPU time 138.4 seconds
Started Mar 17 02:56:05 PM PDT 24
Finished Mar 17 02:58:24 PM PDT 24
Peak memory 1500504 kb
Host smart-29d89985-3423-4e26-99f0-229376e8b017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909362312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2909362312
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3340920899
Short name T943
Test name
Test status
Simulation time 3600204291 ps
CPU time 64.94 seconds
Started Mar 17 02:56:12 PM PDT 24
Finished Mar 17 02:57:18 PM PDT 24
Peak memory 295232 kb
Host smart-90a91ffc-8730-49ad-aca4-1f70338a4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340920899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3340920899
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1047779662
Short name T903
Test name
Test status
Simulation time 28459303 ps
CPU time 0.63 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:56:05 PM PDT 24
Peak memory 202008 kb
Host smart-1b14394e-accf-4fbd-b627-101fa88bf0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047779662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1047779662
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1460495886
Short name T986
Test name
Test status
Simulation time 3540939255 ps
CPU time 44.7 seconds
Started Mar 17 02:56:03 PM PDT 24
Finished Mar 17 02:56:48 PM PDT 24
Peak memory 331328 kb
Host smart-6ba565d4-0c92-4ea7-92bf-6b7b3a9f502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460495886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1460495886
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2948818202
Short name T799
Test name
Test status
Simulation time 8052630347 ps
CPU time 113.16 seconds
Started Mar 17 02:56:04 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 397216 kb
Host smart-628fb4e8-3f6b-4b36-8749-f57489f3336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948818202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2948818202
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.402630490
Short name T1026
Test name
Test status
Simulation time 26750075745 ps
CPU time 639.08 seconds
Started Mar 17 02:56:09 PM PDT 24
Finished Mar 17 03:06:48 PM PDT 24
Peak memory 786408 kb
Host smart-b6d2d93a-21e0-4ab9-b466-3a22b214eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402630490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.402630490
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2847218463
Short name T448
Test name
Test status
Simulation time 4386600987 ps
CPU time 21.88 seconds
Started Mar 17 02:56:11 PM PDT 24
Finished Mar 17 02:56:33 PM PDT 24
Peak memory 227088 kb
Host smart-56fa14e7-2567-4611-8f41-81059b14a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847218463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2847218463
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2475792308
Short name T994
Test name
Test status
Simulation time 5632856548 ps
CPU time 5.44 seconds
Started Mar 17 02:56:19 PM PDT 24
Finished Mar 17 02:56:25 PM PDT 24
Peak memory 202796 kb
Host smart-e4aff410-98dd-4d4d-a34e-d6e1ebbb5f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475792308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2475792308
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.475456931
Short name T1128
Test name
Test status
Simulation time 10101862637 ps
CPU time 13 seconds
Started Mar 17 02:56:09 PM PDT 24
Finished Mar 17 02:56:22 PM PDT 24
Peak memory 270536 kb
Host smart-593e7be7-84b9-405c-a48b-184d7b916d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475456931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.475456931
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2508482022
Short name T562
Test name
Test status
Simulation time 10260163196 ps
CPU time 14.83 seconds
Started Mar 17 02:56:12 PM PDT 24
Finished Mar 17 02:56:27 PM PDT 24
Peak memory 319416 kb
Host smart-15e6a756-91c1-4666-836c-4060bf56530d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508482022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2508482022
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.406260783
Short name T1221
Test name
Test status
Simulation time 3688322542 ps
CPU time 3.61 seconds
Started Mar 17 02:56:13 PM PDT 24
Finished Mar 17 02:56:17 PM PDT 24
Peak memory 203332 kb
Host smart-e41b1737-a0ca-4312-ae38-f056d49d031c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406260783 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.406260783
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2453951967
Short name T999
Test name
Test status
Simulation time 24535962993 ps
CPU time 6.98 seconds
Started Mar 17 02:56:08 PM PDT 24
Finished Mar 17 02:56:15 PM PDT 24
Peak memory 202716 kb
Host smart-e49e3ea1-5573-49d3-9f61-1659d8b0e202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453951967 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2453951967
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.2110050273
Short name T805
Test name
Test status
Simulation time 576476521 ps
CPU time 2.91 seconds
Started Mar 17 02:56:19 PM PDT 24
Finished Mar 17 02:56:22 PM PDT 24
Peak memory 202692 kb
Host smart-87121bef-b5c9-4638-a9e8-7cd4ebd0535a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110050273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.2110050273
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3190322362
Short name T1090
Test name
Test status
Simulation time 674206664 ps
CPU time 9.77 seconds
Started Mar 17 02:56:08 PM PDT 24
Finished Mar 17 02:56:17 PM PDT 24
Peak memory 205284 kb
Host smart-f0abdcea-edd3-48f5-813b-32a7fd15b550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190322362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3190322362
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2209289115
Short name T96
Test name
Test status
Simulation time 48652807767 ps
CPU time 115.99 seconds
Started Mar 17 02:56:09 PM PDT 24
Finished Mar 17 02:58:05 PM PDT 24
Peak memory 1642024 kb
Host smart-a6fa3681-7408-4451-9049-a7863ff808c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209289115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2209289115
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.255324104
Short name T275
Test name
Test status
Simulation time 37907559932 ps
CPU time 626.51 seconds
Started Mar 17 02:56:13 PM PDT 24
Finished Mar 17 03:06:39 PM PDT 24
Peak memory 3566504 kb
Host smart-563adca8-9ff6-4292-af02-9c22ded535de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255324104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.255324104
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4028140307
Short name T1185
Test name
Test status
Simulation time 7054935941 ps
CPU time 7.01 seconds
Started Mar 17 02:56:09 PM PDT 24
Finished Mar 17 02:56:17 PM PDT 24
Peak memory 202748 kb
Host smart-d08f1378-b86b-4368-98b7-4ac02a299a3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028140307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4028140307
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4160369873
Short name T709
Test name
Test status
Simulation time 121042851 ps
CPU time 0.61 seconds
Started Mar 17 02:53:17 PM PDT 24
Finished Mar 17 02:53:18 PM PDT 24
Peak memory 201540 kb
Host smart-f6e10b94-937d-496f-ae8f-d6f36fd6d91b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160369873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4160369873
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.365897054
Short name T1152
Test name
Test status
Simulation time 71606880 ps
CPU time 1.47 seconds
Started Mar 17 02:53:12 PM PDT 24
Finished Mar 17 02:53:13 PM PDT 24
Peak memory 211004 kb
Host smart-1b0f6d69-3233-4132-83e1-3941a7401b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365897054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.365897054
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1462166991
Short name T1205
Test name
Test status
Simulation time 204594509 ps
CPU time 4.41 seconds
Started Mar 17 02:53:10 PM PDT 24
Finished Mar 17 02:53:14 PM PDT 24
Peak memory 239856 kb
Host smart-9efb1448-bc7e-4c46-aee5-99aa15945a7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462166991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1462166991
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.661306618
Short name T926
Test name
Test status
Simulation time 12508562462 ps
CPU time 128.6 seconds
Started Mar 17 02:53:08 PM PDT 24
Finished Mar 17 02:55:22 PM PDT 24
Peak memory 671056 kb
Host smart-fda3017b-efc9-4972-a8e7-cdae5e4a0731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661306618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.661306618
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2718007893
Short name T331
Test name
Test status
Simulation time 2813209079 ps
CPU time 97.4 seconds
Started Mar 17 02:53:12 PM PDT 24
Finished Mar 17 02:54:50 PM PDT 24
Peak memory 804848 kb
Host smart-a06616ad-7716-41f9-a75f-9e43066a6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718007893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2718007893
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1147982146
Short name T1194
Test name
Test status
Simulation time 57041777 ps
CPU time 0.77 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:30 PM PDT 24
Peak memory 202492 kb
Host smart-27add69f-1ad2-4307-a8a1-b7b4a3405e4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147982146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1147982146
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.760714498
Short name T849
Test name
Test status
Simulation time 788828311 ps
CPU time 8.85 seconds
Started Mar 17 02:53:11 PM PDT 24
Finished Mar 17 02:53:21 PM PDT 24
Peak memory 202704 kb
Host smart-0948db16-f5d3-4a3e-bda5-efe092d27d3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760714498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.760714498
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.281756988
Short name T1243
Test name
Test status
Simulation time 23295813241 ps
CPU time 195.51 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:56:49 PM PDT 24
Peak memory 1624268 kb
Host smart-d72aa85f-7919-416d-ae19-ae2562e10764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281756988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.281756988
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2314946311
Short name T176
Test name
Test status
Simulation time 5095329528 ps
CPU time 65.72 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:54:23 PM PDT 24
Peak memory 233924 kb
Host smart-f10c8bef-b5e0-4309-bb76-684dc75fb0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314946311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2314946311
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3708101811
Short name T718
Test name
Test status
Simulation time 24671772 ps
CPU time 0.64 seconds
Started Mar 17 02:53:11 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 201852 kb
Host smart-3f217b57-fbbe-42ee-8efb-b6d72c51a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708101811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3708101811
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3248674960
Short name T254
Test name
Test status
Simulation time 2928564379 ps
CPU time 49.76 seconds
Started Mar 17 02:53:14 PM PDT 24
Finished Mar 17 02:54:04 PM PDT 24
Peak memory 227252 kb
Host smart-6e9cf5e3-8e3f-44d5-96c3-e8ee7487b112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248674960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3248674960
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2079162888
Short name T1224
Test name
Test status
Simulation time 2027019719 ps
CPU time 55.96 seconds
Started Mar 17 02:53:12 PM PDT 24
Finished Mar 17 02:54:08 PM PDT 24
Peak memory 295224 kb
Host smart-8f19f9a0-c085-4e2f-a5d6-dc4f53313255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079162888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2079162888
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3728751597
Short name T138
Test name
Test status
Simulation time 102890305116 ps
CPU time 2230.33 seconds
Started Mar 17 02:53:12 PM PDT 24
Finished Mar 17 03:30:23 PM PDT 24
Peak memory 2462824 kb
Host smart-868e35f7-c331-46a6-9c21-d03da48bf603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728751597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3728751597
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2298132127
Short name T742
Test name
Test status
Simulation time 3682084352 ps
CPU time 17.7 seconds
Started Mar 17 02:53:14 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 219184 kb
Host smart-7ec6c407-163c-4fe6-b459-4ff575e0d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298132127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2298132127
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.68142534
Short name T88
Test name
Test status
Simulation time 74217459 ps
CPU time 0.99 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 02:53:33 PM PDT 24
Peak memory 221180 kb
Host smart-5f43b9d0-4d2e-4f16-985f-ee7cabcf2b17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68142534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.68142534
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.449767426
Short name T359
Test name
Test status
Simulation time 791393698 ps
CPU time 3.63 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:53:19 PM PDT 24
Peak memory 202768 kb
Host smart-b99e6b5a-9619-4acf-be6c-de7dbe33e9c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449767426 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.449767426
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.209819923
Short name T369
Test name
Test status
Simulation time 10083646838 ps
CPU time 29.8 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 407876 kb
Host smart-6d573815-43ae-4b70-bc2e-9f3ed5f0f0b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209819923 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.209819923
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3807499400
Short name T697
Test name
Test status
Simulation time 10209753589 ps
CPU time 35.82 seconds
Started Mar 17 02:53:15 PM PDT 24
Finished Mar 17 02:53:51 PM PDT 24
Peak memory 438572 kb
Host smart-193f8f07-bbb3-415d-8d23-d249c2ab1a7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807499400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3807499400
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3597754759
Short name T33
Test name
Test status
Simulation time 1760756390 ps
CPU time 2.33 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:53:19 PM PDT 24
Peak memory 202768 kb
Host smart-f793a7b0-b23b-4348-a950-4d44475f86ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597754759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3597754759
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3522105594
Short name T493
Test name
Test status
Simulation time 3173731865 ps
CPU time 4.41 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 206828 kb
Host smart-21887b28-1188-4a21-ba3a-1da10b12f674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522105594 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3522105594
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3323448973
Short name T814
Test name
Test status
Simulation time 6307450922 ps
CPU time 4.59 seconds
Started Mar 17 02:53:15 PM PDT 24
Finished Mar 17 02:53:20 PM PDT 24
Peak memory 202704 kb
Host smart-5b0972cd-a5de-4e80-8dab-bb3821757028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323448973 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3323448973
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.2868705908
Short name T457
Test name
Test status
Simulation time 2142786508 ps
CPU time 3.9 seconds
Started Mar 17 02:53:27 PM PDT 24
Finished Mar 17 02:53:31 PM PDT 24
Peak memory 204764 kb
Host smart-fa5a1598-eb11-4896-a952-b9a9c392b108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868705908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.2868705908
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2902455162
Short name T433
Test name
Test status
Simulation time 33865241412 ps
CPU time 46.77 seconds
Started Mar 17 02:53:30 PM PDT 24
Finished Mar 17 02:54:17 PM PDT 24
Peak memory 235144 kb
Host smart-a8bdfde6-551e-471f-88fb-60aa9c73df4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902455162 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2902455162
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2809597296
Short name T427
Test name
Test status
Simulation time 4573180298 ps
CPU time 9.79 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:53:46 PM PDT 24
Peak memory 202736 kb
Host smart-374a80d9-a7de-4dd9-b04a-21dcd2511a43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809597296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2809597296
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.524813483
Short name T405
Test name
Test status
Simulation time 34004263356 ps
CPU time 347.43 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:59:24 PM PDT 24
Peak memory 3518736 kb
Host smart-1678a77f-377e-4472-ae26-5e43571f3975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524813483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.524813483
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.774491271
Short name T779
Test name
Test status
Simulation time 15833988541 ps
CPU time 36.62 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:54:05 PM PDT 24
Peak memory 567652 kb
Host smart-7126203f-82d9-488d-9b5b-fa6dae4a6a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774491271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.774491271
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3248351855
Short name T1240
Test name
Test status
Simulation time 6993970247 ps
CPU time 6.96 seconds
Started Mar 17 02:53:25 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 209144 kb
Host smart-b67857b2-c561-4f4f-bb9e-ba1f8f2e4a87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248351855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3248351855
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.2899285257
Short name T1255
Test name
Test status
Simulation time 762876239 ps
CPU time 4.31 seconds
Started Mar 17 02:53:17 PM PDT 24
Finished Mar 17 02:53:22 PM PDT 24
Peak memory 202700 kb
Host smart-298eaa4d-6217-40dc-bffb-d44cdc80cc16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899285257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.2899285257
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2158295382
Short name T2
Test name
Test status
Simulation time 44284980 ps
CPU time 0.61 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 200568 kb
Host smart-eb9802b9-534f-4b56-91fe-07ec11f3118c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158295382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2158295382
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2398649731
Short name T644
Test name
Test status
Simulation time 904906554 ps
CPU time 10.21 seconds
Started Mar 17 02:56:14 PM PDT 24
Finished Mar 17 02:56:24 PM PDT 24
Peak memory 303068 kb
Host smart-dc1328cb-aaf5-4d71-9684-5846b82b4ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398649731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2398649731
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.292542887
Short name T1066
Test name
Test status
Simulation time 48623205535 ps
CPU time 230.92 seconds
Started Mar 17 02:56:16 PM PDT 24
Finished Mar 17 03:00:07 PM PDT 24
Peak memory 878944 kb
Host smart-b2efb791-954b-48f7-8e6f-c713aa673169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292542887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.292542887
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2871995956
Short name T787
Test name
Test status
Simulation time 10799150419 ps
CPU time 236.83 seconds
Started Mar 17 02:56:15 PM PDT 24
Finished Mar 17 03:00:12 PM PDT 24
Peak memory 903044 kb
Host smart-61758f84-bdd2-4d3b-ba93-86673fe0880f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871995956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2871995956
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2601370222
Short name T891
Test name
Test status
Simulation time 1369618750 ps
CPU time 0.88 seconds
Started Mar 17 02:56:14 PM PDT 24
Finished Mar 17 02:56:15 PM PDT 24
Peak memory 202496 kb
Host smart-d16ff6c0-2d5f-41e9-9c93-c042afa3c3ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601370222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2601370222
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3313777998
Short name T441
Test name
Test status
Simulation time 201182042 ps
CPU time 5.28 seconds
Started Mar 17 02:56:15 PM PDT 24
Finished Mar 17 02:56:20 PM PDT 24
Peak memory 237864 kb
Host smart-77702bc5-79c9-4969-b8a4-0eaac24ef361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313777998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3313777998
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.697325453
Short name T1139
Test name
Test status
Simulation time 5044870004 ps
CPU time 450.81 seconds
Started Mar 17 02:56:16 PM PDT 24
Finished Mar 17 03:03:47 PM PDT 24
Peak memory 1461180 kb
Host smart-67831173-ac03-4406-98c7-c379cd1d22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697325453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.697325453
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3940592826
Short name T1146
Test name
Test status
Simulation time 5019643478 ps
CPU time 108.29 seconds
Started Mar 17 02:56:25 PM PDT 24
Finished Mar 17 02:58:13 PM PDT 24
Peak memory 402440 kb
Host smart-dac7e616-738d-43a6-a9b1-b00590fd1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940592826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3940592826
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.4249573014
Short name T5
Test name
Test status
Simulation time 57298553 ps
CPU time 0.63 seconds
Started Mar 17 02:56:14 PM PDT 24
Finished Mar 17 02:56:15 PM PDT 24
Peak memory 201796 kb
Host smart-24cd820a-3d63-4719-87a4-62ae590e4170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249573014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4249573014
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3644720016
Short name T1129
Test name
Test status
Simulation time 75136068017 ps
CPU time 1212.61 seconds
Started Mar 17 02:56:17 PM PDT 24
Finished Mar 17 03:16:30 PM PDT 24
Peak memory 348380 kb
Host smart-5ad9fcfe-1c87-4615-9d99-f3e4bcef6c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644720016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3644720016
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1888024635
Short name T362
Test name
Test status
Simulation time 14377201583 ps
CPU time 32.23 seconds
Started Mar 17 02:56:14 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 244168 kb
Host smart-d297a842-d189-44db-b7be-1357c65cb482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888024635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1888024635
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3724685187
Short name T309
Test name
Test status
Simulation time 9647643970 ps
CPU time 10.76 seconds
Started Mar 17 02:56:20 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 210916 kb
Host smart-bd967310-3bda-4838-9306-a61d4663909b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724685187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3724685187
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1036910814
Short name T1030
Test name
Test status
Simulation time 1044346393 ps
CPU time 4.36 seconds
Started Mar 17 02:56:27 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 202616 kb
Host smart-93cbdcb9-4981-423c-99ac-4eb57a89642d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036910814 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1036910814
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2572750938
Short name T21
Test name
Test status
Simulation time 10726197614 ps
CPU time 14.8 seconds
Started Mar 17 02:56:25 PM PDT 24
Finished Mar 17 02:56:40 PM PDT 24
Peak memory 349372 kb
Host smart-4963c82a-7091-4b5f-9fa6-39fafdd16d6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572750938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2572750938
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2845845342
Short name T1154
Test name
Test status
Simulation time 3698989909 ps
CPU time 2.59 seconds
Started Mar 17 02:56:24 PM PDT 24
Finished Mar 17 02:56:26 PM PDT 24
Peak memory 202904 kb
Host smart-8ae75a0c-d01f-463f-a931-268ab11d3b92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845845342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2845845342
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1791087264
Short name T379
Test name
Test status
Simulation time 3625062357 ps
CPU time 4.67 seconds
Started Mar 17 02:56:17 PM PDT 24
Finished Mar 17 02:56:22 PM PDT 24
Peak memory 203092 kb
Host smart-99dfb425-b035-45ab-a1a4-0803b3b0fe36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791087264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1791087264
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3909726766
Short name T555
Test name
Test status
Simulation time 11510024807 ps
CPU time 28.62 seconds
Started Mar 17 02:56:26 PM PDT 24
Finished Mar 17 02:56:56 PM PDT 24
Peak memory 673876 kb
Host smart-bece9000-b8ea-4d77-8d8a-d451e77a8fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909726766 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3909726766
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.707949356
Short name T354
Test name
Test status
Simulation time 988696697 ps
CPU time 5.21 seconds
Started Mar 17 02:56:24 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 202676 kb
Host smart-31aeba2e-2c1e-4eec-a3fe-52c5d01e193b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707949356 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.707949356
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1562070413
Short name T435
Test name
Test status
Simulation time 53829377146 ps
CPU time 175.75 seconds
Started Mar 17 02:56:19 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 2195920 kb
Host smart-df1dc65f-1ed0-4989-9877-2e6804a31e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562070413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1562070413
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3449808988
Short name T233
Test name
Test status
Simulation time 7651697683 ps
CPU time 207.69 seconds
Started Mar 17 02:56:19 PM PDT 24
Finished Mar 17 02:59:47 PM PDT 24
Peak memory 1976000 kb
Host smart-ef6b32bd-4fa2-4460-a278-69f9bfe29f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449808988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3449808988
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1678144906
Short name T829
Test name
Test status
Simulation time 6350175966 ps
CPU time 7.95 seconds
Started Mar 17 02:56:23 PM PDT 24
Finished Mar 17 02:56:31 PM PDT 24
Peak memory 207740 kb
Host smart-8ca5700f-b998-4883-97c8-e3d5b969ff76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678144906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1678144906
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.1684008137
Short name T428
Test name
Test status
Simulation time 3888190884 ps
CPU time 5.72 seconds
Started Mar 17 02:56:24 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 208848 kb
Host smart-1c71e3c1-9f5a-4eda-8fe8-5586bd2e01f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684008137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.1684008137
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3167843118
Short name T750
Test name
Test status
Simulation time 38128833 ps
CPU time 0.6 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 201648 kb
Host smart-7b0ac906-764e-44ee-93fa-5090bbc7bdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167843118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3167843118
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1012571982
Short name T925
Test name
Test status
Simulation time 180357034 ps
CPU time 1.5 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:33 PM PDT 24
Peak memory 210992 kb
Host smart-d2679163-203c-4feb-bdfd-e5a00cd22167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012571982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1012571982
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3876397286
Short name T610
Test name
Test status
Simulation time 2193161221 ps
CPU time 11.84 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 02:56:42 PM PDT 24
Peak memory 324516 kb
Host smart-e2b62c32-0ac3-4e1b-89a1-0b97343dc1e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876397286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3876397286
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1555042656
Short name T323
Test name
Test status
Simulation time 16885679392 ps
CPU time 75.33 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:57:44 PM PDT 24
Peak memory 672336 kb
Host smart-d7e0d3ce-d927-4f8a-b1c1-aaa0c09ba191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555042656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1555042656
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.688172833
Short name T311
Test name
Test status
Simulation time 5943149003 ps
CPU time 102.59 seconds
Started Mar 17 02:56:26 PM PDT 24
Finished Mar 17 02:58:10 PM PDT 24
Peak memory 929184 kb
Host smart-a57d5f7d-5e89-49a2-8ad5-8658968405a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688172833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.688172833
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.179670255
Short name T879
Test name
Test status
Simulation time 440015258 ps
CPU time 0.99 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:56:30 PM PDT 24
Peak memory 202056 kb
Host smart-8b7299b8-9704-49a4-83d9-98fa9588d343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179670255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.179670255
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.232812772
Short name T542
Test name
Test status
Simulation time 169029731 ps
CPU time 9.03 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 02:56:39 PM PDT 24
Peak memory 202696 kb
Host smart-73f73bbd-99d9-4f8f-b974-5df252507d21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232812772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
232812772
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3660507368
Short name T231
Test name
Test status
Simulation time 10360154245 ps
CPU time 406.86 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 03:03:16 PM PDT 24
Peak memory 1469020 kb
Host smart-dce018a1-cfc6-43f8-8754-ca8eb6a49e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660507368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3660507368
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_perf.829463393
Short name T133
Test name
Test status
Simulation time 496759014 ps
CPU time 6.53 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:56:34 PM PDT 24
Peak memory 220276 kb
Host smart-892a50e1-12b8-4fa3-8bdb-f8978e027328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829463393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.829463393
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.772656165
Short name T1097
Test name
Test status
Simulation time 2030645416 ps
CPU time 123.81 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 02:58:34 PM PDT 24
Peak memory 267216 kb
Host smart-08b9f6c3-921b-483d-b1b9-bab58dd2596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772656165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.772656165
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3343993530
Short name T1078
Test name
Test status
Simulation time 1633740191 ps
CPU time 7.73 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:56:36 PM PDT 24
Peak memory 210892 kb
Host smart-f823def7-fe7f-4be7-a799-ad9a7b4d98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343993530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3343993530
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2681999636
Short name T966
Test name
Test status
Simulation time 1062609894 ps
CPU time 4.29 seconds
Started Mar 17 02:56:34 PM PDT 24
Finished Mar 17 02:56:39 PM PDT 24
Peak memory 202672 kb
Host smart-1edcada0-302c-4b39-a1ba-1898ed1091d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681999636 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2681999636
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3185985526
Short name T253
Test name
Test status
Simulation time 10272111076 ps
CPU time 13.55 seconds
Started Mar 17 02:56:32 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 287680 kb
Host smart-ec2bdac1-b1ca-412c-b1b9-b68225efbbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185985526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3185985526
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.709249494
Short name T904
Test name
Test status
Simulation time 10234121437 ps
CPU time 18.98 seconds
Started Mar 17 02:56:35 PM PDT 24
Finished Mar 17 02:56:55 PM PDT 24
Peak memory 351468 kb
Host smart-22ef550b-0541-49ed-b8d6-e0d7b6db1739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709249494 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.709249494
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.387408008
Short name T1232
Test name
Test status
Simulation time 1801755131 ps
CPU time 2.51 seconds
Started Mar 17 02:56:31 PM PDT 24
Finished Mar 17 02:56:34 PM PDT 24
Peak memory 202760 kb
Host smart-5e9843d5-02b3-46f4-9225-ec7ac7d48e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387408008 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.387408008
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2200856447
Short name T485
Test name
Test status
Simulation time 3629787471 ps
CPU time 4.61 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 02:56:34 PM PDT 24
Peak memory 202852 kb
Host smart-80fef8c1-5293-4162-b9e9-b4e18fcc7211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200856447 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2200856447
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2956822788
Short name T500
Test name
Test status
Simulation time 20034139093 ps
CPU time 48.28 seconds
Started Mar 17 02:56:28 PM PDT 24
Finished Mar 17 02:57:17 PM PDT 24
Peak memory 830688 kb
Host smart-687c097d-63ea-4252-8907-bb731d7ea1d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956822788 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2956822788
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.1501686696
Short name T244
Test name
Test status
Simulation time 964555811 ps
CPU time 5.3 seconds
Started Mar 17 02:56:33 PM PDT 24
Finished Mar 17 02:56:38 PM PDT 24
Peak memory 209888 kb
Host smart-c2616831-946b-4d31-bff2-0698266fcc27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501686696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.1501686696
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2627245419
Short name T892
Test name
Test status
Simulation time 1018253711 ps
CPU time 21.59 seconds
Started Mar 17 02:56:26 PM PDT 24
Finished Mar 17 02:56:48 PM PDT 24
Peak memory 202688 kb
Host smart-0e10d9d9-9b2a-444c-9451-fa500f9f9d5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627245419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2627245419
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.82151892
Short name T832
Test name
Test status
Simulation time 27800016921 ps
CPU time 17.68 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:49 PM PDT 24
Peak memory 417308 kb
Host smart-4688a928-4e34-4858-b1c5-63c91ab9c5b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82151892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_wr.82151892
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.241090040
Short name T132
Test name
Test status
Simulation time 7992489983 ps
CPU time 253.74 seconds
Started Mar 17 02:56:29 PM PDT 24
Finished Mar 17 03:00:44 PM PDT 24
Peak memory 1074308 kb
Host smart-c02787c4-6862-4855-9c63-5c632a9032c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241090040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.241090040
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.2428574732
Short name T846
Test name
Test status
Simulation time 1832340004 ps
CPU time 6.94 seconds
Started Mar 17 02:56:27 PM PDT 24
Finished Mar 17 02:56:34 PM PDT 24
Peak memory 206980 kb
Host smart-80057d35-aa21-4d79-aa00-a7a18d1cdecd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428574732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.2428574732
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.768943849
Short name T326
Test name
Test status
Simulation time 90130583 ps
CPU time 0.59 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 02:56:44 PM PDT 24
Peak memory 201612 kb
Host smart-35e57bd5-cf60-4488-b7a5-144827c2d456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768943849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.768943849
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1494758301
Short name T771
Test name
Test status
Simulation time 162291445 ps
CPU time 1.56 seconds
Started Mar 17 02:56:35 PM PDT 24
Finished Mar 17 02:56:37 PM PDT 24
Peak memory 211008 kb
Host smart-31d2542c-9ff6-4609-be94-b7e6d9b5eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494758301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1494758301
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1176966717
Short name T1136
Test name
Test status
Simulation time 1205950689 ps
CPU time 7.67 seconds
Started Mar 17 02:56:35 PM PDT 24
Finished Mar 17 02:56:43 PM PDT 24
Peak memory 274344 kb
Host smart-bb0ad2c1-51e1-4d3b-ba87-0a0c76345b49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176966717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1176966717
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3317474564
Short name T601
Test name
Test status
Simulation time 10647977770 ps
CPU time 149.7 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:59:01 PM PDT 24
Peak memory 733860 kb
Host smart-b2d83c1c-fc14-47d2-b19a-81884862b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317474564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3317474564
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2057915775
Short name T580
Test name
Test status
Simulation time 10078324069 ps
CPU time 82.3 seconds
Started Mar 17 02:56:37 PM PDT 24
Finished Mar 17 02:57:59 PM PDT 24
Peak memory 743952 kb
Host smart-dac42f05-3dbb-4b08-a3c6-49360834c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057915775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2057915775
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3744197699
Short name T1239
Test name
Test status
Simulation time 105092897 ps
CPU time 0.95 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 202468 kb
Host smart-8067c4bc-e8ec-445a-b6df-03237ad22cee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744197699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3744197699
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3468082110
Short name T167
Test name
Test status
Simulation time 1003779724 ps
CPU time 3.61 seconds
Started Mar 17 02:56:32 PM PDT 24
Finished Mar 17 02:56:36 PM PDT 24
Peak memory 202804 kb
Host smart-cd1337f9-2ce5-4933-bd38-e38d58938d33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468082110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3468082110
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3473602983
Short name T788
Test name
Test status
Simulation time 6291562807 ps
CPU time 180.22 seconds
Started Mar 17 02:56:33 PM PDT 24
Finished Mar 17 02:59:33 PM PDT 24
Peak memory 1718820 kb
Host smart-d46aeafb-6d24-45fd-a221-4c797f1c19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473602983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3473602983
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3959723867
Short name T653
Test name
Test status
Simulation time 27248658426 ps
CPU time 128.81 seconds
Started Mar 17 02:56:45 PM PDT 24
Finished Mar 17 02:58:54 PM PDT 24
Peak memory 259632 kb
Host smart-cb61c4b6-16ac-4b5a-9ac2-fa3758a9c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959723867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3959723867
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.999605565
Short name T150
Test name
Test status
Simulation time 32607941 ps
CPU time 0.64 seconds
Started Mar 17 02:56:36 PM PDT 24
Finished Mar 17 02:56:36 PM PDT 24
Peak memory 201896 kb
Host smart-d4b82c34-cd3b-4128-b4e6-2991bfb2f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999605565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.999605565
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2623668913
Short name T24
Test name
Test status
Simulation time 3318179823 ps
CPU time 44.22 seconds
Started Mar 17 02:56:32 PM PDT 24
Finished Mar 17 02:57:16 PM PDT 24
Peak memory 202812 kb
Host smart-1aa85665-cedd-4e17-985c-dfb4370de299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623668913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2623668913
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3766831772
Short name T599
Test name
Test status
Simulation time 1684907869 ps
CPU time 92.94 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 246152 kb
Host smart-507e2e8b-2c9b-47c8-85b6-06171a337052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766831772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3766831772
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3779305467
Short name T1257
Test name
Test status
Simulation time 40703311921 ps
CPU time 959.13 seconds
Started Mar 17 02:56:32 PM PDT 24
Finished Mar 17 03:12:31 PM PDT 24
Peak memory 2912736 kb
Host smart-f56d510d-2075-4467-86d5-9d850725178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779305467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3779305467
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.765862270
Short name T630
Test name
Test status
Simulation time 3703740655 ps
CPU time 14.57 seconds
Started Mar 17 02:56:30 PM PDT 24
Finished Mar 17 02:56:46 PM PDT 24
Peak memory 212044 kb
Host smart-b391dee5-3b85-4bbe-b921-bc203bc9461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765862270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.765862270
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1704412860
Short name T345
Test name
Test status
Simulation time 3883786319 ps
CPU time 4.05 seconds
Started Mar 17 02:56:38 PM PDT 24
Finished Mar 17 02:56:42 PM PDT 24
Peak memory 202808 kb
Host smart-6cc43bc9-9fa2-4ac6-b6a0-69a41ab0414e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704412860 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1704412860
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2056058347
Short name T1177
Test name
Test status
Simulation time 10120338168 ps
CPU time 34.05 seconds
Started Mar 17 02:56:38 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 454808 kb
Host smart-b25cafeb-e1ba-488a-8dd4-a73b174e91dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056058347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2056058347
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3521736517
Short name T1148
Test name
Test status
Simulation time 518891167 ps
CPU time 2.91 seconds
Started Mar 17 02:56:36 PM PDT 24
Finished Mar 17 02:56:39 PM PDT 24
Peak memory 202712 kb
Host smart-5094c8c0-ba6d-4a73-9210-d825d4773bf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521736517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3521736517
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2925076938
Short name T442
Test name
Test status
Simulation time 12650535413 ps
CPU time 5.27 seconds
Started Mar 17 02:56:38 PM PDT 24
Finished Mar 17 02:56:44 PM PDT 24
Peak memory 204960 kb
Host smart-ae77774e-b68d-4989-a3d9-8f61e219f6e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925076938 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2925076938
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.4054165609
Short name T1234
Test name
Test status
Simulation time 6175242798 ps
CPU time 4.53 seconds
Started Mar 17 02:56:37 PM PDT 24
Finished Mar 17 02:56:42 PM PDT 24
Peak memory 202788 kb
Host smart-8bd4ae40-70f5-4998-9c5c-b15bd2188d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054165609 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.4054165609
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.3192639665
Short name T1121
Test name
Test status
Simulation time 4206176033 ps
CPU time 4.07 seconds
Started Mar 17 02:56:37 PM PDT 24
Finished Mar 17 02:56:41 PM PDT 24
Peak memory 207968 kb
Host smart-7837cabc-abf7-4dfd-8111-1c9ecb13f25d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192639665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.3192639665
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1940223702
Short name T1149
Test name
Test status
Simulation time 7429298591 ps
CPU time 34.07 seconds
Started Mar 17 02:56:33 PM PDT 24
Finished Mar 17 02:57:07 PM PDT 24
Peak memory 202776 kb
Host smart-c2695860-cb54-4711-8558-4ce6e07030e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940223702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1940223702
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1504668233
Short name T753
Test name
Test status
Simulation time 19005913455 ps
CPU time 973.17 seconds
Started Mar 17 02:56:36 PM PDT 24
Finished Mar 17 03:12:50 PM PDT 24
Peak memory 4538816 kb
Host smart-137385e6-e225-40e3-949c-c99390e27dfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504668233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1504668233
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2763172871
Short name T953
Test name
Test status
Simulation time 1694960963 ps
CPU time 7.67 seconds
Started Mar 17 02:56:36 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 206776 kb
Host smart-247250cd-d181-4dd3-8ce2-239f29d66abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763172871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2763172871
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.572683885
Short name T717
Test name
Test status
Simulation time 8339019799 ps
CPU time 9.36 seconds
Started Mar 17 02:56:37 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 211812 kb
Host smart-12d4cc65-0423-487b-932e-fc0bedafbc63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572683885 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_unexp_stop.572683885
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3236265007
Short name T478
Test name
Test status
Simulation time 44818810 ps
CPU time 0.61 seconds
Started Mar 17 02:56:46 PM PDT 24
Finished Mar 17 02:56:47 PM PDT 24
Peak memory 201648 kb
Host smart-56a85669-daf8-420b-9a87-6f07560761fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236265007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3236265007
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3237525799
Short name T917
Test name
Test status
Simulation time 239236428 ps
CPU time 1.22 seconds
Started Mar 17 02:56:41 PM PDT 24
Finished Mar 17 02:56:43 PM PDT 24
Peak memory 211184 kb
Host smart-952940b2-8222-4bb3-bf1a-20991ad22af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237525799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3237525799
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2571229320
Short name T1265
Test name
Test status
Simulation time 1507101251 ps
CPU time 5.97 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 02:56:49 PM PDT 24
Peak memory 259280 kb
Host smart-b594251a-f8ee-4bb7-8e4d-d63e442461e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571229320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2571229320
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.755859122
Short name T509
Test name
Test status
Simulation time 14672161126 ps
CPU time 103.1 seconds
Started Mar 17 02:56:41 PM PDT 24
Finished Mar 17 02:58:24 PM PDT 24
Peak memory 839788 kb
Host smart-f6d690e8-7903-4658-8824-ae8e86955bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755859122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.755859122
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.158357703
Short name T368
Test name
Test status
Simulation time 3107912831 ps
CPU time 103.33 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 02:58:26 PM PDT 24
Peak memory 573308 kb
Host smart-e165ac27-b36d-4582-8827-104d1882dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158357703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.158357703
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2321294564
Short name T172
Test name
Test status
Simulation time 352676563 ps
CPU time 0.85 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 202468 kb
Host smart-3a4abdef-ddfe-456c-a4b2-e593c48be9c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321294564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2321294564
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1453259882
Short name T284
Test name
Test status
Simulation time 895593100 ps
CPU time 5.88 seconds
Started Mar 17 02:56:45 PM PDT 24
Finished Mar 17 02:56:51 PM PDT 24
Peak memory 248492 kb
Host smart-f1f45820-05d0-4b37-8695-ef425a506a54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453259882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1453259882
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2682659974
Short name T585
Test name
Test status
Simulation time 4672438067 ps
CPU time 336.38 seconds
Started Mar 17 02:56:46 PM PDT 24
Finished Mar 17 03:02:23 PM PDT 24
Peak memory 1264180 kb
Host smart-90c774fd-8ead-4f12-bfb4-e477167be6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682659974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2682659974
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2932990691
Short name T524
Test name
Test status
Simulation time 7288684589 ps
CPU time 72.29 seconds
Started Mar 17 02:56:42 PM PDT 24
Finished Mar 17 02:57:55 PM PDT 24
Peak memory 329800 kb
Host smart-0a9fab6a-2f39-4ab2-bccf-cc7596b85b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932990691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2932990691
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3285263888
Short name T387
Test name
Test status
Simulation time 25762377 ps
CPU time 0.62 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 02:56:44 PM PDT 24
Peak memory 201836 kb
Host smart-15cf5ef3-ea63-466a-8f0a-4b6be1efd47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285263888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3285263888
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.843008252
Short name T510
Test name
Test status
Simulation time 582362352 ps
CPU time 26.91 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:57:11 PM PDT 24
Peak memory 202756 kb
Host smart-59312ad2-4eec-41f6-aea7-6dc9ec4d5c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843008252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.843008252
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.240837356
Short name T545
Test name
Test status
Simulation time 4317899957 ps
CPU time 134.61 seconds
Started Mar 17 02:56:42 PM PDT 24
Finished Mar 17 02:58:57 PM PDT 24
Peak memory 267832 kb
Host smart-0d812be8-03e3-48cf-83cd-7353c8a3c660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240837356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.240837356
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.3002386565
Short name T193
Test name
Test status
Simulation time 685758068 ps
CPU time 31.24 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:57:16 PM PDT 24
Peak memory 210936 kb
Host smart-bec8ec71-f32d-4338-accb-31dd254bb3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002386565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3002386565
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3568024822
Short name T355
Test name
Test status
Simulation time 634173490 ps
CPU time 3.41 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 02:56:46 PM PDT 24
Peak memory 202784 kb
Host smart-485f8ab2-5d53-43f0-bba2-18db6fe285b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568024822 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3568024822
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3336112677
Short name T804
Test name
Test status
Simulation time 10294758790 ps
CPU time 6.73 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:56:51 PM PDT 24
Peak memory 243076 kb
Host smart-f3d1b8cf-56aa-4d99-9c3b-e61ada6a41e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336112677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3336112677
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3942076467
Short name T181
Test name
Test status
Simulation time 600413112 ps
CPU time 2.79 seconds
Started Mar 17 02:56:46 PM PDT 24
Finished Mar 17 02:56:49 PM PDT 24
Peak memory 202760 kb
Host smart-a0306ee4-a014-4d01-b4fa-0fe0cb6fdf2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942076467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3942076467
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.202746087
Short name T504
Test name
Test status
Simulation time 2696704934 ps
CPU time 5.47 seconds
Started Mar 17 02:56:45 PM PDT 24
Finished Mar 17 02:56:50 PM PDT 24
Peak memory 210084 kb
Host smart-effb8253-ce26-4955-8e9e-520e2d580475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202746087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.202746087
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_perf.4274717127
Short name T725
Test name
Test status
Simulation time 2122081049 ps
CPU time 3.54 seconds
Started Mar 17 02:56:41 PM PDT 24
Finished Mar 17 02:56:45 PM PDT 24
Peak memory 202700 kb
Host smart-03342ecc-846a-4064-8ccd-c3de625ced35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274717127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.4274717127
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2627064375
Short name T1060
Test name
Test status
Simulation time 1762132915 ps
CPU time 26.91 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:57:11 PM PDT 24
Peak memory 202696 kb
Host smart-8ab8acb3-e1d2-4ecd-81c7-82885feae5e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627064375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2627064375
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.694322537
Short name T1041
Test name
Test status
Simulation time 38698152357 ps
CPU time 13.76 seconds
Started Mar 17 02:56:41 PM PDT 24
Finished Mar 17 02:56:56 PM PDT 24
Peak memory 400264 kb
Host smart-2035464d-5e00-4995-bb61-d751d81e1ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694322537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.694322537
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2734907710
Short name T218
Test name
Test status
Simulation time 41155849796 ps
CPU time 1270.7 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 03:17:55 PM PDT 24
Peak memory 4789144 kb
Host smart-87c1a5dd-58d2-4471-b054-7d2d1783c675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734907710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2734907710
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2031704360
Short name T436
Test name
Test status
Simulation time 26832083 ps
CPU time 0.62 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:56:49 PM PDT 24
Peak memory 201544 kb
Host smart-274c0bc9-c484-4dd6-964d-e09ff37f8b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031704360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2031704360
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3737194910
Short name T51
Test name
Test status
Simulation time 245926169 ps
CPU time 1.37 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:56:50 PM PDT 24
Peak memory 211132 kb
Host smart-6dc69f92-8cb1-454b-b826-442845c34f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737194910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3737194910
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3809783705
Short name T333
Test name
Test status
Simulation time 394502911 ps
CPU time 6.54 seconds
Started Mar 17 02:56:47 PM PDT 24
Finished Mar 17 02:56:53 PM PDT 24
Peak memory 279132 kb
Host smart-03920497-88f2-43eb-ab90-11cb4cf4eefe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809783705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3809783705
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1874773394
Short name T1069
Test name
Test status
Simulation time 32351220297 ps
CPU time 131.08 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:58:59 PM PDT 24
Peak memory 1011000 kb
Host smart-68ba46b7-e98b-4a90-804f-c5d6f382a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874773394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1874773394
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2196341286
Short name T317
Test name
Test status
Simulation time 2579390109 ps
CPU time 77.78 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:58:07 PM PDT 24
Peak memory 744884 kb
Host smart-e515238c-2a9e-4767-8db4-a840aace4980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196341286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2196341286
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2834743378
Short name T406
Test name
Test status
Simulation time 407270550 ps
CPU time 0.89 seconds
Started Mar 17 02:56:47 PM PDT 24
Finished Mar 17 02:56:48 PM PDT 24
Peak memory 202440 kb
Host smart-9a3eee53-4af4-4285-a306-f9f353510e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834743378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2834743378
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3017083514
Short name T1241
Test name
Test status
Simulation time 230195924 ps
CPU time 5.5 seconds
Started Mar 17 02:56:47 PM PDT 24
Finished Mar 17 02:56:53 PM PDT 24
Peak memory 202728 kb
Host smart-d39df862-d4e8-4f08-8914-7fcf69eae7ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017083514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3017083514
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1298246419
Short name T1043
Test name
Test status
Simulation time 3939650377 ps
CPU time 248.36 seconds
Started Mar 17 02:56:43 PM PDT 24
Finished Mar 17 03:00:51 PM PDT 24
Peak memory 955704 kb
Host smart-6f10084c-6396-4100-9cb8-227492f0e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298246419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1298246419
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.237815563
Short name T185
Test name
Test status
Simulation time 2297566023 ps
CPU time 75.54 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 233336 kb
Host smart-e03ade87-7616-46c6-8b37-a74a47b65e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237815563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.237815563
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3674543424
Short name T710
Test name
Test status
Simulation time 20432606 ps
CPU time 0.66 seconds
Started Mar 17 02:56:45 PM PDT 24
Finished Mar 17 02:56:46 PM PDT 24
Peak memory 201928 kb
Host smart-c64158d3-281b-49ab-b2c6-3c31cd209afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674543424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3674543424
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.4259866149
Short name T977
Test name
Test status
Simulation time 5421925751 ps
CPU time 287.07 seconds
Started Mar 17 02:56:47 PM PDT 24
Finished Mar 17 03:01:35 PM PDT 24
Peak memory 249984 kb
Host smart-72e2d241-8cbb-44ce-b772-c4205260d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259866149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.4259866149
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2554762305
Short name T245
Test name
Test status
Simulation time 7067785092 ps
CPU time 58.94 seconds
Started Mar 17 02:56:44 PM PDT 24
Finished Mar 17 02:57:43 PM PDT 24
Peak memory 309084 kb
Host smart-adb08033-a68c-46aa-8cf9-9e63c2cb3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554762305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2554762305
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2412855855
Short name T1014
Test name
Test status
Simulation time 7985707567 ps
CPU time 346.96 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 03:02:36 PM PDT 24
Peak memory 1401536 kb
Host smart-a713cd88-120d-4066-b460-a37ba450bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412855855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2412855855
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1543521437
Short name T964
Test name
Test status
Simulation time 3463179056 ps
CPU time 12.54 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:57:02 PM PDT 24
Peak memory 211004 kb
Host smart-3423bf6d-8d0f-4595-9917-8bb2ea2674a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543521437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1543521437
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.832090483
Short name T32
Test name
Test status
Simulation time 1316973799 ps
CPU time 4.71 seconds
Started Mar 17 02:56:46 PM PDT 24
Finished Mar 17 02:56:51 PM PDT 24
Peak memory 202788 kb
Host smart-b7d43ccd-999b-44a2-a395-e79ebc6f42df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832090483 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.832090483
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.926370446
Short name T901
Test name
Test status
Simulation time 10209696676 ps
CPU time 29.64 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:57:17 PM PDT 24
Peak memory 406920 kb
Host smart-c766430f-4c73-4a75-bed6-aa88bb19ed36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926370446 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.926370446
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_perf.2777950171
Short name T322
Test name
Test status
Simulation time 5109624844 ps
CPU time 5.14 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:56:53 PM PDT 24
Peak memory 202728 kb
Host smart-d0f22df2-b4fd-4696-a72c-e3c9e5969883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777950171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.2777950171
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2559501786
Short name T219
Test name
Test status
Simulation time 3833051000 ps
CPU time 9.92 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:56:58 PM PDT 24
Peak memory 202688 kb
Host smart-42fd9684-71e2-4a8c-aa38-93f5e6ed02e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559501786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2559501786
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.981844113
Short name T1211
Test name
Test status
Simulation time 54065305480 ps
CPU time 126.76 seconds
Started Mar 17 02:56:46 PM PDT 24
Finished Mar 17 02:58:53 PM PDT 24
Peak memory 1882096 kb
Host smart-ddad90d7-d6de-4307-9b5f-9dca9b3fca5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981844113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.981844113
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.2549044839
Short name T277
Test name
Test status
Simulation time 38945285754 ps
CPU time 300.79 seconds
Started Mar 17 02:56:47 PM PDT 24
Finished Mar 17 03:01:48 PM PDT 24
Peak memory 1035400 kb
Host smart-5c5288fa-2cb5-4416-a541-f8e6dd60a040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549044839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.2549044839
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1195893842
Short name T869
Test name
Test status
Simulation time 7932723197 ps
CPU time 8.42 seconds
Started Mar 17 02:56:49 PM PDT 24
Finished Mar 17 02:56:58 PM PDT 24
Peak memory 212632 kb
Host smart-8fd9d1c5-cfd5-4739-889e-cb2ff62324db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195893842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1195893842
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.1586748054
Short name T639
Test name
Test status
Simulation time 1392784891 ps
CPU time 4.8 seconds
Started Mar 17 02:56:48 PM PDT 24
Finished Mar 17 02:56:53 PM PDT 24
Peak memory 202616 kb
Host smart-a74406cc-5c11-44a2-86ca-ebf8ab99e8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586748054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.1586748054
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.4157605127
Short name T848
Test name
Test status
Simulation time 17503262 ps
CPU time 0.65 seconds
Started Mar 17 02:57:03 PM PDT 24
Finished Mar 17 02:57:04 PM PDT 24
Peak memory 201660 kb
Host smart-c9f26033-f449-45c2-89c1-1122fd17ca17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157605127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.4157605127
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4256913981
Short name T393
Test name
Test status
Simulation time 93023957 ps
CPU time 1.32 seconds
Started Mar 17 02:56:55 PM PDT 24
Finished Mar 17 02:56:57 PM PDT 24
Peak memory 211020 kb
Host smart-f7c92e51-7f4e-4919-9816-ab10c4316442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256913981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4256913981
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3750876111
Short name T438
Test name
Test status
Simulation time 1189970398 ps
CPU time 5.31 seconds
Started Mar 17 02:56:52 PM PDT 24
Finished Mar 17 02:56:57 PM PDT 24
Peak memory 264172 kb
Host smart-bc4b9b4e-cddb-4adf-b187-d62aa837c5c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750876111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3750876111
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.4169796881
Short name T484
Test name
Test status
Simulation time 1754719162 ps
CPU time 108.44 seconds
Started Mar 17 02:56:53 PM PDT 24
Finished Mar 17 02:58:42 PM PDT 24
Peak memory 511432 kb
Host smart-6134d0b0-c153-4a14-a9a9-58bd0532e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169796881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.4169796881
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.989465930
Short name T874
Test name
Test status
Simulation time 6089779634 ps
CPU time 29.55 seconds
Started Mar 17 02:56:51 PM PDT 24
Finished Mar 17 02:57:20 PM PDT 24
Peak memory 331408 kb
Host smart-576baa13-aee8-4176-8698-689a00fd99c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989465930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.989465930
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1661830135
Short name T975
Test name
Test status
Simulation time 348019959 ps
CPU time 0.87 seconds
Started Mar 17 02:56:53 PM PDT 24
Finished Mar 17 02:56:54 PM PDT 24
Peak memory 202372 kb
Host smart-db7a1f67-a36a-4cc4-9986-f3e66ec9fb34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661830135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1661830135
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.4133562458
Short name T836
Test name
Test status
Simulation time 682846903 ps
CPU time 8.68 seconds
Started Mar 17 02:56:53 PM PDT 24
Finished Mar 17 02:57:02 PM PDT 24
Peak memory 202692 kb
Host smart-3f0807ad-3124-45c6-b1f7-eb6f9c81af28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133562458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.4133562458
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.4260758342
Short name T249
Test name
Test status
Simulation time 11160301620 ps
CPU time 465.52 seconds
Started Mar 17 02:56:55 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 1528208 kb
Host smart-b1b9e854-16f2-48dd-b3cc-7f0c75027761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260758342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4260758342
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2611817882
Short name T1184
Test name
Test status
Simulation time 7392223216 ps
CPU time 146.56 seconds
Started Mar 17 02:56:58 PM PDT 24
Finished Mar 17 02:59:25 PM PDT 24
Peak memory 247044 kb
Host smart-90c9b3ee-a2aa-4e9e-8759-019e519ffa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611817882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2611817882
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.933749159
Short name T1108
Test name
Test status
Simulation time 19964709 ps
CPU time 0.64 seconds
Started Mar 17 02:56:52 PM PDT 24
Finished Mar 17 02:56:54 PM PDT 24
Peak memory 201828 kb
Host smart-6ae2e0dc-7699-413c-a8fa-2f18a166b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933749159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.933749159
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.303812572
Short name T1120
Test name
Test status
Simulation time 3382913109 ps
CPU time 27 seconds
Started Mar 17 02:56:51 PM PDT 24
Finished Mar 17 02:57:18 PM PDT 24
Peak memory 202940 kb
Host smart-93ece66d-2e7e-46c7-82b6-8017ca507b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303812572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.303812572
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3584298636
Short name T1169
Test name
Test status
Simulation time 5628131093 ps
CPU time 33.74 seconds
Started Mar 17 02:56:54 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 260696 kb
Host smart-10efc675-0f2d-42bf-ac61-d9e2ebbf683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584298636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3584298636
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2816265142
Short name T1099
Test name
Test status
Simulation time 57370846174 ps
CPU time 3034.94 seconds
Started Mar 17 02:56:52 PM PDT 24
Finished Mar 17 03:47:28 PM PDT 24
Peak memory 2939348 kb
Host smart-1a519495-6a54-4f31-9459-c7580c0b9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816265142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2816265142
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1068980771
Short name T1032
Test name
Test status
Simulation time 10755733821 ps
CPU time 11.02 seconds
Started Mar 17 02:56:51 PM PDT 24
Finished Mar 17 02:57:02 PM PDT 24
Peak memory 211004 kb
Host smart-56bcd2ec-58b5-4543-a061-2db974a0959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068980771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1068980771
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3426436344
Short name T907
Test name
Test status
Simulation time 904889808 ps
CPU time 4.12 seconds
Started Mar 17 02:56:59 PM PDT 24
Finished Mar 17 02:57:04 PM PDT 24
Peak memory 202712 kb
Host smart-c229d49b-b4d7-4704-b5f4-c05764270fe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426436344 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3426436344
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1788426320
Short name T842
Test name
Test status
Simulation time 10081675395 ps
CPU time 29.94 seconds
Started Mar 17 02:57:03 PM PDT 24
Finished Mar 17 02:57:34 PM PDT 24
Peak memory 399964 kb
Host smart-8715b747-242d-4e58-8a6a-4e7d799351d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788426320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1788426320
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2704024567
Short name T293
Test name
Test status
Simulation time 10322743041 ps
CPU time 3.89 seconds
Started Mar 17 02:56:59 PM PDT 24
Finished Mar 17 02:57:03 PM PDT 24
Peak memory 219164 kb
Host smart-8f611166-6331-4032-b658-75fb6965db03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704024567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2704024567
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1203255500
Short name T1225
Test name
Test status
Simulation time 1202298593 ps
CPU time 2.13 seconds
Started Mar 17 02:56:59 PM PDT 24
Finished Mar 17 02:57:02 PM PDT 24
Peak memory 202756 kb
Host smart-61ab220c-0832-405e-abe6-6f153513f11c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203255500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1203255500
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.461476270
Short name T266
Test name
Test status
Simulation time 1139258640 ps
CPU time 5.33 seconds
Started Mar 17 02:56:52 PM PDT 24
Finished Mar 17 02:56:58 PM PDT 24
Peak memory 203680 kb
Host smart-5c4f0daa-6395-4643-a739-691836c6a768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461476270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.461476270
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3208163331
Short name T762
Test name
Test status
Simulation time 29541844294 ps
CPU time 6.2 seconds
Started Mar 17 02:56:53 PM PDT 24
Finished Mar 17 02:57:00 PM PDT 24
Peak memory 202836 kb
Host smart-d0027f11-ab5a-4482-8989-3b88231b3730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208163331 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3208163331
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.2274294985
Short name T363
Test name
Test status
Simulation time 537167022 ps
CPU time 3.27 seconds
Started Mar 17 02:56:58 PM PDT 24
Finished Mar 17 02:57:01 PM PDT 24
Peak memory 202748 kb
Host smart-dcbe7570-f1ca-43ab-9f21-89ff4a4e6609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274294985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.2274294985
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.136113498
Short name T1198
Test name
Test status
Simulation time 58875298413 ps
CPU time 1755.53 seconds
Started Mar 17 02:56:54 PM PDT 24
Finished Mar 17 03:26:10 PM PDT 24
Peak memory 9478100 kb
Host smart-e6610adc-04a8-4c35-8b7b-1058f13dbcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136113498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.136113498
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2916012751
Short name T584
Test name
Test status
Simulation time 1760597429 ps
CPU time 8.06 seconds
Started Mar 17 02:56:54 PM PDT 24
Finished Mar 17 02:57:02 PM PDT 24
Peak memory 205120 kb
Host smart-75d2442b-8bfa-45aa-8a33-dda5bf7f840f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916012751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2916012751
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.2656921284
Short name T1019
Test name
Test status
Simulation time 5555147764 ps
CPU time 8.24 seconds
Started Mar 17 02:56:58 PM PDT 24
Finished Mar 17 02:57:06 PM PDT 24
Peak memory 202812 kb
Host smart-236ea68a-478e-4e85-99ef-d35c56d9f2a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656921284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.2656921284
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3919350367
Short name T553
Test name
Test status
Simulation time 50685094 ps
CPU time 0.61 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 201648 kb
Host smart-5f23b5a9-c5de-4266-b636-95b39a7d1c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919350367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3919350367
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2205237562
Short name T1035
Test name
Test status
Simulation time 50147519 ps
CPU time 1.38 seconds
Started Mar 17 02:57:07 PM PDT 24
Finished Mar 17 02:57:08 PM PDT 24
Peak memory 210924 kb
Host smart-89834aaf-6b7d-4b8b-a40a-7ca263e88d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205237562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2205237562
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3204760670
Short name T649
Test name
Test status
Simulation time 579106892 ps
CPU time 15.8 seconds
Started Mar 17 02:57:00 PM PDT 24
Finished Mar 17 02:57:16 PM PDT 24
Peak memory 264692 kb
Host smart-5eb29927-40d4-4b3d-a18f-d8679a0538e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204760670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3204760670
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2675021303
Short name T650
Test name
Test status
Simulation time 8055356550 ps
CPU time 116.95 seconds
Started Mar 17 02:57:01 PM PDT 24
Finished Mar 17 02:58:58 PM PDT 24
Peak memory 405760 kb
Host smart-5419d938-8bb1-45b4-b8c8-51d852a0ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675021303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2675021303
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3925614186
Short name T341
Test name
Test status
Simulation time 2957723285 ps
CPU time 89.39 seconds
Started Mar 17 02:57:03 PM PDT 24
Finished Mar 17 02:58:33 PM PDT 24
Peak memory 871812 kb
Host smart-f713952e-8190-43fa-9bba-5af4787d0587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925614186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3925614186
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3021143215
Short name T984
Test name
Test status
Simulation time 104778814 ps
CPU time 1.04 seconds
Started Mar 17 02:57:01 PM PDT 24
Finished Mar 17 02:57:03 PM PDT 24
Peak memory 202460 kb
Host smart-33772256-9aae-458c-9419-89c065ddb312
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021143215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3021143215
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3681320610
Short name T664
Test name
Test status
Simulation time 233694182 ps
CPU time 2.79 seconds
Started Mar 17 02:57:01 PM PDT 24
Finished Mar 17 02:57:04 PM PDT 24
Peak memory 202704 kb
Host smart-a8c19bcc-c320-4355-9999-d6991983bd21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681320610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3681320610
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1772626461
Short name T329
Test name
Test status
Simulation time 46191247301 ps
CPU time 371.26 seconds
Started Mar 17 02:57:01 PM PDT 24
Finished Mar 17 03:03:12 PM PDT 24
Peak memory 1353656 kb
Host smart-51a9db96-e260-445b-8b6a-216b3577beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772626461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1772626461
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1541879760
Short name T242
Test name
Test status
Simulation time 7776537569 ps
CPU time 56.37 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 02:58:10 PM PDT 24
Peak memory 291488 kb
Host smart-7e0f8ade-24fb-40c5-bceb-adfbd17d4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541879760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1541879760
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.642318327
Short name T1155
Test name
Test status
Simulation time 41455587 ps
CPU time 0.65 seconds
Started Mar 17 02:57:04 PM PDT 24
Finished Mar 17 02:57:05 PM PDT 24
Peak memory 201912 kb
Host smart-d4a059b9-60a1-4088-87f7-a524457a54cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642318327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.642318327
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.118218719
Short name T414
Test name
Test status
Simulation time 6784828034 ps
CPU time 56.11 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:58:07 PM PDT 24
Peak memory 202764 kb
Host smart-64a90d74-9814-41ef-8619-a820b8b02d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118218719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.118218719
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3669754157
Short name T372
Test name
Test status
Simulation time 9332833866 ps
CPU time 81.19 seconds
Started Mar 17 02:57:00 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 330504 kb
Host smart-6fb3e6b2-a8e7-45df-ab0f-3093b8715b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669754157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3669754157
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1042421379
Short name T121
Test name
Test status
Simulation time 99505292644 ps
CPU time 536.19 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 03:06:08 PM PDT 24
Peak memory 1727872 kb
Host smart-76263e5f-daad-4183-a8cd-2b62ec0b48e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042421379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1042421379
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1947792004
Short name T996
Test name
Test status
Simulation time 10073184056 ps
CPU time 14.23 seconds
Started Mar 17 02:57:06 PM PDT 24
Finished Mar 17 02:57:21 PM PDT 24
Peak memory 215256 kb
Host smart-5e37a0ba-aaa4-4fba-83a7-962297f8029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947792004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1947792004
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.162317202
Short name T546
Test name
Test status
Simulation time 3183488455 ps
CPU time 3.19 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:15 PM PDT 24
Peak memory 202820 kb
Host smart-a23240ea-6a16-487c-9bcc-9a3d8a8cbbe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162317202 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.162317202
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.632024334
Short name T474
Test name
Test status
Simulation time 10053206406 ps
CPU time 28.68 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:53 PM PDT 24
Peak memory 368232 kb
Host smart-af60bce7-0f2b-4197-aeac-c675d55be8df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632024334 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.632024334
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1043382896
Short name T241
Test name
Test status
Simulation time 10434598826 ps
CPU time 3.97 seconds
Started Mar 17 02:57:10 PM PDT 24
Finished Mar 17 02:57:14 PM PDT 24
Peak memory 236144 kb
Host smart-8d025353-e1ad-47b0-af72-60815a60ad2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043382896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1043382896
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3965727995
Short name T217
Test name
Test status
Simulation time 15647790440 ps
CPU time 3.93 seconds
Started Mar 17 02:57:06 PM PDT 24
Finished Mar 17 02:57:10 PM PDT 24
Peak memory 204564 kb
Host smart-1ca87597-dfb1-4a8a-9acf-289a0a6da648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965727995 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3965727995
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.17661307
Short name T591
Test name
Test status
Simulation time 8424423084 ps
CPU time 5.51 seconds
Started Mar 17 02:57:04 PM PDT 24
Finished Mar 17 02:57:10 PM PDT 24
Peak memory 202692 kb
Host smart-2b252fb2-775f-458a-8685-b6098f549dd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661307 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.17661307
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.3213631235
Short name T658
Test name
Test status
Simulation time 6386302193 ps
CPU time 4.02 seconds
Started Mar 17 02:57:16 PM PDT 24
Finished Mar 17 02:57:20 PM PDT 24
Peak memory 202800 kb
Host smart-700738f2-16b3-4d2a-9c75-730dd69ef134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213631235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.3213631235
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3606592877
Short name T54
Test name
Test status
Simulation time 5204016742 ps
CPU time 37.74 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 202732 kb
Host smart-4d737b0a-ab1c-40f1-add3-a00e82d061b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606592877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3606592877
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3636692083
Short name T648
Test name
Test status
Simulation time 58641886502 ps
CPU time 20.37 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 02:57:34 PM PDT 24
Peak memory 210260 kb
Host smart-afe0dc1f-97b6-474c-9f50-970568b7eb57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636692083 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3636692083
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3271476934
Short name T1186
Test name
Test status
Simulation time 805544341 ps
CPU time 7.44 seconds
Started Mar 17 02:57:07 PM PDT 24
Finished Mar 17 02:57:15 PM PDT 24
Peak memory 202668 kb
Host smart-c350aa1b-e6b7-49a8-8e70-5fc83aa2238d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271476934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3271476934
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3621930744
Short name T274
Test name
Test status
Simulation time 49844301047 ps
CPU time 151.76 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:59:44 PM PDT 24
Peak memory 1946672 kb
Host smart-22acc8a7-c38a-4e24-a061-5161afd49120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621930744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3621930744
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.4272442018
Short name T409
Test name
Test status
Simulation time 14862703418 ps
CPU time 71.21 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:58:23 PM PDT 24
Peak memory 937732 kb
Host smart-8c76e074-51b3-49ca-8bb6-b01e2b3bf40d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272442018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.4272442018
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2787420774
Short name T374
Test name
Test status
Simulation time 15236447257 ps
CPU time 8.38 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 02:57:22 PM PDT 24
Peak memory 214396 kb
Host smart-fac52aec-45e7-43a7-8339-71a313ca38a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787420774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2787420774
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.416975904
Short name T3
Test name
Test status
Simulation time 3561380174 ps
CPU time 6.6 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:57:18 PM PDT 24
Peak memory 202836 kb
Host smart-544fcaa3-1888-485e-8b2e-2157c0f25c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416975904 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_unexp_stop.416975904
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3609328440
Short name T1160
Test name
Test status
Simulation time 15655800 ps
CPU time 0.6 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:26 PM PDT 24
Peak memory 201544 kb
Host smart-344600e4-75c6-4e4b-8e4a-297b97eca76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609328440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3609328440
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3107785089
Short name T525
Test name
Test status
Simulation time 45710441 ps
CPU time 1.25 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 202692 kb
Host smart-edcb8ddb-cce3-4030-b1e4-3e6ee3d42efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107785089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3107785089
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1513209272
Short name T464
Test name
Test status
Simulation time 3666187893 ps
CPU time 5.85 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:57:26 PM PDT 24
Peak memory 246740 kb
Host smart-d6783e43-0db4-4425-a43f-32f539e0d3ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513209272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1513209272
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.707427680
Short name T778
Test name
Test status
Simulation time 3022377182 ps
CPU time 103.01 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:58:55 PM PDT 24
Peak memory 956028 kb
Host smart-be4ea3a4-3709-44bd-a28b-a6a3f57ba338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707427680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.707427680
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3530438581
Short name T820
Test name
Test status
Simulation time 2841418251 ps
CPU time 223.8 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 03:00:55 PM PDT 24
Peak memory 866488 kb
Host smart-2f0240e0-b442-402b-9f58-f2e35623765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530438581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3530438581
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1811977290
Short name T1223
Test name
Test status
Simulation time 325422776 ps
CPU time 0.85 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:13 PM PDT 24
Peak memory 202500 kb
Host smart-bb8b112f-413c-4e0d-88cb-a9f89d442039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811977290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1811977290
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1460177110
Short name T529
Test name
Test status
Simulation time 275011693 ps
CPU time 3.55 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:57:14 PM PDT 24
Peak memory 225024 kb
Host smart-3e222ce1-8d1a-45c2-a025-8f0f60ddc898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460177110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1460177110
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2935662641
Short name T1237
Test name
Test status
Simulation time 4121696353 ps
CPU time 123.43 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 1150288 kb
Host smart-4270b884-3fbf-4db9-bff3-9de37cc516ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935662641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2935662641
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1644719035
Short name T622
Test name
Test status
Simulation time 2027246823 ps
CPU time 102.23 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:59:09 PM PDT 24
Peak memory 233476 kb
Host smart-a1e9eb2b-bf59-4212-aa97-8a40926e9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644719035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1644719035
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3746709482
Short name T1201
Test name
Test status
Simulation time 18529956 ps
CPU time 0.61 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:57:12 PM PDT 24
Peak memory 201864 kb
Host smart-88a87da1-8576-40b8-b17c-84ce64ce3927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746709482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3746709482
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.717958015
Short name T160
Test name
Test status
Simulation time 71628704091 ps
CPU time 2095.3 seconds
Started Mar 17 02:57:19 PM PDT 24
Finished Mar 17 03:32:15 PM PDT 24
Peak memory 398068 kb
Host smart-70014e50-b353-4414-988c-f404afe474ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717958015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.717958015
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2665345515
Short name T936
Test name
Test status
Simulation time 9779541486 ps
CPU time 131.19 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:59:31 PM PDT 24
Peak memory 238208 kb
Host smart-04940012-97c3-4531-9a1b-9d7faeaa5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665345515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2665345515
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3930832136
Short name T126
Test name
Test status
Simulation time 79582075740 ps
CPU time 1229.72 seconds
Started Mar 17 02:57:19 PM PDT 24
Finished Mar 17 03:17:50 PM PDT 24
Peak memory 2087856 kb
Host smart-7cf8d746-bc0d-4cab-ad0a-7c123dee83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930832136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3930832136
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3383159650
Short name T235
Test name
Test status
Simulation time 1387138936 ps
CPU time 35.38 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 210900 kb
Host smart-ceed19dc-ed6e-4ae0-8dfd-2bb064dcde2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383159650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3383159650
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.576800377
Short name T408
Test name
Test status
Simulation time 800749264 ps
CPU time 3.66 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:16 PM PDT 24
Peak memory 202760 kb
Host smart-06a24374-fa8d-4fa8-bb87-8394679a1bce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576800377 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.576800377
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3869891958
Short name T412
Test name
Test status
Simulation time 10116055555 ps
CPU time 34.03 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:58:01 PM PDT 24
Peak memory 444004 kb
Host smart-d67b2bb6-6d05-4cc3-8cdd-fe7cbeed40b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869891958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3869891958
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.4016139433
Short name T1072
Test name
Test status
Simulation time 508316282 ps
CPU time 2.59 seconds
Started Mar 17 02:57:16 PM PDT 24
Finished Mar 17 02:57:19 PM PDT 24
Peak memory 202744 kb
Host smart-b9f7216a-f2ff-45cc-a6e4-9e1cf976a56a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016139433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.4016139433
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1216423591
Short name T1267
Test name
Test status
Simulation time 10040443790 ps
CPU time 4.57 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:57:24 PM PDT 24
Peak memory 203212 kb
Host smart-32997526-df75-494b-ae90-cb4a23bc1fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216423591 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1216423591
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1581538445
Short name T737
Test name
Test status
Simulation time 14441672965 ps
CPU time 129.23 seconds
Started Mar 17 02:57:11 PM PDT 24
Finished Mar 17 02:59:21 PM PDT 24
Peak memory 1669804 kb
Host smart-5f2ed7e6-e9fb-4e07-9df9-df44b782d6b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581538445 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1581538445
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.2977946164
Short name T640
Test name
Test status
Simulation time 1712818290 ps
CPU time 5.51 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 02:57:19 PM PDT 24
Peak memory 207448 kb
Host smart-4425fab9-8e9b-4a31-9868-4540a1789a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977946164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.2977946164
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.2642880829
Short name T933
Test name
Test status
Simulation time 56890846269 ps
CPU time 31.5 seconds
Started Mar 17 02:57:27 PM PDT 24
Finished Mar 17 02:57:59 PM PDT 24
Peak memory 217428 kb
Host smart-f9a9d80e-a9f9-430a-85f2-01160f904520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642880829 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.2642880829
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2668486897
Short name T1262
Test name
Test status
Simulation time 822864459 ps
CPU time 33.9 seconds
Started Mar 17 02:57:10 PM PDT 24
Finished Mar 17 02:57:44 PM PDT 24
Peak memory 202772 kb
Host smart-9724a1c2-29cf-42ee-900f-23fa5fa481be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668486897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2668486897
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4081011798
Short name T337
Test name
Test status
Simulation time 51196083464 ps
CPU time 415.04 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 3926284 kb
Host smart-3bd63448-f5c7-4d18-a481-c1aaedde0a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081011798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4081011798
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.152071627
Short name T291
Test name
Test status
Simulation time 12979850220 ps
CPU time 486.44 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 3232168 kb
Host smart-1adb9e7f-58a9-4bda-8df4-30ce4fd1fc11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152071627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.152071627
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2108345981
Short name T397
Test name
Test status
Simulation time 1782058922 ps
CPU time 7.4 seconds
Started Mar 17 02:57:12 PM PDT 24
Finished Mar 17 02:57:19 PM PDT 24
Peak memory 209196 kb
Host smart-bd05dc83-c1bc-4afb-8f2e-7e80fe5133cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108345981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2108345981
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.3130925862
Short name T283
Test name
Test status
Simulation time 11822294882 ps
CPU time 7.74 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 210064 kb
Host smart-8c4e2c06-528d-4bc0-bb20-4eb20895a317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130925862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.3130925862
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.107347837
Short name T582
Test name
Test status
Simulation time 17411177 ps
CPU time 0.62 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 02:57:23 PM PDT 24
Peak memory 201640 kb
Host smart-3623446d-1732-4d54-85ab-a83032a4b36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107347837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.107347837
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1300106406
Short name T995
Test name
Test status
Simulation time 110302194 ps
CPU time 1.53 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 02:57:23 PM PDT 24
Peak memory 210940 kb
Host smart-3ff3b47f-6ca9-4d99-958b-0fe37d533b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300106406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1300106406
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1120043793
Short name T931
Test name
Test status
Simulation time 1462630021 ps
CPU time 12.14 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 02:57:26 PM PDT 24
Peak memory 247884 kb
Host smart-57a4e83e-626a-4ac4-ab31-a770fafd3c99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120043793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1120043793
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4093219300
Short name T624
Test name
Test status
Simulation time 3309868399 ps
CPU time 114.14 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:59:21 PM PDT 24
Peak memory 994276 kb
Host smart-c5f8e347-d67f-4f43-b009-64f48e586543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093219300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4093219300
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2478827765
Short name T224
Test name
Test status
Simulation time 2051198865 ps
CPU time 59.66 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:58:25 PM PDT 24
Peak memory 711784 kb
Host smart-6470d334-e2ec-4944-aee2-d9e450584658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478827765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2478827765
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.4048108493
Short name T611
Test name
Test status
Simulation time 298867831 ps
CPU time 0.86 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 02:57:15 PM PDT 24
Peak memory 202404 kb
Host smart-d18203c4-6885-4e76-9896-38021a931d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048108493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.4048108493
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1381800794
Short name T416
Test name
Test status
Simulation time 221947626 ps
CPU time 4.98 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:57:31 PM PDT 24
Peak memory 202592 kb
Host smart-f94513b6-8240-41e5-9e6f-a06445761d31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381800794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1381800794
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1425932566
Short name T202
Test name
Test status
Simulation time 11754864446 ps
CPU time 460.87 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 1602864 kb
Host smart-65912954-4a85-49ff-b76d-edfad4a6cfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425932566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1425932566
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4055251197
Short name T1094
Test name
Test status
Simulation time 2638454500 ps
CPU time 42.97 seconds
Started Mar 17 02:57:21 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 239648 kb
Host smart-3d30df0f-09da-4c72-adc4-ef01044f498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055251197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4055251197
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.799166593
Short name T332
Test name
Test status
Simulation time 16167792 ps
CPU time 0.66 seconds
Started Mar 17 02:57:13 PM PDT 24
Finished Mar 17 02:57:14 PM PDT 24
Peak memory 201880 kb
Host smart-554a752f-ac5b-4b0b-97f7-afa9205ca796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799166593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.799166593
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1213286213
Short name T15
Test name
Test status
Simulation time 6310467363 ps
CPU time 61.99 seconds
Started Mar 17 02:57:16 PM PDT 24
Finished Mar 17 02:58:18 PM PDT 24
Peak memory 321700 kb
Host smart-b66ad714-e898-4eb1-8abe-760e96c29139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213286213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1213286213
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.226419524
Short name T431
Test name
Test status
Simulation time 2104773325 ps
CPU time 83.31 seconds
Started Mar 17 02:57:14 PM PDT 24
Finished Mar 17 02:58:37 PM PDT 24
Peak memory 341628 kb
Host smart-c27c2593-4c9b-49be-b73b-e33e66660b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226419524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.226419524
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.727917994
Short name T137
Test name
Test status
Simulation time 61807828535 ps
CPU time 1825.14 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 03:27:48 PM PDT 24
Peak memory 2105988 kb
Host smart-012e1058-4c62-4b0b-8440-5c2416e7083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727917994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.727917994
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1455513679
Short name T813
Test name
Test status
Simulation time 361548312 ps
CPU time 6.71 seconds
Started Mar 17 02:57:21 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 210852 kb
Host smart-280e9f56-a0c5-4a7c-af50-c6f26b4e7f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455513679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1455513679
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3296492194
Short name T456
Test name
Test status
Simulation time 1108027730 ps
CPU time 5.37 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:57:29 PM PDT 24
Peak memory 202712 kb
Host smart-a8f71863-304f-41f2-b74a-bd11813cc5b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296492194 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3296492194
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.275633811
Short name T783
Test name
Test status
Simulation time 10152949076 ps
CPU time 28.26 seconds
Started Mar 17 02:57:21 PM PDT 24
Finished Mar 17 02:57:50 PM PDT 24
Peak memory 385776 kb
Host smart-03ecd783-3f20-4265-b158-b97bed68f0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275633811 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.275633811
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3643471654
Short name T303
Test name
Test status
Simulation time 1537116450 ps
CPU time 4.18 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:57:25 PM PDT 24
Peak memory 202720 kb
Host smart-ed4ee1f9-84f2-4fad-9707-067c3a99d6b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643471654 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3643471654
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1353614194
Short name T988
Test name
Test status
Simulation time 20098799976 ps
CPU time 16.7 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:57:37 PM PDT 24
Peak memory 398260 kb
Host smart-10d0b768-51aa-415b-84eb-4d8dbeeb2cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353614194 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1353614194
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.3127719957
Short name T909
Test name
Test status
Simulation time 2973321844 ps
CPU time 4.63 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 204108 kb
Host smart-3e2206ae-cecb-4930-9d11-e00339d0df50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127719957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.3127719957
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2481526029
Short name T942
Test name
Test status
Simulation time 27751768553 ps
CPU time 116.34 seconds
Started Mar 17 02:57:20 PM PDT 24
Finished Mar 17 02:59:17 PM PDT 24
Peak memory 1921744 kb
Host smart-6137e665-4252-43fc-9bd3-732609f04845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481526029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2481526029
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.706965477
Short name T1047
Test name
Test status
Simulation time 12499642443 ps
CPU time 338.83 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 03:03:01 PM PDT 24
Peak memory 2751532 kb
Host smart-166b0e0c-dbd3-4f63-93b0-ce9f06c685a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706965477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.706965477
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1752941855
Short name T492
Test name
Test status
Simulation time 7048175495 ps
CPU time 7.54 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 02:57:30 PM PDT 24
Peak memory 212744 kb
Host smart-0c62a55b-ddcb-4e6d-9913-9e4c4f827ce6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752941855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1752941855
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.1554448685
Short name T377
Test name
Test status
Simulation time 4686888521 ps
CPU time 6.04 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:57:29 PM PDT 24
Peak memory 211520 kb
Host smart-b3048c54-467e-4fd1-8919-55a98933f426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554448685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.1554448685
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1260389254
Short name T482
Test name
Test status
Simulation time 15045805 ps
CPU time 0.61 seconds
Started Mar 17 02:57:29 PM PDT 24
Finished Mar 17 02:57:30 PM PDT 24
Peak memory 201572 kb
Host smart-047c78b9-758a-4432-9b0b-dcc2bfdb5ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260389254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1260389254
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3013302910
Short name T230
Test name
Test status
Simulation time 314247566 ps
CPU time 1.13 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:26 PM PDT 24
Peak memory 210992 kb
Host smart-6e29abfb-b5af-4dbf-904e-5892df993ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013302910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3013302910
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1740485843
Short name T656
Test name
Test status
Simulation time 312829293 ps
CPU time 16.02 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:57:43 PM PDT 24
Peak memory 266864 kb
Host smart-e4ff207d-e654-45a9-b476-b24f71591b8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740485843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1740485843
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2275751960
Short name T56
Test name
Test status
Simulation time 9824541643 ps
CPU time 65.04 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 02:58:28 PM PDT 24
Peak memory 730888 kb
Host smart-add7b25a-4eb3-48d2-8b45-bdd1feeb1462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275751960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2275751960
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2875502635
Short name T587
Test name
Test status
Simulation time 1756885114 ps
CPU time 48.52 seconds
Started Mar 17 02:57:21 PM PDT 24
Finished Mar 17 02:58:10 PM PDT 24
Peak memory 634080 kb
Host smart-1a4b147e-524c-4f82-af83-d03817875d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875502635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2875502635
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1962339595
Short name T727
Test name
Test status
Simulation time 499428169 ps
CPU time 1.04 seconds
Started Mar 17 02:57:24 PM PDT 24
Finished Mar 17 02:57:25 PM PDT 24
Peak memory 202712 kb
Host smart-b2dea6c8-aadc-4044-972e-4a0709f9500f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962339595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1962339595
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3297368958
Short name T1182
Test name
Test status
Simulation time 1347372894 ps
CPU time 5 seconds
Started Mar 17 02:57:22 PM PDT 24
Finished Mar 17 02:57:27 PM PDT 24
Peak memory 242636 kb
Host smart-bc711a12-7a54-4a53-a2f2-ef40b0d9a8a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297368958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3297368958
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.105545845
Short name T189
Test name
Test status
Simulation time 55682385528 ps
CPU time 424.14 seconds
Started Mar 17 02:57:34 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 1480060 kb
Host smart-41f03459-d171-4c04-8a12-15ebb62a57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105545845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.105545845
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2463641553
Short name T722
Test name
Test status
Simulation time 3371022812 ps
CPU time 43.26 seconds
Started Mar 17 02:57:27 PM PDT 24
Finished Mar 17 02:58:11 PM PDT 24
Peak memory 293184 kb
Host smart-f1ad2f23-e384-472d-9e30-9013bc097978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463641553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2463641553
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1842218745
Short name T151
Test name
Test status
Simulation time 84011433 ps
CPU time 0.65 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:57:23 PM PDT 24
Peak memory 201832 kb
Host smart-18bf0be4-c4a3-4a88-acfd-cb1fba13dadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842218745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1842218745
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3581696404
Short name T265
Test name
Test status
Simulation time 7134381796 ps
CPU time 178.68 seconds
Started Mar 17 02:57:27 PM PDT 24
Finished Mar 17 03:00:26 PM PDT 24
Peak memory 202988 kb
Host smart-971fa772-d5bc-43a6-b915-1ba4d0f704d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581696404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3581696404
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1870644812
Short name T693
Test name
Test status
Simulation time 2138654064 ps
CPU time 65.51 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 295068 kb
Host smart-acea133e-4aef-4ed9-8bc4-b7dac3fe0e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870644812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1870644812
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1622534374
Short name T139
Test name
Test status
Simulation time 12885139520 ps
CPU time 573.21 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 03:06:56 PM PDT 24
Peak memory 2739608 kb
Host smart-7c8e0bc5-84f3-4cd9-a6ae-8dacc1137076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622534374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1622534374
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.769437114
Short name T1212
Test name
Test status
Simulation time 2781578955 ps
CPU time 14.35 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:40 PM PDT 24
Peak memory 217612 kb
Host smart-62a9d6c9-5f99-40b3-b199-3188709d2928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769437114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.769437114
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.240088616
Short name T596
Test name
Test status
Simulation time 3164262274 ps
CPU time 4.06 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:57:30 PM PDT 24
Peak memory 202756 kb
Host smart-2eb944c4-d486-462b-bad1-80095600b780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240088616 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.240088616
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1692212382
Short name T675
Test name
Test status
Simulation time 10075793506 ps
CPU time 33.98 seconds
Started Mar 17 02:57:27 PM PDT 24
Finished Mar 17 02:58:01 PM PDT 24
Peak memory 413688 kb
Host smart-f3b7dc4f-cc84-4041-b389-490ae640c6d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692212382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1692212382
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3232802320
Short name T944
Test name
Test status
Simulation time 10096371018 ps
CPU time 115.86 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 02:59:22 PM PDT 24
Peak memory 699988 kb
Host smart-aa63e72b-c32f-41ce-b2c8-ddc0c362d2e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232802320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3232802320
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.342257170
Short name T447
Test name
Test status
Simulation time 557880603 ps
CPU time 2.86 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 202836 kb
Host smart-e8033b2d-80b0-49e7-b365-6dfe7a72a35e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342257170 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_hrst.342257170
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3373943623
Short name T1052
Test name
Test status
Simulation time 1933275755 ps
CPU time 4.7 seconds
Started Mar 17 02:57:23 PM PDT 24
Finished Mar 17 02:57:28 PM PDT 24
Peak memory 202652 kb
Host smart-48e78205-2749-455c-8f53-9152dff1ee08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373943623 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3373943623
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1285622800
Short name T45
Test name
Test status
Simulation time 14043942526 ps
CPU time 49.65 seconds
Started Mar 17 02:57:24 PM PDT 24
Finished Mar 17 02:58:13 PM PDT 24
Peak memory 962916 kb
Host smart-a8cf289d-8a87-429c-b351-24be2fe12a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285622800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1285622800
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.2086784634
Short name T661
Test name
Test status
Simulation time 2462186508 ps
CPU time 4.13 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:30 PM PDT 24
Peak memory 202784 kb
Host smart-0645a2a3-aadb-432a-99cb-b972c9d1f3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086784634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.2086784634
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2788921830
Short name T645
Test name
Test status
Simulation time 26364234818 ps
CPU time 653.75 seconds
Started Mar 17 02:57:26 PM PDT 24
Finished Mar 17 03:08:20 PM PDT 24
Peak memory 3513644 kb
Host smart-c01b0a4a-e567-4d34-b9cf-72a27e076304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788921830 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2788921830
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3997237355
Short name T557
Test name
Test status
Simulation time 28670698426 ps
CPU time 367.35 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 03:03:32 PM PDT 24
Peak memory 1278296 kb
Host smart-e64dff0b-0207-43e8-a79e-01b074bfdfc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997237355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3997237355
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2381163990
Short name T370
Test name
Test status
Simulation time 5130961942 ps
CPU time 6.2 seconds
Started Mar 17 02:57:25 PM PDT 24
Finished Mar 17 02:57:31 PM PDT 24
Peak memory 208080 kb
Host smart-108e42f4-49e7-4259-983e-2a8ad9fa4e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381163990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2381163990
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.924831578
Short name T728
Test name
Test status
Simulation time 1027537272 ps
CPU time 6.76 seconds
Started Mar 17 02:57:24 PM PDT 24
Finished Mar 17 02:57:30 PM PDT 24
Peak memory 202720 kb
Host smart-caf5f2e1-b618-407f-9d12-ed9a45306983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924831578 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_unexp_stop.924831578
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.143903070
Short name T700
Test name
Test status
Simulation time 17511117 ps
CPU time 0.63 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 201624 kb
Host smart-b8a1f46d-4282-4c2e-9162-aa28596c35e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143903070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.143903070
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3622388923
Short name T1215
Test name
Test status
Simulation time 40002496 ps
CPU time 1.78 seconds
Started Mar 17 02:53:18 PM PDT 24
Finished Mar 17 02:53:20 PM PDT 24
Peak memory 211064 kb
Host smart-74b644da-0ee3-431e-b06f-d4572b5d9a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622388923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3622388923
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.4151821771
Short name T1202
Test name
Test status
Simulation time 620551320 ps
CPU time 31.81 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:54:07 PM PDT 24
Peak memory 340068 kb
Host smart-4699debc-fca5-435c-b316-15e4da9d4aad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151821771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.4151821771
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.69572974
Short name T294
Test name
Test status
Simulation time 2137941183 ps
CPU time 57.09 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:54:36 PM PDT 24
Peak memory 490768 kb
Host smart-52eb9eed-71e7-423e-8625-370daf374608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69572974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.69572974
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2599104025
Short name T530
Test name
Test status
Simulation time 12872492358 ps
CPU time 67.09 seconds
Started Mar 17 02:53:18 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 748668 kb
Host smart-5166e427-39e8-4e6d-85c3-f6bbb2f96ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599104025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2599104025
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2988454798
Short name T692
Test name
Test status
Simulation time 206780914 ps
CPU time 0.91 seconds
Started Mar 17 02:53:18 PM PDT 24
Finished Mar 17 02:53:19 PM PDT 24
Peak memory 202432 kb
Host smart-e3b15fe0-fa77-4e33-acc9-553910eb25b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988454798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2988454798
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3541256918
Short name T548
Test name
Test status
Simulation time 876361136 ps
CPU time 3.71 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 221388 kb
Host smart-358a072c-51fb-499e-8ef4-efc084de308d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541256918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3541256918
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1533161853
Short name T516
Test name
Test status
Simulation time 4422808761 ps
CPU time 131.61 seconds
Started Mar 17 02:53:30 PM PDT 24
Finished Mar 17 02:55:42 PM PDT 24
Peak memory 1258752 kb
Host smart-5242e9a7-b9d4-4375-8e90-813345b61a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533161853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1533161853
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1101551922
Short name T26
Test name
Test status
Simulation time 1944341957 ps
CPU time 92.76 seconds
Started Mar 17 02:53:22 PM PDT 24
Finished Mar 17 02:54:55 PM PDT 24
Peak memory 235224 kb
Host smart-be094169-456e-4076-b852-cfc75e600c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101551922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1101551922
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.908259843
Short name T1117
Test name
Test status
Simulation time 30370917 ps
CPU time 0.65 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:53:16 PM PDT 24
Peak memory 201816 kb
Host smart-7460667d-52a6-4cd9-a364-b2fe6fb03f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908259843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.908259843
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.82826235
Short name T731
Test name
Test status
Simulation time 23801676435 ps
CPU time 1191.75 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 03:13:30 PM PDT 24
Peak memory 210820 kb
Host smart-82c10d39-3acf-42cf-9077-336aeee04c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82826235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.82826235
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1878830627
Short name T1130
Test name
Test status
Simulation time 4242755474 ps
CPU time 31.81 seconds
Started Mar 17 02:53:27 PM PDT 24
Finished Mar 17 02:53:59 PM PDT 24
Peak memory 292360 kb
Host smart-74dda88f-b792-4b63-a858-67ef709b72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878830627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1878830627
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.1477668842
Short name T122
Test name
Test status
Simulation time 17450367232 ps
CPU time 133.1 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:55:30 PM PDT 24
Peak memory 888824 kb
Host smart-76aa7f0b-0aec-46e6-b7a5-046703dad0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477668842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.1477668842
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.122558062
Short name T806
Test name
Test status
Simulation time 1947992247 ps
CPU time 14.33 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:47 PM PDT 24
Peak memory 218788 kb
Host smart-cd16aa3c-493b-43da-93c2-0f75b9218bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122558062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.122558062
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.4265465052
Short name T66
Test name
Test status
Simulation time 67529943 ps
CPU time 0.97 seconds
Started Mar 17 02:53:20 PM PDT 24
Finished Mar 17 02:53:22 PM PDT 24
Peak memory 221072 kb
Host smart-04c84893-d3b2-4efc-9d61-51f02cc2dfd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265465052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.4265465052
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1089488649
Short name T843
Test name
Test status
Simulation time 1162811691 ps
CPU time 4.83 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202708 kb
Host smart-0aac7aba-1775-4904-878e-6cce15b1597f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089488649 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1089488649
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2428646839
Short name T573
Test name
Test status
Simulation time 10428369509 ps
CPU time 11.24 seconds
Started Mar 17 02:53:24 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 283620 kb
Host smart-1e1c60af-9ae3-4f1b-9300-011ef8d405e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428646839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2428646839
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2101448858
Short name T385
Test name
Test status
Simulation time 10053867489 ps
CPU time 39.91 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:54:22 PM PDT 24
Peak memory 470880 kb
Host smart-a8256005-1c2a-48af-92e6-23d1f03a0cc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101448858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2101448858
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3302923743
Short name T182
Test name
Test status
Simulation time 484063562 ps
CPU time 2.59 seconds
Started Mar 17 02:53:25 PM PDT 24
Finished Mar 17 02:53:28 PM PDT 24
Peak memory 202704 kb
Host smart-161aa8a0-63ec-4d2f-b35c-a693f20d794d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302923743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3302923743
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.601922839
Short name T1213
Test name
Test status
Simulation time 3554168613 ps
CPU time 5.16 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:53:42 PM PDT 24
Peak memory 202672 kb
Host smart-6ce55b87-45f6-4106-8afd-fb479d47a656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601922839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.601922839
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1395565350
Short name T1042
Test name
Test status
Simulation time 4475782673 ps
CPU time 10.26 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:53:53 PM PDT 24
Peak memory 202676 kb
Host smart-8e4f5547-9238-4585-8c6e-f2182439a8a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395565350 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1395565350
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.1267681404
Short name T958
Test name
Test status
Simulation time 1290733003 ps
CPU time 4.21 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202728 kb
Host smart-8748f5ba-dea1-446b-b79a-8043af31b0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267681404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.1267681404
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2512139363
Short name T92
Test name
Test status
Simulation time 2341365348 ps
CPU time 14.41 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 202712 kb
Host smart-8a899d35-d94a-4ba5-8313-722e64f80d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512139363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2512139363
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2657607313
Short name T665
Test name
Test status
Simulation time 66441357220 ps
CPU time 194.83 seconds
Started Mar 17 02:53:37 PM PDT 24
Finished Mar 17 02:56:52 PM PDT 24
Peak memory 1220700 kb
Host smart-f07acd42-b2ec-4990-b42e-1954dc5ce4dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657607313 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2657607313
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1013043055
Short name T685
Test name
Test status
Simulation time 705810936 ps
CPU time 30.32 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 202660 kb
Host smart-eb4c0577-7830-40f6-9776-418fe34ea7dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013043055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1013043055
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3573107283
Short name T1207
Test name
Test status
Simulation time 45413017303 ps
CPU time 431.4 seconds
Started Mar 17 02:53:16 PM PDT 24
Finished Mar 17 03:00:29 PM PDT 24
Peak memory 4040488 kb
Host smart-fea0fbe4-407e-4c61-bd1f-f907a1f7cd7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573107283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3573107283
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.4148369652
Short name T538
Test name
Test status
Simulation time 32962378660 ps
CPU time 698.5 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 3742620 kb
Host smart-c6e9eb05-84ad-4d00-8ee1-b7ced1b737ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148369652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.4148369652
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3214931521
Short name T1048
Test name
Test status
Simulation time 3238247658 ps
CPU time 6.64 seconds
Started Mar 17 02:53:40 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 203004 kb
Host smart-86b67444-9b0b-45eb-a22d-f2162ec39a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214931521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3214931521
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.910318327
Short name T444
Test name
Test status
Simulation time 713618510 ps
CPU time 4.74 seconds
Started Mar 17 02:53:24 PM PDT 24
Finished Mar 17 02:53:29 PM PDT 24
Peak memory 202648 kb
Host smart-2c7f7a42-09da-46f8-ac11-d5749eb6e3fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910318327 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_unexp_stop.910318327
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.331790157
Short name T751
Test name
Test status
Simulation time 15192395 ps
CPU time 0.6 seconds
Started Mar 17 02:57:41 PM PDT 24
Finished Mar 17 02:57:41 PM PDT 24
Peak memory 201468 kb
Host smart-ccf808d0-ec54-4083-aca8-d0bb2c9c7a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331790157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.331790157
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3292952359
Short name T721
Test name
Test status
Simulation time 158153085 ps
CPU time 1.3 seconds
Started Mar 17 02:57:27 PM PDT 24
Finished Mar 17 02:57:29 PM PDT 24
Peak memory 210896 kb
Host smart-6d325f56-1fe4-409c-bafc-dd77114f58a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292952359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3292952359
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3037898167
Short name T666
Test name
Test status
Simulation time 4702603801 ps
CPU time 23.53 seconds
Started Mar 17 02:57:28 PM PDT 24
Finished Mar 17 02:57:52 PM PDT 24
Peak memory 294212 kb
Host smart-9a49f453-1617-4b8d-ab81-97a0c5d907c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037898167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3037898167
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.475206136
Short name T1138
Test name
Test status
Simulation time 9702796933 ps
CPU time 218.8 seconds
Started Mar 17 02:57:29 PM PDT 24
Finished Mar 17 03:01:07 PM PDT 24
Peak memory 904572 kb
Host smart-ce989377-9e60-4147-9a14-d8387beae643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475206136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.475206136
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1774699551
Short name T971
Test name
Test status
Simulation time 13279906837 ps
CPU time 151.97 seconds
Started Mar 17 02:57:29 PM PDT 24
Finished Mar 17 03:00:01 PM PDT 24
Peak memory 700092 kb
Host smart-710375a9-a693-4632-84b4-15e8e6c2da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774699551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1774699551
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1481217624
Short name T9
Test name
Test status
Simulation time 135130291 ps
CPU time 1.03 seconds
Started Mar 17 02:57:32 PM PDT 24
Finished Mar 17 02:57:33 PM PDT 24
Peak memory 202368 kb
Host smart-2afaad8b-7484-489c-b645-03d4018038c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481217624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1481217624
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1797760479
Short name T1171
Test name
Test status
Simulation time 353773650 ps
CPU time 10.29 seconds
Started Mar 17 02:57:29 PM PDT 24
Finished Mar 17 02:57:39 PM PDT 24
Peak memory 236612 kb
Host smart-b544406c-b3c9-43af-b801-64cb42e16ecd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797760479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1797760479
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1386012022
Short name T888
Test name
Test status
Simulation time 12336876272 ps
CPU time 183.46 seconds
Started Mar 17 02:57:31 PM PDT 24
Finished Mar 17 03:00:34 PM PDT 24
Peak memory 1726508 kb
Host smart-94461476-ff18-4575-a59b-41b2f5533d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386012022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1386012022
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2905065563
Short name T598
Test name
Test status
Simulation time 5330280727 ps
CPU time 29.03 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 245992 kb
Host smart-9a2b5aa1-d547-4951-a751-38339807f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905065563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2905065563
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1583195309
Short name T468
Test name
Test status
Simulation time 40639808 ps
CPU time 0.63 seconds
Started Mar 17 02:57:28 PM PDT 24
Finished Mar 17 02:57:29 PM PDT 24
Peak memory 201844 kb
Host smart-b3d232bd-d749-4bc1-8702-043bc2152116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583195309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1583195309
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3385764335
Short name T845
Test name
Test status
Simulation time 6594361154 ps
CPU time 38.78 seconds
Started Mar 17 02:57:28 PM PDT 24
Finished Mar 17 02:58:07 PM PDT 24
Peak memory 260832 kb
Host smart-24385d12-cc61-4565-8870-72488510dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385764335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3385764335
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1554768411
Short name T198
Test name
Test status
Simulation time 35151228532 ps
CPU time 2916.09 seconds
Started Mar 17 02:57:33 PM PDT 24
Finished Mar 17 03:46:10 PM PDT 24
Peak memory 3558076 kb
Host smart-b7dab3e5-263c-4082-bc9e-c89e6dc4945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554768411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1554768411
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3259813217
Short name T934
Test name
Test status
Simulation time 529827287 ps
CPU time 8.88 seconds
Started Mar 17 02:57:30 PM PDT 24
Finished Mar 17 02:57:39 PM PDT 24
Peak memory 210976 kb
Host smart-ada96807-97d0-4626-bf09-f473808cc1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259813217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3259813217
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1133767373
Short name T878
Test name
Test status
Simulation time 5755813099 ps
CPU time 5.54 seconds
Started Mar 17 02:57:41 PM PDT 24
Finished Mar 17 02:57:47 PM PDT 24
Peak memory 202772 kb
Host smart-c3908ecc-4241-4de4-ba45-097794eb543d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133767373 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1133767373
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1050234602
Short name T1110
Test name
Test status
Simulation time 10310668555 ps
CPU time 14.25 seconds
Started Mar 17 02:57:34 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 337024 kb
Host smart-63f3a814-3f75-4f5f-a1ac-d65c8f499fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050234602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1050234602
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4186501341
Short name T894
Test name
Test status
Simulation time 10692476543 ps
CPU time 10.73 seconds
Started Mar 17 02:57:35 PM PDT 24
Finished Mar 17 02:57:46 PM PDT 24
Peak memory 283948 kb
Host smart-c52c23fd-ced1-4169-a6f3-bf4aa462df52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186501341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4186501341
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1300923977
Short name T983
Test name
Test status
Simulation time 1362165114 ps
CPU time 2.51 seconds
Started Mar 17 02:57:38 PM PDT 24
Finished Mar 17 02:57:41 PM PDT 24
Peak memory 202704 kb
Host smart-738ff005-0318-4c14-8a0a-2e5ec3460c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300923977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1300923977
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1554102093
Short name T452
Test name
Test status
Simulation time 10727409655 ps
CPU time 52.22 seconds
Started Mar 17 02:57:37 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 1013140 kb
Host smart-2ecdce1b-5b1d-4e82-90f5-74b8ecca11b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554102093 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1554102093
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.2730723371
Short name T396
Test name
Test status
Simulation time 411383552 ps
CPU time 2.91 seconds
Started Mar 17 02:57:34 PM PDT 24
Finished Mar 17 02:57:37 PM PDT 24
Peak memory 202732 kb
Host smart-d3d1636d-cd29-4352-9ac0-a57167935681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730723371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.2730723371
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.770348086
Short name T576
Test name
Test status
Simulation time 109006509241 ps
CPU time 30.27 seconds
Started Mar 17 02:57:36 PM PDT 24
Finished Mar 17 02:58:06 PM PDT 24
Peak memory 216948 kb
Host smart-23e5ac13-b38e-49c1-9a8f-62f4bb8e9780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770348086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_stress_all.770348086
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3787565548
Short name T935
Test name
Test status
Simulation time 33998563337 ps
CPU time 281.06 seconds
Started Mar 17 02:57:35 PM PDT 24
Finished Mar 17 03:02:16 PM PDT 24
Peak memory 3380436 kb
Host smart-8788be3a-7e25-456a-836a-3cb8a8bd58b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787565548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3787565548
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1986873939
Short name T597
Test name
Test status
Simulation time 5661100132 ps
CPU time 6.65 seconds
Started Mar 17 02:57:35 PM PDT 24
Finished Mar 17 02:57:42 PM PDT 24
Peak memory 202816 kb
Host smart-16148af7-d546-46a5-9ea8-6f4b89ac8a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986873939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1986873939
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.4059479510
Short name T678
Test name
Test status
Simulation time 1113537404 ps
CPU time 5.14 seconds
Started Mar 17 02:57:34 PM PDT 24
Finished Mar 17 02:57:40 PM PDT 24
Peak memory 202804 kb
Host smart-4cacac2f-43aa-407d-b185-ad04e5793053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059479510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.4059479510
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.4034269629
Short name T511
Test name
Test status
Simulation time 69213341 ps
CPU time 0.6 seconds
Started Mar 17 02:57:47 PM PDT 24
Finished Mar 17 02:57:48 PM PDT 24
Peak memory 201568 kb
Host smart-b7e8617e-9146-4e9e-af29-b280c2891371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034269629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.4034269629
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.95450230
Short name T858
Test name
Test status
Simulation time 92927915 ps
CPU time 1.36 seconds
Started Mar 17 02:57:41 PM PDT 24
Finished Mar 17 02:57:42 PM PDT 24
Peak memory 213020 kb
Host smart-2e32af63-519c-4bf9-8051-33f57cafb2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95450230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.95450230
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3465509629
Short name T1210
Test name
Test status
Simulation time 565855825 ps
CPU time 11.62 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 303384 kb
Host smart-710367de-586b-49e7-bbb8-c6edfeabfe99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465509629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3465509629
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1017644252
Short name T558
Test name
Test status
Simulation time 10714711236 ps
CPU time 73.15 seconds
Started Mar 17 02:57:38 PM PDT 24
Finished Mar 17 02:58:52 PM PDT 24
Peak memory 699204 kb
Host smart-40db72f4-5808-4204-a4ef-376208efde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017644252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1017644252
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.832520799
Short name T955
Test name
Test status
Simulation time 1852843611 ps
CPU time 132.61 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:59:52 PM PDT 24
Peak memory 662756 kb
Host smart-c5630a4a-ffab-4a44-99ff-62381196fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832520799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.832520799
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1323842244
Short name T310
Test name
Test status
Simulation time 358679195 ps
CPU time 0.84 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:57:40 PM PDT 24
Peak memory 202496 kb
Host smart-30576977-5a5f-4527-919e-0b3daf8dde64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323842244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1323842244
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2936501985
Short name T407
Test name
Test status
Simulation time 879733997 ps
CPU time 4.16 seconds
Started Mar 17 02:57:37 PM PDT 24
Finished Mar 17 02:57:41 PM PDT 24
Peak memory 228104 kb
Host smart-9284abec-271f-4763-9ddb-dd50bfa31c0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936501985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2936501985
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1530151927
Short name T607
Test name
Test status
Simulation time 50073371990 ps
CPU time 191.54 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 03:00:51 PM PDT 24
Peak memory 1603448 kb
Host smart-7648b62a-28c2-49c9-9cc7-be42da29d74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530151927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1530151927
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1929712154
Short name T1023
Test name
Test status
Simulation time 2557712033 ps
CPU time 55.45 seconds
Started Mar 17 02:57:42 PM PDT 24
Finished Mar 17 02:58:38 PM PDT 24
Peak memory 294756 kb
Host smart-8b1a3418-e635-4e9b-9024-6df963f5e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929712154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1929712154
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.785681833
Short name T1061
Test name
Test status
Simulation time 86449190 ps
CPU time 0.64 seconds
Started Mar 17 02:57:40 PM PDT 24
Finished Mar 17 02:57:41 PM PDT 24
Peak memory 201796 kb
Host smart-0b426b1f-abce-40d1-b39a-98a3f8d918c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785681833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.785681833
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2299617901
Short name T1248
Test name
Test status
Simulation time 2794970923 ps
CPU time 62.22 seconds
Started Mar 17 02:57:41 PM PDT 24
Finished Mar 17 02:58:43 PM PDT 24
Peak memory 264424 kb
Host smart-be25dfc0-c9d7-4872-a6d7-f8e4b585fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299617901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2299617901
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3644829080
Short name T866
Test name
Test status
Simulation time 2308795094 ps
CPU time 87.72 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:59:07 PM PDT 24
Peak memory 312484 kb
Host smart-2f30671d-ce2b-484f-bac9-7a6f03c9bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644829080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3644829080
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.1709828712
Short name T1192
Test name
Test status
Simulation time 39519890610 ps
CPU time 2164.3 seconds
Started Mar 17 02:57:41 PM PDT 24
Finished Mar 17 03:33:45 PM PDT 24
Peak memory 2874204 kb
Host smart-9e41b679-fff8-4543-a298-de10d175bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709828712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1709828712
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3653957183
Short name T758
Test name
Test status
Simulation time 548482847 ps
CPU time 22.38 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:58:02 PM PDT 24
Peak memory 210912 kb
Host smart-ab26f2ad-6b9a-4c2f-b1db-bfb9e1650326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653957183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3653957183
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3492889077
Short name T31
Test name
Test status
Simulation time 2488746746 ps
CPU time 5.18 seconds
Started Mar 17 02:57:43 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 202840 kb
Host smart-c08eb3cb-1391-4252-b529-b15dd50a3eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492889077 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3492889077
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2197094445
Short name T272
Test name
Test status
Simulation time 10176464285 ps
CPU time 70.35 seconds
Started Mar 17 02:57:46 PM PDT 24
Finished Mar 17 02:58:56 PM PDT 24
Peak memory 532436 kb
Host smart-f8a5fe9a-2912-49db-9428-bfbd58c514ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197094445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2197094445
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1901315807
Short name T1098
Test name
Test status
Simulation time 626340253 ps
CPU time 2.77 seconds
Started Mar 17 02:57:44 PM PDT 24
Finished Mar 17 02:57:47 PM PDT 24
Peak memory 202736 kb
Host smart-4cb61424-9339-41f5-a698-a86b81fcd370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901315807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1901315807
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3346370530
Short name T455
Test name
Test status
Simulation time 3676001382 ps
CPU time 4.26 seconds
Started Mar 17 02:57:39 PM PDT 24
Finished Mar 17 02:57:44 PM PDT 24
Peak memory 204048 kb
Host smart-b42889bd-da9a-459c-abe0-3088fbecd492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346370530 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3346370530
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2384961506
Short name T723
Test name
Test status
Simulation time 6011894967 ps
CPU time 13.48 seconds
Started Mar 17 02:57:43 PM PDT 24
Finished Mar 17 02:57:57 PM PDT 24
Peak memory 202792 kb
Host smart-f4df8f08-70ed-4eb2-8052-f6017b2a6754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384961506 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2384961506
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.3213448331
Short name T769
Test name
Test status
Simulation time 449277797 ps
CPU time 3.03 seconds
Started Mar 17 02:57:44 PM PDT 24
Finished Mar 17 02:57:47 PM PDT 24
Peak memory 202744 kb
Host smart-5e0fbe38-d175-4c59-a256-c98ccc530c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213448331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.3213448331
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.311275516
Short name T1007
Test name
Test status
Simulation time 43935901579 ps
CPU time 481.4 seconds
Started Mar 17 02:57:43 PM PDT 24
Finished Mar 17 03:05:45 PM PDT 24
Peak memory 3035516 kb
Host smart-a405e7b7-6136-40d5-823d-9a1c5a699e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311275516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_stress_all.311275516
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3881868427
Short name T1145
Test name
Test status
Simulation time 32927986795 ps
CPU time 100.89 seconds
Started Mar 17 02:57:40 PM PDT 24
Finished Mar 17 02:59:21 PM PDT 24
Peak memory 1616516 kb
Host smart-61cf1397-4f2c-4b91-820e-e0e0260a1523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881868427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3881868427
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3615537
Short name T1020
Test name
Test status
Simulation time 10028521998 ps
CPU time 169.84 seconds
Started Mar 17 02:57:40 PM PDT 24
Finished Mar 17 03:00:30 PM PDT 24
Peak memory 1687560 kb
Host smart-760a6c5a-31f7-4bf2-80a7-8249bed236b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_stretch.3615537
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3446479470
Short name T724
Test name
Test status
Simulation time 5634976262 ps
CPU time 6.1 seconds
Started Mar 17 02:57:42 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 209360 kb
Host smart-1243b5f2-90c8-412c-9b53-bee8fa5417f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446479470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3446479470
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.3430104453
Short name T765
Test name
Test status
Simulation time 1026385782 ps
CPU time 4.94 seconds
Started Mar 17 02:57:44 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 202872 kb
Host smart-dedc5cd1-faae-457f-a951-6a1792886f31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430104453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.3430104453
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.800415249
Short name T234
Test name
Test status
Simulation time 42238986 ps
CPU time 0.58 seconds
Started Mar 17 02:57:52 PM PDT 24
Finished Mar 17 02:57:53 PM PDT 24
Peak memory 201624 kb
Host smart-c1bed8be-b85f-45a0-8cf6-eaf385d02886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800415249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.800415249
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.964805304
Short name T49
Test name
Test status
Simulation time 48053474 ps
CPU time 1.56 seconds
Started Mar 17 02:57:49 PM PDT 24
Finished Mar 17 02:57:50 PM PDT 24
Peak memory 210908 kb
Host smart-4d40fdda-d651-416c-9ef0-d77214f37c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964805304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.964805304
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3901020210
Short name T330
Test name
Test status
Simulation time 1592330774 ps
CPU time 6.49 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:57:58 PM PDT 24
Peak memory 284796 kb
Host smart-ab9154d4-b6d0-4e34-9eb4-46039ca9ef4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901020210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3901020210
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1147251843
Short name T1197
Test name
Test status
Simulation time 2566181352 ps
CPU time 176.51 seconds
Started Mar 17 02:57:45 PM PDT 24
Finished Mar 17 03:00:42 PM PDT 24
Peak memory 768668 kb
Host smart-e145073d-2037-4f16-983a-0c7fb6a56a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147251843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1147251843
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.800457702
Short name T319
Test name
Test status
Simulation time 3171397073 ps
CPU time 45.4 seconds
Started Mar 17 02:57:45 PM PDT 24
Finished Mar 17 02:58:31 PM PDT 24
Peak memory 597440 kb
Host smart-b711ec93-93c9-487f-ae25-c7d8ac4af4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800457702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.800457702
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1649811577
Short name T1091
Test name
Test status
Simulation time 599734463 ps
CPU time 1.16 seconds
Started Mar 17 02:57:47 PM PDT 24
Finished Mar 17 02:57:49 PM PDT 24
Peak memory 202700 kb
Host smart-6ec0f4e0-e256-4ea3-a099-c1816507004c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649811577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1649811577
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.4255817166
Short name T908
Test name
Test status
Simulation time 425829471 ps
CPU time 6.42 seconds
Started Mar 17 02:57:45 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 219852 kb
Host smart-be7a5386-1fb6-4711-bafa-b5fa047e08d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255817166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.4255817166
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3789328808
Short name T623
Test name
Test status
Simulation time 10989713874 ps
CPU time 441.86 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 03:05:13 PM PDT 24
Peak memory 1466968 kb
Host smart-4caadfde-0ca8-40d6-9fb8-16b47c281e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789328808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3789328808
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3758287269
Short name T343
Test name
Test status
Simulation time 8087083123 ps
CPU time 47.36 seconds
Started Mar 17 02:57:52 PM PDT 24
Finished Mar 17 02:58:40 PM PDT 24
Peak memory 247208 kb
Host smart-1e2fa0a9-f9bd-49f1-9be9-4fac1b86cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758287269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3758287269
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.240581796
Short name T6
Test name
Test status
Simulation time 19378251 ps
CPU time 0.71 seconds
Started Mar 17 02:57:48 PM PDT 24
Finished Mar 17 02:57:48 PM PDT 24
Peak memory 201956 kb
Host smart-4f4590e8-8731-43ae-8a34-00126b4c4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240581796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.240581796
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.409267780
Short name T349
Test name
Test status
Simulation time 1195924708 ps
CPU time 21.14 seconds
Started Mar 17 02:57:46 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 202692 kb
Host smart-bba15281-3abb-4f97-a4a8-a6174c2f49e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409267780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.409267780
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4053919835
Short name T796
Test name
Test status
Simulation time 9262925351 ps
CPU time 44.99 seconds
Started Mar 17 02:57:49 PM PDT 24
Finished Mar 17 02:58:34 PM PDT 24
Peak memory 251136 kb
Host smart-05e6548c-5d82-4875-b439-0fb828961ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053919835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4053919835
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1382129920
Short name T347
Test name
Test status
Simulation time 25737253402 ps
CPU time 1865.48 seconds
Started Mar 17 02:57:50 PM PDT 24
Finished Mar 17 03:28:56 PM PDT 24
Peak memory 2703496 kb
Host smart-1954fa84-8d86-4049-968d-88fc2fb27f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382129920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1382129920
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1310741234
Short name T952
Test name
Test status
Simulation time 2317241823 ps
CPU time 13.61 seconds
Started Mar 17 02:57:46 PM PDT 24
Finished Mar 17 02:58:00 PM PDT 24
Peak memory 227376 kb
Host smart-008099f7-6e35-48d7-abe6-6edc64bd8364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310741234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1310741234
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3463137143
Short name T657
Test name
Test status
Simulation time 3372410134 ps
CPU time 4.37 seconds
Started Mar 17 02:57:50 PM PDT 24
Finished Mar 17 02:57:54 PM PDT 24
Peak memory 202696 kb
Host smart-92d9e7ca-064d-478c-9c17-800c1c5b7c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463137143 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3463137143
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.7122987
Short name T263
Test name
Test status
Simulation time 10049076718 ps
CPU time 33.08 seconds
Started Mar 17 02:57:50 PM PDT 24
Finished Mar 17 02:58:24 PM PDT 24
Peak memory 362280 kb
Host smart-e1dd03fb-1a13-4017-8a14-519fcb94a8f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7122987 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_fifo_reset_acq.7122987
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3684603942
Short name T616
Test name
Test status
Simulation time 1707895766 ps
CPU time 2.62 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:57:53 PM PDT 24
Peak memory 202668 kb
Host smart-4cadb1c9-7c19-4998-9856-21675d8a613e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684603942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3684603942
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3014519852
Short name T339
Test name
Test status
Simulation time 1019377921 ps
CPU time 5.09 seconds
Started Mar 17 02:57:47 PM PDT 24
Finished Mar 17 02:57:53 PM PDT 24
Peak memory 203844 kb
Host smart-7522a93d-efe3-43ad-96b6-2b6523629862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014519852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3014519852
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1767359673
Short name T255
Test name
Test status
Simulation time 3497284224 ps
CPU time 2.87 seconds
Started Mar 17 02:57:48 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 202660 kb
Host smart-1cba7108-fa91-4460-b330-56aa73d3862f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767359673 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1767359673
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.3577740509
Short name T744
Test name
Test status
Simulation time 1208958133 ps
CPU time 2.16 seconds
Started Mar 17 02:57:52 PM PDT 24
Finished Mar 17 02:57:55 PM PDT 24
Peak memory 202752 kb
Host smart-733a7e94-c172-46ef-ace9-666aff0d6908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577740509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.3577740509
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2385358147
Short name T963
Test name
Test status
Simulation time 2122675430 ps
CPU time 28.18 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:58:19 PM PDT 24
Peak memory 202660 kb
Host smart-0a48f3d0-2d22-4b11-93fd-199631f75ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385358147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2385358147
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1020853279
Short name T1220
Test name
Test status
Simulation time 39834541039 ps
CPU time 820.41 seconds
Started Mar 17 02:57:52 PM PDT 24
Finished Mar 17 03:11:33 PM PDT 24
Peak memory 3519320 kb
Host smart-679ac558-fb41-4929-9ab3-171aaf5d7965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020853279 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1020853279
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2486943840
Short name T225
Test name
Test status
Simulation time 661284373 ps
CPU time 11.58 seconds
Started Mar 17 02:57:47 PM PDT 24
Finished Mar 17 02:57:59 PM PDT 24
Peak memory 203940 kb
Host smart-01fe25bc-648c-40ec-98d5-46819354813a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486943840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2486943840
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.4206429076
Short name T756
Test name
Test status
Simulation time 57349704258 ps
CPU time 997.54 seconds
Started Mar 17 02:57:48 PM PDT 24
Finished Mar 17 03:14:25 PM PDT 24
Peak memory 6335272 kb
Host smart-3d4866a5-4ed0-4471-98a7-28d5cb9b173f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206429076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.4206429076
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1321700335
Short name T55
Test name
Test status
Simulation time 18295710714 ps
CPU time 2706.25 seconds
Started Mar 17 02:57:47 PM PDT 24
Finished Mar 17 03:42:54 PM PDT 24
Peak memory 4454204 kb
Host smart-d3f69b16-1d0d-43a7-8504-8ae44a33eeeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321700335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1321700335
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3463896179
Short name T889
Test name
Test status
Simulation time 1469619292 ps
CPU time 7.26 seconds
Started Mar 17 02:57:46 PM PDT 24
Finished Mar 17 02:57:53 PM PDT 24
Peak memory 202732 kb
Host smart-829f89e7-3a27-42e7-ae6a-048b8383c6c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463896179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3463896179
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.80699605
Short name T1057
Test name
Test status
Simulation time 809169829 ps
CPU time 4.73 seconds
Started Mar 17 02:57:49 PM PDT 24
Finished Mar 17 02:57:54 PM PDT 24
Peak memory 203208 kb
Host smart-d31c8160-b71f-4a79-a299-c24f3d78e8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80699605 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_unexp_stop.80699605
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1881802063
Short name T1168
Test name
Test status
Simulation time 16210246 ps
CPU time 0.68 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 201516 kb
Host smart-7fde892e-7fe2-459e-9205-43f5d34bab1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881802063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1881802063
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4165329309
Short name T498
Test name
Test status
Simulation time 111654968 ps
CPU time 1.62 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 02:57:59 PM PDT 24
Peak memory 210984 kb
Host smart-6e6f5cfa-3f9f-41fa-950c-1c17e2f760e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165329309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4165329309
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1262434965
Short name T1176
Test name
Test status
Simulation time 296608219 ps
CPU time 15.15 seconds
Started Mar 17 02:57:52 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 264208 kb
Host smart-a5b3d190-95e1-4545-9f6d-abff61e63ca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262434965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1262434965
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3689036460
Short name T395
Test name
Test status
Simulation time 4039335781 ps
CPU time 51.98 seconds
Started Mar 17 02:57:56 PM PDT 24
Finished Mar 17 02:58:49 PM PDT 24
Peak memory 600432 kb
Host smart-bda11f36-da95-483b-a90e-f1938d09051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689036460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3689036460
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1367827745
Short name T841
Test name
Test status
Simulation time 2543537513 ps
CPU time 175.66 seconds
Started Mar 17 02:57:54 PM PDT 24
Finished Mar 17 03:00:50 PM PDT 24
Peak memory 684740 kb
Host smart-ff0a1129-e19c-4179-aa60-cd95683d2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367827745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1367827745
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2099942425
Short name T1124
Test name
Test status
Simulation time 236210247 ps
CPU time 1.01 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:57:52 PM PDT 24
Peak memory 202492 kb
Host smart-241ce488-ce22-4162-9aa6-2afd5ae1001b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099942425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2099942425
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.105430240
Short name T278
Test name
Test status
Simulation time 785682070 ps
CPU time 10.31 seconds
Started Mar 17 02:57:53 PM PDT 24
Finished Mar 17 02:58:03 PM PDT 24
Peak memory 202708 kb
Host smart-b16989a8-1c61-4e90-a85b-55a4bc313b04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105430240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
105430240
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2317631080
Short name T586
Test name
Test status
Simulation time 10600309285 ps
CPU time 55.35 seconds
Started Mar 17 02:58:01 PM PDT 24
Finished Mar 17 02:58:57 PM PDT 24
Peak memory 342024 kb
Host smart-87460618-3343-4e59-bb9a-683a64ba2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317631080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2317631080
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2176498153
Short name T950
Test name
Test status
Simulation time 35195291 ps
CPU time 0.59 seconds
Started Mar 17 02:57:50 PM PDT 24
Finished Mar 17 02:57:51 PM PDT 24
Peak memory 201868 kb
Host smart-2a78af92-d50d-4642-98a1-afffa02233c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176498153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2176498153
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2044936579
Short name T593
Test name
Test status
Simulation time 5316262195 ps
CPU time 159.01 seconds
Started Mar 17 02:57:58 PM PDT 24
Finished Mar 17 03:00:37 PM PDT 24
Peak memory 354196 kb
Host smart-2be5a2cc-e385-430c-9cea-7a7faa25dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044936579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2044936579
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1401275971
Short name T672
Test name
Test status
Simulation time 3055897733 ps
CPU time 78.26 seconds
Started Mar 17 02:57:51 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 218860 kb
Host smart-aee50e86-b9ae-41cb-b04a-dbf5b4e4ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401275971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1401275971
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.97622882
Short name T741
Test name
Test status
Simulation time 35885089055 ps
CPU time 706.62 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 03:09:44 PM PDT 24
Peak memory 946724 kb
Host smart-06fe997f-d9f8-4845-82f7-21df7770acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97622882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.97622882
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.408662047
Short name T531
Test name
Test status
Simulation time 2251796942 ps
CPU time 35.59 seconds
Started Mar 17 02:57:58 PM PDT 24
Finished Mar 17 02:58:34 PM PDT 24
Peak memory 210924 kb
Host smart-a9aea179-d1af-44cf-8ab9-7beed851d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408662047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.408662047
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1265751159
Short name T413
Test name
Test status
Simulation time 3101008356 ps
CPU time 4.83 seconds
Started Mar 17 02:57:56 PM PDT 24
Finished Mar 17 02:58:02 PM PDT 24
Peak memory 202944 kb
Host smart-48b3d271-0bac-4412-8e74-9a60c0082c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265751159 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1265751159
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1763507368
Short name T213
Test name
Test status
Simulation time 10165339109 ps
CPU time 12.29 seconds
Started Mar 17 02:57:58 PM PDT 24
Finished Mar 17 02:58:11 PM PDT 24
Peak memory 293136 kb
Host smart-a0ccdc30-cff1-4743-8c74-57b704cd4fe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763507368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1763507368
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.627390813
Short name T759
Test name
Test status
Simulation time 10119014777 ps
CPU time 41.89 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 02:58:39 PM PDT 24
Peak memory 529560 kb
Host smart-c94a220c-fa85-41e5-b133-54eeb79baf82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627390813 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.627390813
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.795507709
Short name T910
Test name
Test status
Simulation time 3610699466 ps
CPU time 2.72 seconds
Started Mar 17 02:58:04 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 202872 kb
Host smart-c7b6ae73-e841-431d-b731-abcf1ba19fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795507709 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.795507709
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2196402356
Short name T1261
Test name
Test status
Simulation time 18693397258 ps
CPU time 92.11 seconds
Started Mar 17 02:57:59 PM PDT 24
Finished Mar 17 02:59:31 PM PDT 24
Peak memory 1336396 kb
Host smart-f6c92244-1520-4ec5-8e53-650ee7d48e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196402356 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2196402356
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.495218698
Short name T928
Test name
Test status
Simulation time 796638593 ps
CPU time 5 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 02:58:03 PM PDT 24
Peak memory 205388 kb
Host smart-a52ef3be-0705-4d1d-819d-b662d5ff08f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495218698 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_perf.495218698
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.3140634411
Short name T563
Test name
Test status
Simulation time 10281135557 ps
CPU time 42.93 seconds
Started Mar 17 02:57:58 PM PDT 24
Finished Mar 17 02:58:41 PM PDT 24
Peak memory 220776 kb
Host smart-fc8cf379-16de-4345-8701-e34f4fcf2879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140634411 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.3140634411
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1349536091
Short name T793
Test name
Test status
Simulation time 36186993143 ps
CPU time 451.57 seconds
Started Mar 17 02:57:58 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 3963588 kb
Host smart-d2feccae-eddd-492c-9593-f0f36749c07e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349536091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1349536091
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.4260446916
Short name T268
Test name
Test status
Simulation time 23248319892 ps
CPU time 522.27 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 03:06:40 PM PDT 24
Peak memory 1506360 kb
Host smart-3ecd0ee9-d096-4c11-b94e-f27d01f669f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260446916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.4260446916
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2012871129
Short name T1106
Test name
Test status
Simulation time 1441890427 ps
CPU time 7.22 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 213772 kb
Host smart-dfd31b16-4054-4a4b-ad81-b3ed1a122ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012871129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2012871129
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.2795922863
Short name T604
Test name
Test status
Simulation time 1232223297 ps
CPU time 6.64 seconds
Started Mar 17 02:57:57 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 206348 kb
Host smart-8d339dc9-db68-4105-9b0a-8ed7c67c5798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795922863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.2795922863
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1609522249
Short name T773
Test name
Test status
Simulation time 41839579 ps
CPU time 0.63 seconds
Started Mar 17 02:58:13 PM PDT 24
Finished Mar 17 02:58:14 PM PDT 24
Peak memory 201584 kb
Host smart-d27c0ecf-82d1-44f0-b6df-3c4c025914ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609522249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1609522249
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1936527656
Short name T739
Test name
Test status
Simulation time 39477295 ps
CPU time 1.22 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:58:04 PM PDT 24
Peak memory 210876 kb
Host smart-2f5d548c-ef85-448b-97cf-7ee44cafe95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936527656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1936527656
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.980917882
Short name T1214
Test name
Test status
Simulation time 559915665 ps
CPU time 10.44 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:58:14 PM PDT 24
Peak memory 327252 kb
Host smart-64cbfead-dfd1-47b7-bd47-b393e43a1e45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980917882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.980917882
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2933807936
Short name T802
Test name
Test status
Simulation time 8541180023 ps
CPU time 86.4 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:59:30 PM PDT 24
Peak memory 799120 kb
Host smart-0eccca99-7067-4f1b-a8f7-cc84f7bbd9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933807936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2933807936
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3740771320
Short name T1252
Test name
Test status
Simulation time 4442814754 ps
CPU time 67.14 seconds
Started Mar 17 02:58:02 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 712404 kb
Host smart-aadf8823-9003-4e17-823f-a16fe5015373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740771320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3740771320
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1750127368
Short name T285
Test name
Test status
Simulation time 299873527 ps
CPU time 1.04 seconds
Started Mar 17 02:58:00 PM PDT 24
Finished Mar 17 02:58:02 PM PDT 24
Peak memory 202472 kb
Host smart-e5671d1a-6e07-4016-97f4-72e42fe19798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750127368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1750127368
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3186009857
Short name T1166
Test name
Test status
Simulation time 716088695 ps
CPU time 4.61 seconds
Started Mar 17 02:58:04 PM PDT 24
Finished Mar 17 02:58:10 PM PDT 24
Peak memory 235584 kb
Host smart-0934f30e-43dd-4b6b-810f-525279339bbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186009857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3186009857
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3758909172
Short name T1059
Test name
Test status
Simulation time 11057957810 ps
CPU time 156.21 seconds
Started Mar 17 02:58:04 PM PDT 24
Finished Mar 17 03:00:41 PM PDT 24
Peak memory 1526256 kb
Host smart-c65d0632-2885-4505-88d1-37980502badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758909172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3758909172
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1355849253
Short name T719
Test name
Test status
Simulation time 2339312102 ps
CPU time 99.8 seconds
Started Mar 17 02:58:11 PM PDT 24
Finished Mar 17 02:59:51 PM PDT 24
Peak memory 398744 kb
Host smart-624a5b31-8dcc-4f49-92ea-b6f65b4c2b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355849253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1355849253
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.182275271
Short name T155
Test name
Test status
Simulation time 48836331 ps
CPU time 0.69 seconds
Started Mar 17 02:58:01 PM PDT 24
Finished Mar 17 02:58:02 PM PDT 24
Peak memory 201932 kb
Host smart-df0993b2-7d26-4de1-bce5-e123c8c692bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182275271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.182275271
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3869165840
Short name T702
Test name
Test status
Simulation time 50138900755 ps
CPU time 222.9 seconds
Started Mar 17 02:58:02 PM PDT 24
Finished Mar 17 03:01:46 PM PDT 24
Peak memory 217664 kb
Host smart-03ad7413-1ff0-4c11-b116-714461f699a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869165840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3869165840
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3196583324
Short name T1115
Test name
Test status
Simulation time 1464906572 ps
CPU time 88.79 seconds
Started Mar 17 02:58:04 PM PDT 24
Finished Mar 17 02:59:33 PM PDT 24
Peak memory 248572 kb
Host smart-948d0eb4-eb49-4ce9-a541-70385b3d346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196583324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3196583324
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.746647171
Short name T424
Test name
Test status
Simulation time 1839690824 ps
CPU time 2.67 seconds
Started Mar 17 02:58:05 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 202700 kb
Host smart-51c0410a-75d5-432b-9cfb-046b5a4cdbe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746647171 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.746647171
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1320683445
Short name T1079
Test name
Test status
Simulation time 10229716533 ps
CPU time 15.16 seconds
Started Mar 17 02:58:05 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 280576 kb
Host smart-726bee67-d7e2-45db-8092-c45165f64d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320683445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1320683445
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1985783233
Short name T351
Test name
Test status
Simulation time 10063795305 ps
CPU time 73.52 seconds
Started Mar 17 02:58:07 PM PDT 24
Finished Mar 17 02:59:21 PM PDT 24
Peak memory 599844 kb
Host smart-7ac7c24e-2969-41ea-bb4d-233fc8cf0d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985783233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1985783233
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.519441555
Short name T417
Test name
Test status
Simulation time 1986099305 ps
CPU time 2.72 seconds
Started Mar 17 02:58:06 PM PDT 24
Finished Mar 17 02:58:09 PM PDT 24
Peak memory 202668 kb
Host smart-edf9c44d-b555-45d9-9579-0c95b22a3441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519441555 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.519441555
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.4036910051
Short name T460
Test name
Test status
Simulation time 1053819966 ps
CPU time 5.18 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:58:10 PM PDT 24
Peak memory 202756 kb
Host smart-103fcc92-ff6f-49c0-9f69-dad8bdc48710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036910051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.4036910051
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2576833651
Short name T95
Test name
Test status
Simulation time 13673882902 ps
CPU time 42.75 seconds
Started Mar 17 02:58:03 PM PDT 24
Finished Mar 17 02:58:46 PM PDT 24
Peak memory 892176 kb
Host smart-2a9b9b79-2405-468d-8efd-c99ff9d32b30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576833651 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2576833651
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.3072930213
Short name T257
Test name
Test status
Simulation time 1203201421 ps
CPU time 4.15 seconds
Started Mar 17 02:58:09 PM PDT 24
Finished Mar 17 02:58:13 PM PDT 24
Peak memory 204660 kb
Host smart-0ca76dd8-2ac9-4cfb-833b-04cc47a14b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072930213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.3072930213
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1503468126
Short name T541
Test name
Test status
Simulation time 1106739430 ps
CPU time 4.98 seconds
Started Mar 17 02:58:02 PM PDT 24
Finished Mar 17 02:58:08 PM PDT 24
Peak memory 202680 kb
Host smart-038d460f-7328-4585-845a-cda4d4e2aab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503468126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1503468126
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2907738
Short name T1093
Test name
Test status
Simulation time 30870886022 ps
CPU time 19.77 seconds
Started Mar 17 02:58:01 PM PDT 24
Finished Mar 17 02:58:22 PM PDT 24
Peak memory 487512 kb
Host smart-95ba83d1-0d3e-45fc-b89f-a0585d339b21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stress_wr.2907738
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.4002503653
Short name T434
Test name
Test status
Simulation time 2378301625 ps
CPU time 6.77 seconds
Started Mar 17 02:58:06 PM PDT 24
Finished Mar 17 02:58:13 PM PDT 24
Peak memory 214432 kb
Host smart-60939c86-ba76-4f11-8667-2db4a3f25cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002503653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.4002503653
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.4120667549
Short name T1135
Test name
Test status
Simulation time 47564103 ps
CPU time 0.61 seconds
Started Mar 17 02:58:20 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 201556 kb
Host smart-4ad38194-e610-470d-8600-b8aff06d7bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120667549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.4120667549
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1852838090
Short name T589
Test name
Test status
Simulation time 109324719 ps
CPU time 1.52 seconds
Started Mar 17 02:58:14 PM PDT 24
Finished Mar 17 02:58:15 PM PDT 24
Peak memory 210948 kb
Host smart-781b3793-e432-4bf8-8368-99e52786af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852838090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1852838090
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.685360231
Short name T1161
Test name
Test status
Simulation time 4812869086 ps
CPU time 8.83 seconds
Started Mar 17 02:58:10 PM PDT 24
Finished Mar 17 02:58:19 PM PDT 24
Peak memory 297788 kb
Host smart-87b7b694-a412-4977-8526-d3e599d7b0a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685360231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.685360231
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1429351398
Short name T357
Test name
Test status
Simulation time 2982968435 ps
CPU time 40.16 seconds
Started Mar 17 02:58:14 PM PDT 24
Finished Mar 17 02:58:54 PM PDT 24
Peak memory 403528 kb
Host smart-b70d95e3-9ebb-4675-aa11-5a2f20d7e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429351398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1429351398
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2689898258
Short name T134
Test name
Test status
Simulation time 3615171031 ps
CPU time 45.29 seconds
Started Mar 17 02:58:12 PM PDT 24
Finished Mar 17 02:58:57 PM PDT 24
Peak memory 603864 kb
Host smart-98ec192f-18a6-4aa9-a4ab-40c0c79e9ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689898258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2689898258
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.125616274
Short name T220
Test name
Test status
Simulation time 1844922084 ps
CPU time 1.05 seconds
Started Mar 17 02:58:12 PM PDT 24
Finished Mar 17 02:58:13 PM PDT 24
Peak memory 202656 kb
Host smart-06845986-4fbd-40af-9f2f-6bf10697e95c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125616274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.125616274
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2612209201
Short name T577
Test name
Test status
Simulation time 372330369 ps
CPU time 10.85 seconds
Started Mar 17 02:58:10 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 238588 kb
Host smart-d4a9a8a8-b9a4-4bf8-bfd7-1b469014d0bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612209201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2612209201
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2183668302
Short name T197
Test name
Test status
Simulation time 94904674129 ps
CPU time 198.69 seconds
Started Mar 17 02:58:11 PM PDT 24
Finished Mar 17 03:01:29 PM PDT 24
Peak memory 1650336 kb
Host smart-d9b08bb1-5a5b-4704-b2c9-605830f92038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183668302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2183668302
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2116979406
Short name T867
Test name
Test status
Simulation time 4297221413 ps
CPU time 58.08 seconds
Started Mar 17 02:58:21 PM PDT 24
Finished Mar 17 02:59:20 PM PDT 24
Peak memory 284108 kb
Host smart-95b8b634-c1b4-4f24-a0c6-a66d00c72310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116979406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2116979406
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3186046953
Short name T668
Test name
Test status
Simulation time 49515619 ps
CPU time 0.62 seconds
Started Mar 17 02:58:12 PM PDT 24
Finished Mar 17 02:58:12 PM PDT 24
Peak memory 201808 kb
Host smart-95fcc794-6d0a-4ba1-a7ad-9269855c2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186046953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3186046953
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.243878228
Short name T517
Test name
Test status
Simulation time 8506730759 ps
CPU time 38.03 seconds
Started Mar 17 02:58:15 PM PDT 24
Finished Mar 17 02:58:53 PM PDT 24
Peak memory 255980 kb
Host smart-97190246-17ba-4769-ac1e-80546d0dba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243878228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.243878228
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3849762131
Short name T90
Test name
Test status
Simulation time 2447844521 ps
CPU time 62.95 seconds
Started Mar 17 02:58:12 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 243416 kb
Host smart-184384f9-1fd3-4184-adb8-f93b0edc56c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849762131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3849762131
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.587969666
Short name T273
Test name
Test status
Simulation time 4141381856 ps
CPU time 20.16 seconds
Started Mar 17 02:58:16 PM PDT 24
Finished Mar 17 02:58:36 PM PDT 24
Peak memory 226808 kb
Host smart-c9ac987a-7a4d-469b-97ff-4b05be782368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587969666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.587969666
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3779483954
Short name T922
Test name
Test status
Simulation time 16352835364 ps
CPU time 4.39 seconds
Started Mar 17 02:58:20 PM PDT 24
Finished Mar 17 02:58:24 PM PDT 24
Peak memory 202752 kb
Host smart-bf13715a-7bc9-428d-8fac-8f11a9b494fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779483954 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3779483954
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1130928457
Short name T212
Test name
Test status
Simulation time 10292231838 ps
CPU time 28.59 seconds
Started Mar 17 02:58:17 PM PDT 24
Finished Mar 17 02:58:45 PM PDT 24
Peak memory 342512 kb
Host smart-ea3101f7-efd6-4625-b252-528b8ecad119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130928457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1130928457
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.864032326
Short name T911
Test name
Test status
Simulation time 10057334716 ps
CPU time 81.25 seconds
Started Mar 17 02:58:17 PM PDT 24
Finished Mar 17 02:59:38 PM PDT 24
Peak memory 690052 kb
Host smart-5826ef3b-6611-4191-b015-d43306c02f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864032326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.864032326
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2018395453
Short name T568
Test name
Test status
Simulation time 924106289 ps
CPU time 2.38 seconds
Started Mar 17 02:58:22 PM PDT 24
Finished Mar 17 02:58:24 PM PDT 24
Peak memory 202800 kb
Host smart-ff208e44-2a6c-4d28-998c-12396d93684b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018395453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2018395453
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2051723346
Short name T632
Test name
Test status
Simulation time 914659766 ps
CPU time 4.82 seconds
Started Mar 17 02:58:15 PM PDT 24
Finished Mar 17 02:58:20 PM PDT 24
Peak memory 207180 kb
Host smart-1c616dbd-ab2c-471e-bc22-0b07a40cc2fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051723346 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2051723346
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.4156627522
Short name T605
Test name
Test status
Simulation time 7645697701 ps
CPU time 18.27 seconds
Started Mar 17 02:58:18 PM PDT 24
Finished Mar 17 02:58:36 PM PDT 24
Peak memory 202800 kb
Host smart-7fba028c-ce95-4285-a548-423453a2edc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156627522 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.4156627522
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.3712519859
Short name T689
Test name
Test status
Simulation time 882026118 ps
CPU time 4.98 seconds
Started Mar 17 02:58:14 PM PDT 24
Finished Mar 17 02:58:19 PM PDT 24
Peak memory 202644 kb
Host smart-33428058-e8a5-49b5-b1c9-4af88bcf852e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712519859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.3712519859
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.250465820
Short name T900
Test name
Test status
Simulation time 893287886 ps
CPU time 23.26 seconds
Started Mar 17 02:58:16 PM PDT 24
Finished Mar 17 02:58:40 PM PDT 24
Peak memory 202688 kb
Host smart-1e912cce-887e-4543-a551-65b345633761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250465820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.250465820
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2103806682
Short name T301
Test name
Test status
Simulation time 284842714 ps
CPU time 3.96 seconds
Started Mar 17 02:58:15 PM PDT 24
Finished Mar 17 02:58:20 PM PDT 24
Peak memory 202716 kb
Host smart-a734119d-5000-45f2-b1b1-73ddd24e69b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103806682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2103806682
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3401071940
Short name T288
Test name
Test status
Simulation time 26780394108 ps
CPU time 555.65 seconds
Started Mar 17 02:58:16 PM PDT 24
Finished Mar 17 03:07:32 PM PDT 24
Peak memory 1653108 kb
Host smart-afa36b75-0447-4e12-9155-6d8c6fd5776f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401071940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3401071940
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2855307002
Short name T861
Test name
Test status
Simulation time 1645560352 ps
CPU time 6.55 seconds
Started Mar 17 02:58:15 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 202736 kb
Host smart-ac77dc0b-af5c-45cf-9db9-e7d374bccdba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855307002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2855307002
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.2835375993
Short name T918
Test name
Test status
Simulation time 5582441545 ps
CPU time 6.41 seconds
Started Mar 17 02:58:15 PM PDT 24
Finished Mar 17 02:58:21 PM PDT 24
Peak memory 205028 kb
Host smart-8fd8c18a-00a8-4bd5-9a22-d0d7db68b745
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835375993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.2835375993
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1310938846
Short name T1089
Test name
Test status
Simulation time 18614629 ps
CPU time 0.63 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 02:58:30 PM PDT 24
Peak memory 201628 kb
Host smart-725ad7c6-9426-43af-8ef5-092833e364a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310938846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1310938846
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3205178662
Short name T974
Test name
Test status
Simulation time 403879958 ps
CPU time 1.1 seconds
Started Mar 17 02:58:26 PM PDT 24
Finished Mar 17 02:58:27 PM PDT 24
Peak memory 202776 kb
Host smart-7c9381b0-9e3f-4e9f-85f1-d4246353f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205178662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3205178662
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.821804284
Short name T618
Test name
Test status
Simulation time 681013873 ps
CPU time 7.21 seconds
Started Mar 17 02:58:20 PM PDT 24
Finished Mar 17 02:58:27 PM PDT 24
Peak memory 263920 kb
Host smart-36c40ef2-8e1a-473a-a8f0-25bd37bff5fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821804284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.821804284
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.728696732
Short name T831
Test name
Test status
Simulation time 51548051352 ps
CPU time 330.53 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 03:03:56 PM PDT 24
Peak memory 1059920 kb
Host smart-49d6e9ce-fcd3-4704-95b7-0915e2f06083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728696732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.728696732
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1688100229
Short name T991
Test name
Test status
Simulation time 2438378917 ps
CPU time 192.75 seconds
Started Mar 17 02:58:22 PM PDT 24
Finished Mar 17 03:01:35 PM PDT 24
Peak memory 796660 kb
Host smart-eba26075-c1ee-4ed0-a163-2dadb01d08a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688100229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1688100229
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3036655336
Short name T763
Test name
Test status
Simulation time 136025741 ps
CPU time 0.88 seconds
Started Mar 17 02:58:19 PM PDT 24
Finished Mar 17 02:58:20 PM PDT 24
Peak memory 202500 kb
Host smart-d423b645-0be2-469b-8e8c-f5e018b95fca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036655336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3036655336
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3883885675
Short name T292
Test name
Test status
Simulation time 231135256 ps
CPU time 12.77 seconds
Started Mar 17 02:58:26 PM PDT 24
Finished Mar 17 02:58:39 PM PDT 24
Peak memory 248056 kb
Host smart-f188e5c4-ca31-4209-a471-17cbba5f0384
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883885675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3883885675
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3096766829
Short name T811
Test name
Test status
Simulation time 5308609751 ps
CPU time 422.46 seconds
Started Mar 17 02:58:21 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 1476948 kb
Host smart-232f2e8f-4e6c-4b88-ab42-93ab4a8c3fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096766829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3096766829
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3869868497
Short name T899
Test name
Test status
Simulation time 2324703014 ps
CPU time 136.49 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 03:00:42 PM PDT 24
Peak memory 276052 kb
Host smart-91b5f17c-6273-4c95-9821-328b05d3cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869868497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3869868497
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2928358236
Short name T1153
Test name
Test status
Simulation time 18186245 ps
CPU time 0.62 seconds
Started Mar 17 02:58:19 PM PDT 24
Finished Mar 17 02:58:19 PM PDT 24
Peak memory 201872 kb
Host smart-dc25e996-a1fc-40cc-bff2-9884e34f3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928358236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2928358236
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3269434951
Short name T1010
Test name
Test status
Simulation time 5711993226 ps
CPU time 73.83 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 02:59:39 PM PDT 24
Peak memory 315324 kb
Host smart-168edd10-9128-4ad7-b451-4c344b3d67c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269434951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3269434951
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.635028728
Short name T532
Test name
Test status
Simulation time 1594446606 ps
CPU time 39.3 seconds
Started Mar 17 02:58:20 PM PDT 24
Finished Mar 17 02:59:00 PM PDT 24
Peak memory 287716 kb
Host smart-b01a5520-dbfe-4a02-abad-8f409e921c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635028728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.635028728
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2255428305
Short name T205
Test name
Test status
Simulation time 53031462828 ps
CPU time 701.41 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 03:10:06 PM PDT 24
Peak memory 2980512 kb
Host smart-90ccc4c6-b934-43cf-95e1-6b0a79aa36a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255428305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2255428305
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1698573311
Short name T1187
Test name
Test status
Simulation time 792763563 ps
CPU time 8.2 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 02:58:34 PM PDT 24
Peak memory 217476 kb
Host smart-0bff2411-7eee-4014-8486-4c6bb1f865d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698573311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1698573311
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.509374353
Short name T929
Test name
Test status
Simulation time 12665557283 ps
CPU time 3.66 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 202820 kb
Host smart-eeb86ef9-c9bd-4517-8089-244ee6e0f20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509374353 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.509374353
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3650035031
Short name T1238
Test name
Test status
Simulation time 10232188399 ps
CPU time 14.9 seconds
Started Mar 17 02:58:27 PM PDT 24
Finished Mar 17 02:58:42 PM PDT 24
Peak memory 305248 kb
Host smart-1f8c9afe-177b-4f7e-85a5-5b7b65027b4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650035031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3650035031
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3869300987
Short name T477
Test name
Test status
Simulation time 566328533 ps
CPU time 2.1 seconds
Started Mar 17 02:58:24 PM PDT 24
Finished Mar 17 02:58:26 PM PDT 24
Peak memory 202720 kb
Host smart-49d07419-f620-4bc4-b346-c1df84126311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869300987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3869300987
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3222986329
Short name T1229
Test name
Test status
Simulation time 6001108423 ps
CPU time 6.87 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 02:58:32 PM PDT 24
Peak memory 212664 kb
Host smart-27052d3e-21ae-4467-bf04-31a04af30f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222986329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3222986329
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_perf.3646751250
Short name T536
Test name
Test status
Simulation time 5491490877 ps
CPU time 5.24 seconds
Started Mar 17 02:58:23 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 215560 kb
Host smart-b184cd1a-0dc2-4389-b9a7-49addbc14d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646751250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.3646751250
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.396136624
Short name T483
Test name
Test status
Simulation time 659239121 ps
CPU time 8.95 seconds
Started Mar 17 02:58:26 PM PDT 24
Finished Mar 17 02:58:35 PM PDT 24
Peak memory 202708 kb
Host smart-68121003-33de-4be2-a6ca-3ae694de63a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396136624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.396136624
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.294670878
Short name T228
Test name
Test status
Simulation time 26102923848 ps
CPU time 42.02 seconds
Started Mar 17 02:58:26 PM PDT 24
Finished Mar 17 02:59:09 PM PDT 24
Peak memory 739644 kb
Host smart-5b4b9fbe-bedd-45b4-aafc-be551bcb5133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294670878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.294670878
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.4155829378
Short name T939
Test name
Test status
Simulation time 10434956281 ps
CPU time 283.95 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 03:03:09 PM PDT 24
Peak memory 1186748 kb
Host smart-9ba07eb2-c6bf-42f9-9717-e9cf0edd0746
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155829378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.4155829378
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3579699158
Short name T556
Test name
Test status
Simulation time 4721653282 ps
CPU time 6.62 seconds
Started Mar 17 02:58:25 PM PDT 24
Finished Mar 17 02:58:33 PM PDT 24
Peak memory 214364 kb
Host smart-18cde424-ec88-4647-994c-27b9268bc6e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579699158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3579699158
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3789124424
Short name T404
Test name
Test status
Simulation time 19100111 ps
CPU time 0.62 seconds
Started Mar 17 02:58:34 PM PDT 24
Finished Mar 17 02:58:35 PM PDT 24
Peak memory 201600 kb
Host smart-887f8523-ee0a-4e31-84a8-e34025e93f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789124424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3789124424
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1366939258
Short name T479
Test name
Test status
Simulation time 102059107 ps
CPU time 1.51 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 02:58:31 PM PDT 24
Peak memory 210912 kb
Host smart-dde1a5fb-566c-4634-a32c-535301ffbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366939258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1366939258
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3228707428
Short name T426
Test name
Test status
Simulation time 946627803 ps
CPU time 6.06 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 02:58:36 PM PDT 24
Peak memory 259264 kb
Host smart-3d55cc9d-e669-427d-bc4d-6c643ae44322
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228707428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3228707428
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1657626204
Short name T1123
Test name
Test status
Simulation time 3762292273 ps
CPU time 48.49 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 587600 kb
Host smart-21680122-b747-4f29-a6c7-40ec1ee87990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657626204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1657626204
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1242381439
Short name T1062
Test name
Test status
Simulation time 3898682354 ps
CPU time 248.95 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 03:02:39 PM PDT 24
Peak memory 919056 kb
Host smart-ac254d64-9c2f-40dd-9869-a643c46eb34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242381439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1242381439
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2513454396
Short name T450
Test name
Test status
Simulation time 111437032 ps
CPU time 0.91 seconds
Started Mar 17 02:58:28 PM PDT 24
Finished Mar 17 02:58:29 PM PDT 24
Peak memory 202496 kb
Host smart-bf94fefd-376d-43ba-ac4a-e16eaf77efb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513454396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2513454396
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2366016609
Short name T312
Test name
Test status
Simulation time 193442744 ps
CPU time 9.82 seconds
Started Mar 17 02:58:30 PM PDT 24
Finished Mar 17 02:58:40 PM PDT 24
Peak memory 233292 kb
Host smart-f62cf293-4776-4738-8b89-273224aee19e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366016609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2366016609
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.925420770
Short name T537
Test name
Test status
Simulation time 4303348061 ps
CPU time 321.4 seconds
Started Mar 17 02:58:30 PM PDT 24
Finished Mar 17 03:03:51 PM PDT 24
Peak memory 1199660 kb
Host smart-9b616f6d-30c1-4248-a7ce-a847bd387836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925420770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.925420770
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2245653830
Short name T28
Test name
Test status
Simulation time 5100491890 ps
CPU time 64.86 seconds
Started Mar 17 02:58:35 PM PDT 24
Finished Mar 17 02:59:40 PM PDT 24
Peak memory 219008 kb
Host smart-13d16f08-e13c-44c1-8de6-14d9077dbd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245653830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2245653830
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.302198369
Short name T713
Test name
Test status
Simulation time 25691272 ps
CPU time 0.63 seconds
Started Mar 17 02:58:29 PM PDT 24
Finished Mar 17 02:58:30 PM PDT 24
Peak memory 201840 kb
Host smart-29628f93-5e3e-49ad-a64d-e2a86dd6e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302198369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.302198369
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1369816850
Short name T592
Test name
Test status
Simulation time 2258563320 ps
CPU time 21.82 seconds
Started Mar 17 02:58:30 PM PDT 24
Finished Mar 17 02:58:52 PM PDT 24
Peak memory 211032 kb
Host smart-0904fe5d-04dc-4c15-90ae-93ca4e61605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369816850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1369816850
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.255690832
Short name T895
Test name
Test status
Simulation time 2719563713 ps
CPU time 28.66 seconds
Started Mar 17 02:58:31 PM PDT 24
Finished Mar 17 02:59:00 PM PDT 24
Peak memory 218976 kb
Host smart-215f2721-c868-4c7f-901a-3e549d2f5899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255690832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.255690832
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3458942446
Short name T191
Test name
Test status
Simulation time 10631078027 ps
CPU time 17.67 seconds
Started Mar 17 02:58:32 PM PDT 24
Finished Mar 17 02:58:49 PM PDT 24
Peak memory 227392 kb
Host smart-b59864fc-f0b7-473b-bdbf-fb995291394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458942446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3458942446
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1454224390
Short name T471
Test name
Test status
Simulation time 4623002701 ps
CPU time 4.83 seconds
Started Mar 17 02:58:35 PM PDT 24
Finished Mar 17 02:58:40 PM PDT 24
Peak memory 202788 kb
Host smart-d9f57f30-89a7-4656-985d-bc8380fb9552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454224390 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1454224390
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3093570494
Short name T131
Test name
Test status
Simulation time 814079839 ps
CPU time 2.62 seconds
Started Mar 17 02:58:34 PM PDT 24
Finished Mar 17 02:58:36 PM PDT 24
Peak memory 202724 kb
Host smart-9d8ab71b-7921-480d-85a5-5557d2f6b2d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093570494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3093570494
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.149734491
Short name T547
Test name
Test status
Simulation time 1288680405 ps
CPU time 5.81 seconds
Started Mar 17 02:58:36 PM PDT 24
Finished Mar 17 02:58:42 PM PDT 24
Peak memory 202732 kb
Host smart-23daacd2-4b45-47d7-9d2c-bedeeab36c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149734491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_intr_smoke.149734491
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2941269836
Short name T373
Test name
Test status
Simulation time 10798877116 ps
CPU time 49.75 seconds
Started Mar 17 02:58:35 PM PDT 24
Finished Mar 17 02:59:25 PM PDT 24
Peak memory 977100 kb
Host smart-b231e006-34ee-465e-95d0-f96386f4c6d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941269836 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2941269836
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.4059525811
Short name T318
Test name
Test status
Simulation time 5217878761 ps
CPU time 4.3 seconds
Started Mar 17 02:58:35 PM PDT 24
Finished Mar 17 02:58:39 PM PDT 24
Peak memory 202788 kb
Host smart-a3c2c7bb-f421-42ae-9091-52d7df97a468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059525811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.4059525811
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.3600508968
Short name T1068
Test name
Test status
Simulation time 31063604511 ps
CPU time 31.43 seconds
Started Mar 17 02:58:36 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 266724 kb
Host smart-eec94bee-69c0-43a2-9cca-307e891c75ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600508968 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.3600508968
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.4119321715
Short name T681
Test name
Test status
Simulation time 17382043951 ps
CPU time 1017.49 seconds
Started Mar 17 02:58:34 PM PDT 24
Finished Mar 17 03:15:32 PM PDT 24
Peak memory 4250720 kb
Host smart-56d1732d-ee84-4e34-809c-2b50b4cd5b36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119321715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.4119321715
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.5283418
Short name T856
Test name
Test status
Simulation time 1922969237 ps
CPU time 8.04 seconds
Started Mar 17 02:58:36 PM PDT 24
Finished Mar 17 02:58:44 PM PDT 24
Peak memory 202660 kb
Host smart-36aa9d90-d66e-4b93-85d5-814cc1406af1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5283418 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_timeout.5283418
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.4293378295
Short name T1131
Test name
Test status
Simulation time 4284346414 ps
CPU time 4.82 seconds
Started Mar 17 02:58:37 PM PDT 24
Finished Mar 17 02:58:42 PM PDT 24
Peak memory 202736 kb
Host smart-f85fba71-705a-4e6c-9b2d-7f3c262bb610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293378295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.4293378295
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2058871140
Short name T809
Test name
Test status
Simulation time 18156431 ps
CPU time 0.63 seconds
Started Mar 17 02:58:45 PM PDT 24
Finished Mar 17 02:58:45 PM PDT 24
Peak memory 201768 kb
Host smart-f3a9090d-8582-4549-a97d-4fe3031458ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058871140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2058871140
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3051805315
Short name T1
Test name
Test status
Simulation time 276777523 ps
CPU time 1.66 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 02:58:44 PM PDT 24
Peak memory 210912 kb
Host smart-b9389b31-0617-4d25-9bec-70c2cb2ca5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051805315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3051805315
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2097920304
Short name T790
Test name
Test status
Simulation time 2872704698 ps
CPU time 21.83 seconds
Started Mar 17 02:58:38 PM PDT 24
Finished Mar 17 02:59:00 PM PDT 24
Peak memory 275128 kb
Host smart-b7e0b5a4-7309-45dc-86c2-06bf15d82984
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097920304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2097920304
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3464354420
Short name T851
Test name
Test status
Simulation time 12692026377 ps
CPU time 83.47 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 03:00:06 PM PDT 24
Peak memory 821308 kb
Host smart-323ffafb-b8ab-461f-aea9-7e0158c0afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464354420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3464354420
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3832265999
Short name T588
Test name
Test status
Simulation time 1826086430 ps
CPU time 57.71 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:59:37 PM PDT 24
Peak memory 603444 kb
Host smart-201e8a5b-3a02-4e0d-9752-b59edc797142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832265999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3832265999
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.995824147
Short name T173
Test name
Test status
Simulation time 589877405 ps
CPU time 1 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 02:58:43 PM PDT 24
Peak memory 202228 kb
Host smart-1c468a21-b17c-4788-aad8-9dea2263cba9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995824147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.995824147
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.253663919
Short name T543
Test name
Test status
Simulation time 207096231 ps
CPU time 5.4 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 02:58:49 PM PDT 24
Peak memory 238592 kb
Host smart-b8057467-b5dc-4126-a449-67e364b72498
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253663919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
253663919
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.3128326515
Short name T603
Test name
Test status
Simulation time 4637038919 ps
CPU time 371.97 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 1332876 kb
Host smart-e8c716ec-7c1e-4f3a-8eca-fc93fb7c4c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128326515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3128326515
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.784032564
Short name T662
Test name
Test status
Simulation time 3298750890 ps
CPU time 94.62 seconds
Started Mar 17 02:58:49 PM PDT 24
Finished Mar 17 03:00:24 PM PDT 24
Peak memory 259624 kb
Host smart-3037a044-d2ec-4201-9319-569a850fd3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784032564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.784032564
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3140373788
Short name T216
Test name
Test status
Simulation time 18711156 ps
CPU time 0.61 seconds
Started Mar 17 02:58:36 PM PDT 24
Finished Mar 17 02:58:37 PM PDT 24
Peak memory 201756 kb
Host smart-579865be-3df7-494e-b98a-b83596a9ffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140373788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3140373788
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.116788307
Short name T352
Test name
Test status
Simulation time 12937293487 ps
CPU time 98.42 seconds
Started Mar 17 02:58:37 PM PDT 24
Finished Mar 17 03:00:16 PM PDT 24
Peak memory 202864 kb
Host smart-0ec36405-0fae-49a1-b573-3317db00c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116788307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.116788307
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2138998558
Short name T239
Test name
Test status
Simulation time 14334183188 ps
CPU time 89.88 seconds
Started Mar 17 02:58:35 PM PDT 24
Finished Mar 17 03:00:05 PM PDT 24
Peak memory 236452 kb
Host smart-e677e0b2-f508-4905-969c-e41a8a3b5d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138998558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2138998558
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2755403955
Short name T140
Test name
Test status
Simulation time 159709131517 ps
CPU time 632.03 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 03:09:15 PM PDT 24
Peak memory 2015684 kb
Host smart-da0dc936-ee2d-4fea-a86b-600874440d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755403955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2755403955
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2974024755
Short name T190
Test name
Test status
Simulation time 2365041191 ps
CPU time 11.52 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:58:50 PM PDT 24
Peak memory 211064 kb
Host smart-29f822c6-4772-44f3-ac08-d2598dac9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974024755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2974024755
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2952077999
Short name T491
Test name
Test status
Simulation time 973660861 ps
CPU time 4.11 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 02:58:48 PM PDT 24
Peak memory 202668 kb
Host smart-4ff41010-0dd7-4d16-a7b7-7b707819f35f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952077999 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2952077999
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1879502462
Short name T465
Test name
Test status
Simulation time 10035976870 ps
CPU time 64.31 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:59:44 PM PDT 24
Peak memory 559388 kb
Host smart-19ffebe4-49e8-4e5d-8527-5bf1f3e1d217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879502462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1879502462
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.378736931
Short name T1107
Test name
Test status
Simulation time 10252655430 ps
CPU time 14.55 seconds
Started Mar 17 02:58:38 PM PDT 24
Finished Mar 17 02:58:53 PM PDT 24
Peak memory 359904 kb
Host smart-3d6fcf22-b38e-467f-a8e7-e382c214ce1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378736931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.378736931
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3455221897
Short name T940
Test name
Test status
Simulation time 364804909 ps
CPU time 2.22 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:58:42 PM PDT 24
Peak memory 202716 kb
Host smart-91bc1bc1-3404-4fec-8cf1-38ebe3b1ed22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455221897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3455221897
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1882364512
Short name T716
Test name
Test status
Simulation time 980988789 ps
CPU time 4.88 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:58:44 PM PDT 24
Peak memory 202640 kb
Host smart-1d1651cd-7a75-49a2-8ca5-295c6a9b5042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882364512 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1882364512
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.4153091662
Short name T965
Test name
Test status
Simulation time 21069777479 ps
CPU time 407.42 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 3643844 kb
Host smart-8b12ba9c-eda3-4319-92e5-e825e3906d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153091662 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4153091662
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.440069532
Short name T1092
Test name
Test status
Simulation time 547883337 ps
CPU time 3.44 seconds
Started Mar 17 02:58:40 PM PDT 24
Finished Mar 17 02:58:43 PM PDT 24
Peak memory 202584 kb
Host smart-ea24e6a2-f711-421a-9bfa-0fd8ed0d44c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440069532 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_perf.440069532
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.2343202013
Short name T1102
Test name
Test status
Simulation time 60393324874 ps
CPU time 189.94 seconds
Started Mar 17 02:58:38 PM PDT 24
Finished Mar 17 03:01:48 PM PDT 24
Peak memory 1152440 kb
Host smart-df1a3670-6f16-41b4-854d-9373b8f60195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343202013 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.2343202013
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3054227461
Short name T919
Test name
Test status
Simulation time 37637923281 ps
CPU time 28.97 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 680156 kb
Host smart-e5ed3c00-1afc-417a-990c-abfa8f5c1979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054227461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3054227461
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1905524947
Short name T1125
Test name
Test status
Simulation time 1452225700 ps
CPU time 6.64 seconds
Started Mar 17 02:58:42 PM PDT 24
Finished Mar 17 02:58:49 PM PDT 24
Peak memory 207184 kb
Host smart-4491d935-75ba-46fa-b112-7824b9770f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905524947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1905524947
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.3024412518
Short name T643
Test name
Test status
Simulation time 4044198125 ps
CPU time 6.38 seconds
Started Mar 17 02:58:39 PM PDT 24
Finished Mar 17 02:58:45 PM PDT 24
Peak memory 205812 kb
Host smart-0d072123-0d0a-46bc-b075-7e3c3470f828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024412518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.3024412518
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.122007379
Short name T912
Test name
Test status
Simulation time 36863578 ps
CPU time 0.66 seconds
Started Mar 17 02:58:56 PM PDT 24
Finished Mar 17 02:58:58 PM PDT 24
Peak memory 201568 kb
Host smart-b6500ee9-6ee8-438e-a069-6a0f5234cfe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122007379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.122007379
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3641089132
Short name T789
Test name
Test status
Simulation time 151597584 ps
CPU time 1.31 seconds
Started Mar 17 02:58:45 PM PDT 24
Finished Mar 17 02:58:47 PM PDT 24
Peak memory 210952 kb
Host smart-8adaa829-efb6-4e3b-9d2c-3b1350f9ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641089132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3641089132
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3815623605
Short name T770
Test name
Test status
Simulation time 191396362 ps
CPU time 4.27 seconds
Started Mar 17 02:58:47 PM PDT 24
Finished Mar 17 02:58:51 PM PDT 24
Peak memory 233492 kb
Host smart-84765de3-bf93-48d4-8eca-ceedc184bc64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815623605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3815623605
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1130191267
Short name T774
Test name
Test status
Simulation time 3062090237 ps
CPU time 241.67 seconds
Started Mar 17 02:58:46 PM PDT 24
Finished Mar 17 03:02:48 PM PDT 24
Peak memory 934328 kb
Host smart-ac9c6073-8b24-46f6-aba7-b6c17a096f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130191267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1130191267
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.94083951
Short name T701
Test name
Test status
Simulation time 2249443624 ps
CPU time 147.06 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 03:01:11 PM PDT 24
Peak memory 603164 kb
Host smart-84243e7f-72a0-4e2d-b81c-f2551a32c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94083951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.94083951
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1010879366
Short name T325
Test name
Test status
Simulation time 115549741 ps
CPU time 0.95 seconds
Started Mar 17 02:58:46 PM PDT 24
Finished Mar 17 02:58:47 PM PDT 24
Peak memory 202424 kb
Host smart-778f02c0-0311-429e-bc5f-7b89a5fba0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010879366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1010879366
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.971797904
Short name T671
Test name
Test status
Simulation time 2108876050 ps
CPU time 10 seconds
Started Mar 17 02:58:46 PM PDT 24
Finished Mar 17 02:58:57 PM PDT 24
Peak memory 202676 kb
Host smart-2cb33934-7cbd-42e8-afb0-263fc2c1de39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971797904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
971797904
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3533833622
Short name T399
Test name
Test status
Simulation time 15748742947 ps
CPU time 293.95 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 03:03:38 PM PDT 24
Peak memory 1154976 kb
Host smart-56824f41-7f6d-4f5d-9e42-260634569f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533833622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3533833622
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.4028822725
Short name T827
Test name
Test status
Simulation time 15165882628 ps
CPU time 41.35 seconds
Started Mar 17 02:58:53 PM PDT 24
Finished Mar 17 02:59:35 PM PDT 24
Peak memory 267404 kb
Host smart-20ef025a-e1ed-412f-8349-15f564285973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028822725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.4028822725
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.4020046353
Short name T502
Test name
Test status
Simulation time 15146532 ps
CPU time 0.61 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 02:58:45 PM PDT 24
Peak memory 201784 kb
Host smart-33ff2cd0-d2ee-46a8-a1e6-3d5e053a48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020046353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.4020046353
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.4024205323
Short name T443
Test name
Test status
Simulation time 3328860635 ps
CPU time 61.68 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 02:59:46 PM PDT 24
Peak memory 237600 kb
Host smart-7f71c30b-41a5-4a41-bdf7-f6f2c25129aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024205323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4024205323
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2748819136
Short name T1018
Test name
Test status
Simulation time 9046078337 ps
CPU time 115.61 seconds
Started Mar 17 02:58:43 PM PDT 24
Finished Mar 17 03:00:39 PM PDT 24
Peak memory 231740 kb
Host smart-ace3f975-5502-4a62-8883-ece7d8accedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748819136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2748819136
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.646069456
Short name T1105
Test name
Test status
Simulation time 19178430577 ps
CPU time 553.62 seconds
Started Mar 17 02:58:43 PM PDT 24
Finished Mar 17 03:07:57 PM PDT 24
Peak memory 1917712 kb
Host smart-80269db7-0c92-44b6-9cd8-a210fdbacd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646069456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.646069456
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3744650646
Short name T281
Test name
Test status
Simulation time 1341786708 ps
CPU time 29.8 seconds
Started Mar 17 02:58:44 PM PDT 24
Finished Mar 17 02:59:14 PM PDT 24
Peak memory 210972 kb
Host smart-9b1d9f8e-d3fe-437c-a8c3-008411b58f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744650646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3744650646
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3102811837
Short name T1253
Test name
Test status
Simulation time 714702309 ps
CPU time 3.57 seconds
Started Mar 17 02:58:49 PM PDT 24
Finished Mar 17 02:58:52 PM PDT 24
Peak memory 202724 kb
Host smart-03dfac58-3ade-41a8-b1a0-6d221cdb3b7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102811837 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3102811837
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.4223790151
Short name T747
Test name
Test status
Simulation time 10272792092 ps
CPU time 37.1 seconds
Started Mar 17 02:58:49 PM PDT 24
Finished Mar 17 02:59:27 PM PDT 24
Peak memory 440028 kb
Host smart-8af8b96f-c5d0-4c48-a9f1-da6a086274b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223790151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.4223790151
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2089947850
Short name T1250
Test name
Test status
Simulation time 10453528719 ps
CPU time 11.31 seconds
Started Mar 17 02:58:48 PM PDT 24
Finished Mar 17 02:59:00 PM PDT 24
Peak memory 319120 kb
Host smart-5fc2a959-8624-49c0-989d-77c8229ec715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089947850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2089947850
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.688053947
Short name T48
Test name
Test status
Simulation time 1686392890 ps
CPU time 2.52 seconds
Started Mar 17 02:58:48 PM PDT 24
Finished Mar 17 02:58:51 PM PDT 24
Peak memory 202760 kb
Host smart-9caab37c-7f89-4734-b916-20577c6c5798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688053947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.688053947
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3824010661
Short name T358
Test name
Test status
Simulation time 2215792237 ps
CPU time 2.97 seconds
Started Mar 17 02:58:51 PM PDT 24
Finished Mar 17 02:58:54 PM PDT 24
Peak memory 202768 kb
Host smart-e9acb5e1-ff24-435f-af3f-90b40898e3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824010661 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3824010661
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2133632245
Short name T915
Test name
Test status
Simulation time 13197715506 ps
CPU time 99.14 seconds
Started Mar 17 02:58:48 PM PDT 24
Finished Mar 17 03:00:27 PM PDT 24
Peak memory 1548472 kb
Host smart-272f63d0-a640-4c27-a39e-a0e8cff43cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133632245 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2133632245
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.346236662
Short name T877
Test name
Test status
Simulation time 3285424331 ps
CPU time 5.58 seconds
Started Mar 17 02:58:48 PM PDT 24
Finished Mar 17 02:58:54 PM PDT 24
Peak memory 208868 kb
Host smart-13b7accb-46fc-4450-bc89-282db5c02bc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346236662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_perf.346236662
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1039438334
Short name T419
Test name
Test status
Simulation time 489417581 ps
CPU time 4.64 seconds
Started Mar 17 02:58:50 PM PDT 24
Finished Mar 17 02:58:55 PM PDT 24
Peak memory 202684 kb
Host smart-256dac2b-8fa0-411f-9b06-8cde82a3bd05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039438334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1039438334
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2301211355
Short name T473
Test name
Test status
Simulation time 39151705984 ps
CPU time 72.98 seconds
Started Mar 17 02:58:49 PM PDT 24
Finished Mar 17 03:00:02 PM PDT 24
Peak memory 1191380 kb
Host smart-eb1fad71-fb4a-4963-85a5-f0822e328db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301211355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2301211355
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2931785704
Short name T1034
Test name
Test status
Simulation time 34130578592 ps
CPU time 750.15 seconds
Started Mar 17 02:58:50 PM PDT 24
Finished Mar 17 03:11:21 PM PDT 24
Peak memory 4152256 kb
Host smart-8a5cb3b6-8e0a-4fad-bb91-045c2e00957e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931785704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2931785704
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2304065922
Short name T626
Test name
Test status
Simulation time 3780835319 ps
CPU time 6.38 seconds
Started Mar 17 02:58:48 PM PDT 24
Finished Mar 17 02:58:55 PM PDT 24
Peak memory 208848 kb
Host smart-316c948d-29d5-4ec7-ba14-50bdbc3886c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304065922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2304065922
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2492550491
Short name T816
Test name
Test status
Simulation time 2811256981 ps
CPU time 6.43 seconds
Started Mar 17 02:58:50 PM PDT 24
Finished Mar 17 02:58:57 PM PDT 24
Peak memory 206004 kb
Host smart-a13552c1-d3d9-4fb2-b84e-c05205848ad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492550491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2492550491
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.4067600069
Short name T378
Test name
Test status
Simulation time 115914355 ps
CPU time 0.57 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:53:37 PM PDT 24
Peak memory 201624 kb
Host smart-a2d83ee2-8396-44f2-ad05-6ae6484ad8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067600069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.4067600069
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.837542907
Short name T336
Test name
Test status
Simulation time 249862835 ps
CPU time 1.33 seconds
Started Mar 17 02:53:20 PM PDT 24
Finished Mar 17 02:53:22 PM PDT 24
Peak memory 210996 kb
Host smart-aeb799b8-9cb8-4041-9547-f39e09e79869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837542907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.837542907
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1771071079
Short name T260
Test name
Test status
Simulation time 457364852 ps
CPU time 7.89 seconds
Started Mar 17 02:53:21 PM PDT 24
Finished Mar 17 02:53:29 PM PDT 24
Peak memory 270984 kb
Host smart-e3ec8c53-04ea-4a6b-be72-38697f1d6860
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771071079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1771071079
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1741692144
Short name T307
Test name
Test status
Simulation time 4723980438 ps
CPU time 75.73 seconds
Started Mar 17 02:53:40 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 779628 kb
Host smart-7cfbd755-05d8-4b60-8b27-75763eaf82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741692144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1741692144
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1504038500
Short name T470
Test name
Test status
Simulation time 9666295321 ps
CPU time 171.93 seconds
Started Mar 17 02:53:21 PM PDT 24
Finished Mar 17 02:56:13 PM PDT 24
Peak memory 710308 kb
Host smart-839d4604-b2b2-4932-a19d-4d78bc47ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504038500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1504038500
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1355756660
Short name T170
Test name
Test status
Simulation time 139908775 ps
CPU time 1.18 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 202640 kb
Host smart-cacc3c8f-659d-428f-9e95-d89d06cbbff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355756660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1355756660
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.704981875
Short name T142
Test name
Test status
Simulation time 245231620 ps
CPU time 5.87 seconds
Started Mar 17 02:53:21 PM PDT 24
Finished Mar 17 02:53:27 PM PDT 24
Peak memory 202680 kb
Host smart-f33ad4d5-5ec3-493f-9852-67db5d0b3601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704981875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.704981875
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3104213072
Short name T800
Test name
Test status
Simulation time 16653972865 ps
CPU time 85.97 seconds
Started Mar 17 02:53:18 PM PDT 24
Finished Mar 17 02:54:44 PM PDT 24
Peak memory 1114900 kb
Host smart-68a84dba-d610-46c1-b05f-b91d1efe5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104213072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3104213072
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3355434267
Short name T262
Test name
Test status
Simulation time 2395130451 ps
CPU time 69.95 seconds
Started Mar 17 02:53:26 PM PDT 24
Finished Mar 17 02:54:36 PM PDT 24
Peak memory 308188 kb
Host smart-74c99215-4c91-43af-85e9-5378666a13b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355434267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3355434267
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2957765224
Short name T157
Test name
Test status
Simulation time 21387977 ps
CPU time 0.62 seconds
Started Mar 17 02:53:46 PM PDT 24
Finished Mar 17 02:53:47 PM PDT 24
Peak memory 201868 kb
Host smart-52639826-c34e-4596-8b5a-44976022b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957765224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2957765224
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.705469089
Short name T29
Test name
Test status
Simulation time 19200423615 ps
CPU time 314.42 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:58:53 PM PDT 24
Peak memory 218072 kb
Host smart-e2241271-3db8-4306-b217-747dea3d667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705469089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.705469089
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.40231362
Short name T628
Test name
Test status
Simulation time 1963056470 ps
CPU time 45.48 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:54:28 PM PDT 24
Peak memory 243436 kb
Host smart-dd2f714e-7916-40ad-bbf4-3146a0c51a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40231362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.40231362
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3608306486
Short name T764
Test name
Test status
Simulation time 100988326826 ps
CPU time 2297.39 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 03:31:49 PM PDT 24
Peak memory 2034516 kb
Host smart-df8afae2-a8ee-4cae-8111-61906024b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608306486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3608306486
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.258981565
Short name T734
Test name
Test status
Simulation time 2413601418 ps
CPU time 27.07 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:54:09 PM PDT 24
Peak memory 210900 kb
Host smart-b3476ce2-dc71-4d91-b49e-9d58098b43aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258981565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.258981565
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.213624293
Short name T1217
Test name
Test status
Simulation time 2725215157 ps
CPU time 3.48 seconds
Started Mar 17 02:53:40 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 202852 kb
Host smart-be38ca35-c658-4e89-90de-a6862ee50f8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213624293 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.213624293
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3915315582
Short name T1009
Test name
Test status
Simulation time 10237188264 ps
CPU time 29.74 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:54:09 PM PDT 24
Peak memory 384660 kb
Host smart-d71e210e-51d2-4c13-a8ad-1ec16f2ae34b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915315582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3915315582
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.138546803
Short name T1193
Test name
Test status
Simulation time 705748118 ps
CPU time 2.03 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 202748 kb
Host smart-addbe931-9f01-4d9e-bf7c-4557f1195362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138546803 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.138546803
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.96064298
Short name T808
Test name
Test status
Simulation time 950119174 ps
CPU time 5.15 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 208368 kb
Host smart-7a60dc96-eea1-460d-8141-7d56cbb2921d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96064298 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.96064298
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3257510986
Short name T246
Test name
Test status
Simulation time 11269449942 ps
CPU time 9.64 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:53:49 PM PDT 24
Peak memory 276996 kb
Host smart-3973b713-4735-4fe5-8fb5-3074774388d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257510986 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3257510986
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.1495447821
Short name T425
Test name
Test status
Simulation time 599239395 ps
CPU time 3.58 seconds
Started Mar 17 02:53:25 PM PDT 24
Finished Mar 17 02:53:29 PM PDT 24
Peak memory 203660 kb
Host smart-f8af94c5-d7f2-46c9-839f-3fd10c60e23d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495447821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.1495447821
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.1524167205
Short name T446
Test name
Test status
Simulation time 9739100907 ps
CPU time 49.73 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 297384 kb
Host smart-6b8b0647-8a85-4111-9061-bf52a431f0d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524167205 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.1524167205
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1316894671
Short name T1082
Test name
Test status
Simulation time 20450400196 ps
CPU time 12.73 seconds
Started Mar 17 02:53:22 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 202848 kb
Host smart-94d771db-c67a-4e20-9ae8-ef20f643aa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316894671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1316894671
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1796446998
Short name T365
Test name
Test status
Simulation time 6656996722 ps
CPU time 7.43 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:53:43 PM PDT 24
Peak memory 208884 kb
Host smart-9aa9bd9b-87a1-42f7-a64b-0772bc750685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796446998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1796446998
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.2045447678
Short name T53
Test name
Test status
Simulation time 1164783803 ps
CPU time 6.38 seconds
Started Mar 17 02:53:27 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 202740 kb
Host smart-970c8b48-3110-43d3-b334-5920d2d0571d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045447678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.2045447678
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.566705838
Short name T730
Test name
Test status
Simulation time 16332739 ps
CPU time 0.62 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:29 PM PDT 24
Peak memory 201548 kb
Host smart-b4ba9401-3225-4574-8fdd-ef388772e516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566705838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.566705838
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2200780008
Short name T564
Test name
Test status
Simulation time 97544196 ps
CPU time 1.3 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 210980 kb
Host smart-4573f859-12e8-4a0f-b81b-460f62f0a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200780008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2200780008
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.868585915
Short name T992
Test name
Test status
Simulation time 681978388 ps
CPU time 6.74 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 276440 kb
Host smart-73a409b9-db08-42e7-bf78-7f59a4cbe9c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868585915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.868585915
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2091757139
Short name T196
Test name
Test status
Simulation time 9200159703 ps
CPU time 75.24 seconds
Started Mar 17 02:53:30 PM PDT 24
Finished Mar 17 02:54:45 PM PDT 24
Peak memory 777048 kb
Host smart-255746db-dd22-40e5-bdd1-48324f3a91a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091757139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2091757139
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.669805039
Short name T1122
Test name
Test status
Simulation time 11345455457 ps
CPU time 94.05 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:55:14 PM PDT 24
Peak memory 773056 kb
Host smart-30a80944-59a9-47a9-a699-90751226ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669805039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.669805039
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2608602658
Short name T528
Test name
Test status
Simulation time 266860082 ps
CPU time 0.8 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:30 PM PDT 24
Peak memory 202444 kb
Host smart-6aea8f82-6e3d-44c8-b6a5-8974113185c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608602658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2608602658
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.63541787
Short name T1087
Test name
Test status
Simulation time 623366962 ps
CPU time 7.75 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202652 kb
Host smart-d35954b4-7347-4de0-9ea1-f7c56fe472f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63541787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.63541787
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1010810321
Short name T629
Test name
Test status
Simulation time 4603011581 ps
CPU time 375.26 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:59:58 PM PDT 24
Peak memory 1347732 kb
Host smart-1a3a8716-485f-460c-abd5-657d00a96357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010810321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1010810321
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.963966891
Short name T740
Test name
Test status
Simulation time 1341321717 ps
CPU time 47.96 seconds
Started Mar 17 02:53:26 PM PDT 24
Finished Mar 17 02:54:14 PM PDT 24
Peak memory 340292 kb
Host smart-a9005843-5183-44ee-bbb5-ef0da0df2fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963966891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.963966891
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1224432303
Short name T755
Test name
Test status
Simulation time 41698517 ps
CPU time 0.62 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 201820 kb
Host smart-dc946eef-49da-468a-a224-cc1398b2fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224432303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1224432303
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2381013511
Short name T183
Test name
Test status
Simulation time 9032372230 ps
CPU time 144.07 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 252120 kb
Host smart-8047fcf9-aa68-47a0-9e19-32ccc5642b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381013511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2381013511
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3482587375
Short name T1150
Test name
Test status
Simulation time 4899163855 ps
CPU time 168.45 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 292620 kb
Host smart-de112b75-0911-46f5-a2a6-2200221193b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482587375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3482587375
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2297318445
Short name T136
Test name
Test status
Simulation time 28223751055 ps
CPU time 772.68 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 03:06:27 PM PDT 24
Peak memory 1529124 kb
Host smart-a4dbba50-ad30-48ab-8bf7-5ab281c3b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297318445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2297318445
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3711997012
Short name T508
Test name
Test status
Simulation time 1553117997 ps
CPU time 30.55 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:54:12 PM PDT 24
Peak memory 210788 kb
Host smart-55a8d826-6094-4c13-825c-efd4de329016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711997012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3711997012
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3785842947
Short name T247
Test name
Test status
Simulation time 10128441616 ps
CPU time 62.51 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:54:31 PM PDT 24
Peak memory 538188 kb
Host smart-c36dcb3e-d8b5-4a08-a850-28ad522d61a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785842947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3785842947
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2027590256
Short name T998
Test name
Test status
Simulation time 10721792867 ps
CPU time 6.36 seconds
Started Mar 17 02:53:37 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 246588 kb
Host smart-607fc9a5-09a0-41e4-9935-c5ad948c3f50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027590256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2027590256
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.4205627130
Short name T776
Test name
Test status
Simulation time 356681553 ps
CPU time 2.37 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 202568 kb
Host smart-0227fac6-6bb9-443b-9ec7-da976f025142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205627130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.4205627130
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1738276198
Short name T549
Test name
Test status
Simulation time 1221782096 ps
CPU time 5.16 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 202756 kb
Host smart-feb251d0-d75c-4598-87b4-a09e8a234b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738276198 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1738276198
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2159162322
Short name T733
Test name
Test status
Simulation time 19392281448 ps
CPU time 130.91 seconds
Started Mar 17 02:53:24 PM PDT 24
Finished Mar 17 02:55:35 PM PDT 24
Peak memory 1611320 kb
Host smart-066dad29-b8fd-47cd-8526-38ae2c254779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159162322 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2159162322
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.3255470750
Short name T320
Test name
Test status
Simulation time 1125959464 ps
CPU time 2.27 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 202788 kb
Host smart-2878f97b-0793-4d1a-b118-1349109eaaec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255470750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.3255470750
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2751336317
Short name T383
Test name
Test status
Simulation time 684838804 ps
CPU time 13.17 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:53:42 PM PDT 24
Peak memory 202904 kb
Host smart-56f6ff43-73a1-411b-a998-a775e82c2333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751336317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2751336317
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.4175055792
Short name T1266
Test name
Test status
Simulation time 51236161583 ps
CPU time 163.59 seconds
Started Mar 17 02:53:26 PM PDT 24
Finished Mar 17 02:56:10 PM PDT 24
Peak memory 2006596 kb
Host smart-a9055674-64c5-409a-a06c-9fc16c9180e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175055792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.4175055792
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.4048106583
Short name T941
Test name
Test status
Simulation time 7594408394 ps
CPU time 476.93 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 03:01:39 PM PDT 24
Peak memory 1669528 kb
Host smart-b7635ad1-e098-4fe4-b6fb-f8174e68037c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048106583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.4048106583
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.3950543006
Short name T229
Test name
Test status
Simulation time 3940149151 ps
CPU time 6.78 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202724 kb
Host smart-a886b755-cc6f-4eee-a597-c606c92c677b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950543006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.3950543006
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.81907597
Short name T1070
Test name
Test status
Simulation time 36682563 ps
CPU time 0.59 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:53:44 PM PDT 24
Peak memory 201560 kb
Host smart-59634fb9-0c97-40bc-8db1-479e789a6391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81907597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.81907597
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3444740119
Short name T886
Test name
Test status
Simulation time 237215456 ps
CPU time 1.5 seconds
Started Mar 17 02:53:40 PM PDT 24
Finished Mar 17 02:53:42 PM PDT 24
Peak memory 212636 kb
Host smart-c586c818-748f-44d9-90e5-08d110690cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444740119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3444740119
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4193349539
Short name T287
Test name
Test status
Simulation time 739799556 ps
CPU time 4.29 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 239108 kb
Host smart-de573ee3-bc22-4a44-8187-be108c5b521b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193349539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4193349539
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3227137069
Short name T954
Test name
Test status
Simulation time 8704206793 ps
CPU time 157.42 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 723256 kb
Host smart-1fd178f0-2854-4338-9db4-cafe27d87fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227137069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3227137069
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1311072137
Short name T411
Test name
Test status
Simulation time 1974527313 ps
CPU time 142.59 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:56:02 PM PDT 24
Peak memory 673004 kb
Host smart-0315c171-448c-49bb-bf6b-aa1a0ded12ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311072137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1311072137
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3509267927
Short name T821
Test name
Test status
Simulation time 911897911 ps
CPU time 1.03 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 02:53:33 PM PDT 24
Peak memory 202848 kb
Host smart-244d2a67-5bdf-41fe-bc7f-e623b05545a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509267927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3509267927
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2095091720
Short name T1162
Test name
Test status
Simulation time 223935534 ps
CPU time 12.42 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 02:53:45 PM PDT 24
Peak memory 245936 kb
Host smart-39f66e93-ab96-4093-af21-a3e4e3155e1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095091720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2095091720
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3367003584
Short name T200
Test name
Test status
Simulation time 4895475257 ps
CPU time 156.47 seconds
Started Mar 17 02:53:37 PM PDT 24
Finished Mar 17 02:56:13 PM PDT 24
Peak memory 1350128 kb
Host smart-19e4b3ee-9188-44ad-a6de-81bb2b55f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367003584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3367003584
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.869970587
Short name T34
Test name
Test status
Simulation time 3559447499 ps
CPU time 97.65 seconds
Started Mar 17 02:53:39 PM PDT 24
Finished Mar 17 02:55:17 PM PDT 24
Peak memory 227296 kb
Host smart-8ae92f31-07f9-4fcd-9aa7-1d3207b73e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869970587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.869970587
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.140572501
Short name T327
Test name
Test status
Simulation time 17604588 ps
CPU time 0.64 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 201812 kb
Host smart-bd0673a1-9acb-4e58-b65f-9a4194ce4a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140572501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.140572501
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2850481911
Short name T840
Test name
Test status
Simulation time 6024503837 ps
CPU time 32.8 seconds
Started Mar 17 02:53:37 PM PDT 24
Finished Mar 17 02:54:10 PM PDT 24
Peak memory 231788 kb
Host smart-629494a2-21eb-40c5-9232-eec731f77955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850481911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2850481911
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2926114285
Short name T297
Test name
Test status
Simulation time 5524925833 ps
CPU time 72.19 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:54:40 PM PDT 24
Peak memory 243616 kb
Host smart-697e5647-178d-4df3-b393-431c5753459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926114285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2926114285
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1078061819
Short name T206
Test name
Test status
Simulation time 15414602774 ps
CPU time 378.85 seconds
Started Mar 17 02:53:45 PM PDT 24
Finished Mar 17 03:00:05 PM PDT 24
Peak memory 1697124 kb
Host smart-8f0173c3-ccfe-41cd-9eb1-b23e56ad25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078061819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1078061819
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3409351278
Short name T932
Test name
Test status
Simulation time 749261832 ps
CPU time 10.83 seconds
Started Mar 17 02:53:29 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 214400 kb
Host smart-b2806f81-f41a-4df8-a344-8f5a3aa6610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409351278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3409351278
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.4032334057
Short name T571
Test name
Test status
Simulation time 1070133695 ps
CPU time 4.4 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:43 PM PDT 24
Peak memory 202672 kb
Host smart-3ae50f1b-f83e-457b-a866-d7fdf31220e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032334057 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.4032334057
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1655986706
Short name T646
Test name
Test status
Simulation time 12130178728 ps
CPU time 5.79 seconds
Started Mar 17 02:53:28 PM PDT 24
Finished Mar 17 02:53:34 PM PDT 24
Peak memory 256788 kb
Host smart-7bef3e2b-f18e-4909-b5e4-fc3ab6b80e6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655986706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1655986706
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1180564354
Short name T1165
Test name
Test status
Simulation time 1487843105 ps
CPU time 2.4 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:35 PM PDT 24
Peak memory 202788 kb
Host smart-927f7b68-95e2-44b8-a799-dcae91f0e676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180564354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1180564354
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3638522910
Short name T1244
Test name
Test status
Simulation time 4404136863 ps
CPU time 5.24 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 210336 kb
Host smart-1abc9750-964f-4b20-a084-49a4a9634e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638522910 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3638522910
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3673197207
Short name T973
Test name
Test status
Simulation time 19590630445 ps
CPU time 336.76 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 3063268 kb
Host smart-3ae416a0-14b2-4421-a4e2-56bc5cbf2dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673197207 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3673197207
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.3132367984
Short name T1222
Test name
Test status
Simulation time 1650415725 ps
CPU time 4.74 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 205908 kb
Host smart-134f8d4a-8e86-4077-99db-5c0053d4eb7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132367984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.3132367984
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.1827595606
Short name T340
Test name
Test status
Simulation time 23429820951 ps
CPU time 55.44 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 02:54:27 PM PDT 24
Peak memory 317016 kb
Host smart-e61f79ec-4718-4fa1-80d1-d27a2d4e844f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827595606 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.1827595606
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.300281401
Short name T356
Test name
Test status
Simulation time 40738998412 ps
CPU time 621.62 seconds
Started Mar 17 02:53:45 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 5140016 kb
Host smart-aa0e2bf8-d373-4180-8907-2e6b11ccd6ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300281401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.300281401
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2442853222
Short name T663
Test name
Test status
Simulation time 18106627146 ps
CPU time 161.23 seconds
Started Mar 17 02:53:30 PM PDT 24
Finished Mar 17 02:56:12 PM PDT 24
Peak memory 768112 kb
Host smart-500fc899-93f4-4b79-b49e-a5cbdd089591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442853222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2442853222
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1556235347
Short name T752
Test name
Test status
Simulation time 1594286924 ps
CPU time 7.28 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:53:46 PM PDT 24
Peak memory 202636 kb
Host smart-d09634c0-48a8-4cab-9506-f042850861a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556235347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1556235347
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.616261288
Short name T1085
Test name
Test status
Simulation time 3446871806 ps
CPU time 4.55 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 202796 kb
Host smart-0eeccd1f-3eef-451c-aaa9-a70db45aa21c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616261288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_unexp_stop.616261288
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2979614331
Short name T1254
Test name
Test status
Simulation time 15382265 ps
CPU time 0.59 seconds
Started Mar 17 02:53:37 PM PDT 24
Finished Mar 17 02:53:37 PM PDT 24
Peak memory 201456 kb
Host smart-8ec37473-8fb0-4e9d-ab1f-0c8aa3bfce11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979614331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2979614331
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1519879045
Short name T544
Test name
Test status
Simulation time 80246209 ps
CPU time 1.41 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:53:36 PM PDT 24
Peak memory 210960 kb
Host smart-83e3e74c-538d-4a07-a986-591234017c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519879045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1519879045
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.425609746
Short name T578
Test name
Test status
Simulation time 664021651 ps
CPU time 5.93 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:53:42 PM PDT 24
Peak memory 273424 kb
Host smart-c5bc3bce-6f64-4c04-847f-9bfe95b2e7f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425609746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.425609746
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.17152246
Short name T850
Test name
Test status
Simulation time 2523594291 ps
CPU time 151.68 seconds
Started Mar 17 02:53:34 PM PDT 24
Finished Mar 17 02:56:06 PM PDT 24
Peak memory 589176 kb
Host smart-12dac502-16a7-46c0-b8f7-856f54f4a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17152246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.17152246
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1278429145
Short name T57
Test name
Test status
Simulation time 3350678317 ps
CPU time 104.42 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:55:19 PM PDT 24
Peak memory 862128 kb
Host smart-da7e3d2b-eaf5-4cee-bcb7-7523b8ec53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278429145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1278429145
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2833276569
Short name T1100
Test name
Test status
Simulation time 89185347 ps
CPU time 0.87 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 02:53:33 PM PDT 24
Peak memory 202452 kb
Host smart-d8b3fa24-dc02-4157-8d2f-6d921acf10fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833276569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2833276569
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3114174482
Short name T1140
Test name
Test status
Simulation time 138824958 ps
CPU time 3.87 seconds
Started Mar 17 02:53:44 PM PDT 24
Finished Mar 17 02:53:48 PM PDT 24
Peak memory 202740 kb
Host smart-b2b96076-ffd6-4213-9739-b83688b33808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114174482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3114174482
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.632188108
Short name T127
Test name
Test status
Simulation time 8319258647 ps
CPU time 140.55 seconds
Started Mar 17 02:53:40 PM PDT 24
Finished Mar 17 02:56:02 PM PDT 24
Peak memory 1494260 kb
Host smart-123ee09a-d673-4c3e-a982-007dcf6dc425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632188108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.632188108
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_override.886590189
Short name T817
Test name
Test status
Simulation time 46151373 ps
CPU time 0.64 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 02:53:33 PM PDT 24
Peak memory 201860 kb
Host smart-37839d80-d18f-4eb8-94b4-25f77de7aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886590189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.886590189
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1185784810
Short name T1051
Test name
Test status
Simulation time 9835826403 ps
CPU time 41.82 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:54:25 PM PDT 24
Peak memory 224560 kb
Host smart-c5f6266a-1d27-46ef-9968-390abbad099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185784810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1185784810
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2601146128
Short name T527
Test name
Test status
Simulation time 10567706913 ps
CPU time 36.32 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:54:15 PM PDT 24
Peak memory 267592 kb
Host smart-2bad196a-48ad-4ed1-ad38-28e0cc2f74bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601146128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2601146128
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.48785915
Short name T129
Test name
Test status
Simulation time 33360414376 ps
CPU time 1852.4 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 03:24:35 PM PDT 24
Peak memory 4447080 kb
Host smart-3b9740cc-ee9b-442b-beda-b8c34d5270d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48785915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.48785915
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2341449680
Short name T1003
Test name
Test status
Simulation time 981800119 ps
CPU time 18.97 seconds
Started Mar 17 02:53:33 PM PDT 24
Finished Mar 17 02:53:53 PM PDT 24
Peak memory 217012 kb
Host smart-3e8303f2-6db8-4c01-9001-80ca56f3e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341449680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2341449680
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2768926665
Short name T1071
Test name
Test status
Simulation time 10110465054 ps
CPU time 13.9 seconds
Started Mar 17 02:53:32 PM PDT 24
Finished Mar 17 02:53:46 PM PDT 24
Peak memory 322080 kb
Host smart-f33312d0-3a85-4782-84ca-7447c6d1e68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768926665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2768926665
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1342628084
Short name T389
Test name
Test status
Simulation time 10168925821 ps
CPU time 33.99 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:54:13 PM PDT 24
Peak memory 426504 kb
Host smart-13b1acb0-8336-463a-94be-309504b93328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342628084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1342628084
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1109168935
Short name T466
Test name
Test status
Simulation time 1606938062 ps
CPU time 4.4 seconds
Started Mar 17 02:53:36 PM PDT 24
Finished Mar 17 02:53:40 PM PDT 24
Peak memory 202624 kb
Host smart-976f5397-292e-4d7d-961a-1c0b776168db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109168935 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1109168935
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_perf.73650729
Short name T627
Test name
Test status
Simulation time 1484874876 ps
CPU time 2.77 seconds
Started Mar 17 02:53:35 PM PDT 24
Finished Mar 17 02:53:38 PM PDT 24
Peak memory 202496 kb
Host smart-6df4c899-5171-45bb-ab18-485e718e7431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73650729 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.i2c_target_perf.73650729
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.3007304119
Short name T575
Test name
Test status
Simulation time 15758296172 ps
CPU time 36.14 seconds
Started Mar 17 02:53:47 PM PDT 24
Finished Mar 17 02:54:26 PM PDT 24
Peak memory 221864 kb
Host smart-0fef774c-9461-467e-b049-6c7b5f7a9775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007304119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.3007304119
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1870962642
Short name T1088
Test name
Test status
Simulation time 11842648547 ps
CPU time 7.33 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 202768 kb
Host smart-ab1ac929-c8a0-419f-87af-1d6de5bd6d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870962642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1870962642
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.952192805
Short name T391
Test name
Test status
Simulation time 1175371828 ps
CPU time 6.45 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 208148 kb
Host smart-41745a33-827e-4ad8-99b5-0c072a745d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952192805 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.952192805
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.2308430208
Short name T1028
Test name
Test status
Simulation time 2853138135 ps
CPU time 3.92 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:53:47 PM PDT 24
Peak memory 202720 kb
Host smart-ed7e6ce2-0309-40e0-9ce8-1a09d73bd04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308430208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.2308430208
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2685041974
Short name T905
Test name
Test status
Simulation time 24003069 ps
CPU time 0.63 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 201588 kb
Host smart-cce037bc-374a-42b9-8d7c-3482bcfd852f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685041974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2685041974
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.4234591046
Short name T515
Test name
Test status
Simulation time 45155554 ps
CPU time 1.32 seconds
Started Mar 17 02:53:47 PM PDT 24
Finished Mar 17 02:53:50 PM PDT 24
Peak memory 210900 kb
Host smart-f251a40c-8d5e-4e18-acac-22b337a86b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234591046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.4234591046
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2756825506
Short name T579
Test name
Test status
Simulation time 2084606416 ps
CPU time 10.47 seconds
Started Mar 17 02:53:43 PM PDT 24
Finished Mar 17 02:53:54 PM PDT 24
Peak memory 323276 kb
Host smart-e2107bee-0b7b-4133-8df8-b20c3267f88c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756825506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2756825506
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.464145193
Short name T595
Test name
Test status
Simulation time 11467602667 ps
CPU time 106.2 seconds
Started Mar 17 02:53:52 PM PDT 24
Finished Mar 17 02:55:39 PM PDT 24
Peak memory 890080 kb
Host smart-475c974e-b890-4636-8ace-a4bf16081c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464145193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.464145193
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2182044441
Short name T271
Test name
Test status
Simulation time 4046641135 ps
CPU time 123.41 seconds
Started Mar 17 02:53:57 PM PDT 24
Finished Mar 17 02:56:01 PM PDT 24
Peak memory 493144 kb
Host smart-9d6df5a1-db0c-4e7f-80c5-8b1966648738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182044441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2182044441
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.451624235
Short name T706
Test name
Test status
Simulation time 551003541 ps
CPU time 0.91 seconds
Started Mar 17 02:53:41 PM PDT 24
Finished Mar 17 02:53:43 PM PDT 24
Peak memory 202616 kb
Host smart-66899bd2-e416-46ac-aca7-ca9db42b87cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451624235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.451624235
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1684863804
Short name T1000
Test name
Test status
Simulation time 857422346 ps
CPU time 4.48 seconds
Started Mar 17 02:53:52 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 202680 kb
Host smart-ac33623e-7ba9-4d1e-8bb0-0a4068bb7620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684863804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1684863804
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2293468509
Short name T847
Test name
Test status
Simulation time 4866912060 ps
CPU time 143.6 seconds
Started Mar 17 02:53:52 PM PDT 24
Finished Mar 17 02:56:16 PM PDT 24
Peak memory 1301348 kb
Host smart-aac87e04-8bd7-46e7-b98d-039ae3bbb1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293468509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2293468509
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2051876929
Short name T1126
Test name
Test status
Simulation time 10973813448 ps
CPU time 73.52 seconds
Started Mar 17 02:53:46 PM PDT 24
Finished Mar 17 02:55:00 PM PDT 24
Peak memory 295672 kb
Host smart-dd95bc7d-b5ae-4c3d-b83e-abe3ceb49243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051876929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2051876929
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2283050343
Short name T1230
Test name
Test status
Simulation time 25403873 ps
CPU time 0.61 seconds
Started Mar 17 02:53:55 PM PDT 24
Finished Mar 17 02:53:55 PM PDT 24
Peak memory 202072 kb
Host smart-2dd8fda9-b92e-4ebd-8ee6-29719ba4b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283050343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2283050343
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1285126671
Short name T833
Test name
Test status
Simulation time 6088400573 ps
CPU time 28.58 seconds
Started Mar 17 02:53:51 PM PDT 24
Finished Mar 17 02:54:20 PM PDT 24
Peak memory 210988 kb
Host smart-ad7c5e0e-ff9c-4fc5-8bf7-44a0f5dcd031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285126671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1285126671
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2701146675
Short name T147
Test name
Test status
Simulation time 1969120443 ps
CPU time 68.28 seconds
Started Mar 17 02:53:38 PM PDT 24
Finished Mar 17 02:54:47 PM PDT 24
Peak memory 308044 kb
Host smart-4affaa1c-4a7e-4099-97e9-959b0d6a1553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701146675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2701146675
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2204848591
Short name T207
Test name
Test status
Simulation time 6824731195 ps
CPU time 306.47 seconds
Started Mar 17 02:53:54 PM PDT 24
Finished Mar 17 02:59:01 PM PDT 24
Peak memory 1302116 kb
Host smart-11332490-339e-4788-9eb0-526d7abc379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204848591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2204848591
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1190432532
Short name T916
Test name
Test status
Simulation time 2819258605 ps
CPU time 31.59 seconds
Started Mar 17 02:53:44 PM PDT 24
Finished Mar 17 02:54:16 PM PDT 24
Peak memory 210908 kb
Host smart-c88ae69c-cd1f-46c2-98bc-4e331dcd1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190432532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1190432532
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1176438317
Short name T1073
Test name
Test status
Simulation time 1497953924 ps
CPU time 3.55 seconds
Started Mar 17 02:53:49 PM PDT 24
Finished Mar 17 02:53:53 PM PDT 24
Peak memory 202660 kb
Host smart-9d49b3ab-cde2-491e-a463-e6b7e82b0eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176438317 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1176438317
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3875051353
Short name T1204
Test name
Test status
Simulation time 10047864571 ps
CPU time 26.38 seconds
Started Mar 17 02:53:50 PM PDT 24
Finished Mar 17 02:54:17 PM PDT 24
Peak memory 356744 kb
Host smart-348672e9-8549-4b04-a851-0235a2923fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875051353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3875051353
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2622914772
Short name T1183
Test name
Test status
Simulation time 10031065846 ps
CPU time 98.16 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:55:28 PM PDT 24
Peak memory 707804 kb
Host smart-53e35774-d405-4abb-9266-6e6762c8a396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622914772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2622914772
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2566020527
Short name T1033
Test name
Test status
Simulation time 1378928347 ps
CPU time 6.29 seconds
Started Mar 17 02:53:46 PM PDT 24
Finished Mar 17 02:53:53 PM PDT 24
Peak memory 207160 kb
Host smart-72fe8a5d-f3b5-406b-988a-5f54bb38ad4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566020527 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2566020527
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.279842435
Short name T487
Test name
Test status
Simulation time 15981166935 ps
CPU time 201.63 seconds
Started Mar 17 02:53:52 PM PDT 24
Finished Mar 17 02:57:14 PM PDT 24
Peak memory 2394784 kb
Host smart-ba9a5fc5-d46d-4279-9d75-ef3300de22b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279842435 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.279842435
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3088979040
Short name T539
Test name
Test status
Simulation time 652591839 ps
CPU time 3.9 seconds
Started Mar 17 02:53:47 PM PDT 24
Finished Mar 17 02:53:54 PM PDT 24
Peak memory 202648 kb
Host smart-b1f68459-2c48-4211-abc3-5d345780d4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088979040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3088979040
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.3328733772
Short name T44
Test name
Test status
Simulation time 43513104025 ps
CPU time 61.66 seconds
Started Mar 17 02:53:54 PM PDT 24
Finished Mar 17 02:54:57 PM PDT 24
Peak memory 366680 kb
Host smart-64b9fd81-9869-4534-86e9-abad81e0b964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328733772 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.3328733772
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.175254042
Short name T1147
Test name
Test status
Simulation time 11794233998 ps
CPU time 61.52 seconds
Started Mar 17 02:53:42 PM PDT 24
Finished Mar 17 02:54:45 PM PDT 24
Peak memory 777360 kb
Host smart-e2851d55-9d61-47ac-beb0-dc26aba1c19e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175254042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.175254042
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.3641473664
Short name T810
Test name
Test status
Simulation time 1374155498 ps
CPU time 6.38 seconds
Started Mar 17 02:53:48 PM PDT 24
Finished Mar 17 02:53:56 PM PDT 24
Peak memory 211068 kb
Host smart-6231e178-f309-4793-869f-8f0de70462b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641473664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.3641473664
Directory /workspace/9.i2c_target_unexp_stop/latest
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