Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

141091

1

T1

90

T3

82

T52

164

ack

12800

1

T1

1

T2

33

T3

22

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	572	1			T3	1		T52	1		T18	1
high	31823	1			T1	22		T2	2		T3	15
med	57152	1			T1	30		T2	4		T3	41
sml	63755	1			T1	39		T2	27		T3	47
all_zero	589	1			T52	1		T12	1		T70	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76730

1

T1

42

T2

13

T3

51

auto[1]

77161

1

T1

49

T2

20

T3

53

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105501

1

T1

63

T2

25

T3

81

auto[1]

48390

1

T1

28

T2

8

T3

23

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147293

1

T1

91

T2

13

T3

95

auto[1]

6598

1

T2

20

T3

9

T52

18

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145334

1

T1

90

T2

20

T3

85

auto[1]

8557

1

T1

1

T2

13

T3

19

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146027

1

T1

90

T2

21

T3

86

auto[1]

7864

1

T1

1

T2

12

T3

18

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76730

1

T1

42

T2

13

T3

51

auto[1]

77161

1

T1

49

T2

20

T3

53

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105501

1

T1

63

T2

25

T3

81

auto[1]

48390

1

T1

28

T2

8

T3

23

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147293

1

T1

91

T2

13

T3

95

auto[1]

6598

1

T2

20

T3

9

T52

18

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145334

1

T1

90

T2

20

T3

85

auto[1]

8557

1

T1

1

T2

13

T3

19

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146027

1

T1

90

T2

21

T3

86

auto[1]

7864

1

T1

1

T2

12

T3

18

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T197

1

T198

1

T199

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T200

1

T201

1

T202

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T154

1

T203

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

236

1

T52

2

T29

1

T197

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

117

1

T52

1

T68

1

T204

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

117

1

T29

1

T205

1

T37

3

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

459

1

T3

2

T52

1

T18

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

259

1

T29

1

T197

2

T37

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

227

1

T3

3

T52

2

T19

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

434

1

T52

4

T19

1

T29

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

228

1

T205

1

T197

2

T68

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

243

1

T3

1

T19

1

T205

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T206

1

T207

1

T208

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T208

1

T186

1

T209

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T188

2

T210

1

T211

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	44912	1			T1	29		T3	23		T52	43
write_address_byte	8557	1			T1	1		T2	13		T3	19
read_with_ack	1858	1			T2	8		T18	2		T19	2
read_with_nack	4740	1			T2	12		T3	9		T52	18
stop_byte	7864	1			T1	1		T2	12		T3	18
write_address_byte_nak	4093	1			T3	14		T52	26		T18	5
data_byte_nack	141091	1			T1	90		T3	82		T52	164
stop_byte_nack	4658	1			T1	1		T3	12		T52	26
nakok_byte_nack	70759	1			T1	49		T3	43		T52	79
nakok_addr_byte_nack	2037	1			T3	7		T52	13		T18	3