Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38727379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12679894

1

T7

39

T1

3414

T8

71

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45824082	1			T7	94		T1	9467		T8	180
values[0x0]	2792204	1			T7	57		T1	50		T8	99
values[0x1]	2790987	1			T7	31		T1	54		T8	75

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28188769	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23218504

1

T7

71

T1

5009

T8

143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	163141	1			T1	42		T4	1		T2	200
valid_sources[0x01]	180158	1			T1	28		T8	5		T4	6
valid_sources[0x02]	168140	1			T1	52		T4	6		T2	269
valid_sources[0x03]	170479	1			T1	44		T4	3		T2	246
valid_sources[0x04]	162796	1			T1	33		T4	3		T2	222
valid_sources[0x05]	183421	1			T1	42		T4	1		T2	276
valid_sources[0x06]	169371	1			T1	22		T4	2		T2	195
valid_sources[0x07]	166430	1			T1	34		T8	12		T4	6
valid_sources[0x08]	176226	1			T1	36		T8	1		T4	2
valid_sources[0x09]	161560	1			T1	39		T8	1		T4	10
valid_sources[0x0a]	216685	1			T1	23		T4	4		T2	218
valid_sources[0x0b]	178074	1			T1	37		T8	1		T4	5
valid_sources[0x0c]	182913	1			T1	33		T8	10		T4	2
valid_sources[0x0d]	179951	1			T1	26		T4	6		T2	204
valid_sources[0x0e]	220276	1			T1	47		T8	2		T4	16
valid_sources[0x0f]	324874	1			T1	38		T8	17		T4	6
valid_sources[0x10]	164901	1			T1	54		T4	7		T2	217
valid_sources[0x11]	167299	1			T1	34		T4	6		T2	281
valid_sources[0x12]	182688	1			T1	33		T4	6		T2	230
valid_sources[0x13]	170258	1			T1	32		T4	7		T2	259
valid_sources[0x14]	164293	1			T1	36		T4	1		T2	227
valid_sources[0x15]	168244	1			T1	43		T4	4		T2	223
valid_sources[0x16]	179375	1			T1	39		T8	2		T4	2
valid_sources[0x17]	170389	1			T1	42		T4	8		T2	235
valid_sources[0x18]	171741	1			T1	39		T4	2		T2	157
valid_sources[0x19]	162522	1			T1	30		T4	5		T2	210
valid_sources[0x1a]	164850	1			T1	37		T4	9		T2	218
valid_sources[0x1b]	177214	1			T1	30		T8	1		T4	5
valid_sources[0x1c]	216154	1			T1	32		T8	4		T4	5
valid_sources[0x1d]	174790	1			T1	44		T4	9		T2	281
valid_sources[0x1e]	184938	1			T1	43		T4	3		T2	236
valid_sources[0x1f]	176924	1			T1	64		T8	3		T4	2
valid_sources[0x20]	171970	1			T1	31		T4	5		T2	243
valid_sources[0x21]	169424	1			T1	27		T4	9		T2	263
valid_sources[0x22]	174119	1			T1	41		T8	4		T4	4
valid_sources[0x23]	183926	1			T1	34		T4	3		T2	193
valid_sources[0x24]	165121	1			T1	37		T4	7		T2	167
valid_sources[0x25]	175361	1			T1	35		T4	11		T2	266
valid_sources[0x26]	557803	1			T1	18		T4	5		T2	220
valid_sources[0x27]	190257	1			T1	49		T8	2		T2	207
valid_sources[0x28]	176006	1			T1	38		T4	14		T2	231
valid_sources[0x29]	172601	1			T1	36		T8	3		T4	6
valid_sources[0x2a]	172040	1			T1	38		T4	6		T2	160
valid_sources[0x2b]	183826	1			T1	44		T4	19		T2	172
valid_sources[0x2c]	185900	1			T1	48		T4	3		T2	258
valid_sources[0x2d]	254072	1			T1	36		T4	2		T2	243
valid_sources[0x2e]	265867	1			T1	32		T4	6		T2	273
valid_sources[0x2f]	225927	1			T1	36		T8	1		T2	255
valid_sources[0x30]	823069	1			T1	28		T4	4		T2	261
valid_sources[0x31]	164440	1			T1	42		T4	8		T2	210
valid_sources[0x32]	167352	1			T1	41		T8	2		T4	5
valid_sources[0x33]	176920	1			T1	48		T4	3		T2	198
valid_sources[0x34]	168220	1			T1	36		T4	4		T2	183
valid_sources[0x35]	171728	1			T1	44		T4	7		T2	266
valid_sources[0x36]	164685	1			T1	37		T4	3		T2	173
valid_sources[0x37]	166445	1			T1	31		T4	2		T2	235
valid_sources[0x38]	162588	1			T1	38		T8	1		T4	3
valid_sources[0x39]	172651	1			T1	48		T4	13		T2	223
valid_sources[0x3a]	605105	1			T1	34		T4	16		T2	202
valid_sources[0x3b]	189479	1			T1	39		T8	1		T4	7
valid_sources[0x3c]	171609	1			T1	37		T4	5		T2	289
valid_sources[0x3d]	206888	1			T1	41		T8	2		T4	9
valid_sources[0x3e]	181146	1			T1	48		T4	1		T2	178
valid_sources[0x3f]	169087	1			T1	50		T8	2		T4	6
valid_sources[0x40]	168970	1			T1	20		T4	4		T2	245
valid_sources[0x41]	178359	1			T1	33		T8	2		T4	14
valid_sources[0x42]	192558	1			T1	26		T4	6		T2	200
valid_sources[0x43]	163878	1			T1	28		T4	4		T2	186
valid_sources[0x44]	174763	1			T1	40		T2	167		T3	23
valid_sources[0x45]	172933	1			T1	30		T4	8		T2	250
valid_sources[0x46]	199227	1			T1	42		T4	5		T2	193
valid_sources[0x47]	168461	1			T1	32		T4	9		T2	248
valid_sources[0x48]	279365	1			T1	36		T4	9		T2	242
valid_sources[0x49]	171030	1			T1	47		T4	5		T2	242
valid_sources[0x4a]	182916	1			T1	40		T8	4		T4	6
valid_sources[0x4b]	200609	1			T1	34		T4	4		T2	259
valid_sources[0x4c]	163452	1			T1	31		T4	7		T2	230
valid_sources[0x4d]	180618	1			T1	36		T4	8		T2	219
valid_sources[0x4e]	173214	1			T1	39		T4	4		T2	245
valid_sources[0x4f]	164173	1			T1	40		T4	15		T2	220
valid_sources[0x50]	436946	1			T1	29		T8	1		T4	1
valid_sources[0x51]	175974	1			T1	32		T8	3		T4	8
valid_sources[0x52]	162495	1			T1	45		T4	1		T2	192
valid_sources[0x53]	175655	1			T1	30		T8	1		T4	2
valid_sources[0x54]	291580	1			T1	28		T4	10		T2	230
valid_sources[0x55]	183861	1			T1	38		T4	4		T2	218
valid_sources[0x56]	187198	1			T1	32		T8	4		T4	3
valid_sources[0x57]	172609	1			T1	36		T2	259		T3	19
valid_sources[0x58]	175198	1			T1	29		T8	2		T4	3
valid_sources[0x59]	173354	1			T1	27		T4	1		T2	185
valid_sources[0x5a]	165975	1			T1	29		T4	7		T2	246
valid_sources[0x5b]	180627	1			T1	29		T8	8		T4	12
valid_sources[0x5c]	240805	1			T1	36		T8	1		T4	8
valid_sources[0x5d]	169755	1			T1	34		T4	9		T2	190
valid_sources[0x5e]	169325	1			T1	53		T8	9		T4	3
valid_sources[0x5f]	181907	1			T1	29		T4	7		T2	184
valid_sources[0x60]	220855	1			T1	40		T8	2		T4	5
valid_sources[0x61]	197071	1			T1	33		T4	9		T2	201
valid_sources[0x62]	167410	1			T1	30		T4	6		T2	212
valid_sources[0x63]	286182	1			T1	52		T8	3		T4	1
valid_sources[0x64]	211509	1			T1	37		T4	2		T2	189
valid_sources[0x65]	183589	1			T1	29		T4	3		T2	236
valid_sources[0x66]	163728	1			T1	28		T8	3		T4	6
valid_sources[0x67]	180080	1			T1	44		T4	5		T2	250
valid_sources[0x68]	166749	1			T1	28		T8	3		T4	3
valid_sources[0x69]	166433	1			T1	39		T4	6		T2	154
valid_sources[0x6a]	171970	1			T1	40		T4	9		T2	262
valid_sources[0x6b]	185982	1			T1	57		T4	9		T2	215
valid_sources[0x6c]	169584	1			T1	46		T4	8		T2	275
valid_sources[0x6d]	175775	1			T1	48		T2	224		T3	40
valid_sources[0x6e]	161623	1			T1	38		T8	1		T4	5
valid_sources[0x6f]	167737	1			T1	19		T4	7		T2	206
valid_sources[0x70]	165922	1			T1	32		T4	2		T2	202
valid_sources[0x71]	210088	1			T1	35		T8	7		T4	3
valid_sources[0x72]	179600	1			T1	39		T8	1		T4	7
valid_sources[0x73]	183556	1			T1	41		T4	7		T2	198
valid_sources[0x74]	163247	1			T1	42		T4	8		T2	209
valid_sources[0x75]	182687	1			T1	40		T4	10		T2	237
valid_sources[0x76]	181174	1			T1	32		T8	1		T4	4
valid_sources[0x77]	193386	1			T1	42		T4	7		T2	291
valid_sources[0x78]	182924	1			T1	37		T4	1		T2	297
valid_sources[0x79]	166530	1			T1	48		T4	4		T2	204
valid_sources[0x7a]	178283	1			T1	28		T4	6		T2	233
valid_sources[0x7b]	186608	1			T1	33		T4	9		T2	231
valid_sources[0x7c]	174707	1			T1	45		T8	1		T4	11
valid_sources[0x7d]	179331	1			T1	41		T4	11		T2	218
valid_sources[0x7e]	244960	1			T1	50		T4	2		T2	204
valid_sources[0x7f]	185886	1			T1	46		T4	2		T2	269
valid_sources[0x80]	177889	1			T1	35		T4	7		T2	251

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10476202

1

T7

1

T1

3371

T8

1

values[0x0]

all_enables

biggest_size

1409235

1

T7

31

T1

30

T8

49

values[0x1]

all_enables

biggest_size

794457

1

T7

7

T1

13

T8

21