Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.14	93.09	87.45		45.81	89.36	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	83.14	93.09	87.45		45.81	89.36	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.14	93.09	87.45		45.81	89.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.14	93.09	87.45		45.81	89.36	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		608	566	93.09
ALWAYS	169	17	17	100.00
CONT_ASSIGN	193	1	1	100.00
ALWAYS	196	3	3	100.00
ALWAYS	209	9	9	100.00
ALWAYS	226	5	5	100.00
ALWAYS	239	6	5	83.33
ALWAYS	250	7	7	100.00
ALWAYS	263	6	6	100.00
ALWAYS	274	5	5	100.00
ALWAYS	281	7	7	100.00
ALWAYS	294	5	5	100.00
ALWAYS	308	8	8	100.00
ALWAYS	320	8	7	87.50
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
ALWAYS	342	9	9	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	363	7	7	100.00
ALWAYS	374	5	5	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
ALWAYS	460	6	6	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	483	4	4	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
ALWAYS	508	199	178	89.45
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	907	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
ALWAYS	925	260	241	92.69
ALWAYS	1479	3	3	100.00
ALWAYS	1488	5	5	100.00
CONT_ASSIGN	1497	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1501	1	1	100.00
CONT_ASSIGN	1504	1	1	100.00
CONT_ASSIGN	1508	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
185	1	1
186	1	1
188	1	1
193	1	1
196	1	1
197	1	1
199	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
215	1	1
216	1	1
217	1	1
219	1	1
226	1	1
227	1	1
228	1	1
229	1	1
231	1	1
239	1	1
240	1	1
241	1	1
242	0	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
257	1	1
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
274	2	2
275	2	2
276	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
288	1	1
294	1	1
295	1	1
296	1	1
298	1	1
299	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
320	1	1
321	1	1
322	1	1
323	0	1
324	1	1
325	1	1
326	1	1
327	1	1
			MISSING_ELSE
332	1	1
335	1	1
338	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
349	2	2
350	1	1
352	1	1
357	1	1
358	1	1
359	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	2	2
			MISSING_ELSE
			MISSING_ELSE
374	1	1
375	1	1
376	1	1
377	2	2
			MISSING_ELSE
			MISSING_ELSE
391	1	1
394	1	1
395	1	1
455	1	1
460	1	1
461	1	1
462	1	1
466	1	1
467	1	1
468	1	1
			MISSING_ELSE
478	1	1
483	1	1
484	1	1
485	1	1
486	1	1
			MISSING_ELSE
500	1	1
504	1	1
508	1	1
509	1	1
510	1	1
511	1	1
512	1	1
513	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
526	1	1
527	1	1
532	1	1
533	1	1
534	0	1
535	0	1
537	1	1
538	1	1
543	1	1
544	1	1
545	1	1
546	2	2
			MISSING_ELSE
550	1	1
551	1	1
552	1	1
556	1	1
557	1	1
558	1	1
561	1	1
562	1	1
563	1	1
565	1	1
567	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	2	2
			MISSING_ELSE
576	2	2
			MISSING_ELSE
580	1	1
581	1	1
582	1	1
586	1	1
587	1	1
588	1	1
592	1	1
593	1	1
594	1	1
595	2	2
			MISSING_ELSE
596	1	1
597	2	2
			MISSING_ELSE
598	2	2
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
608	1	1
609	1	1
610	1	1
614	1	1
615	1	1
616	1	1
617	2	2
			MISSING_ELSE
618	2	2
			MISSING_ELSE
622	1	1
623	1	1
624	1	1
625	1	1
626	1	1
			MISSING_ELSE
631	1	1
632	1	1
636	2	2
637	2	2
638	1	1
642	1	1
643	2	2
644	2	2
645	1	1
646	1	1
647	1	1
648	2	2
			MISSING_ELSE
649	2	2
			MISSING_ELSE
653	1	1
654	2	2
655	2	2
656	1	1
657	1	1
661	1	1
662	1	1
663	1	1
667	1	1
668	1	1
669	1	1
673	1	1
674	1	1
675	1	1
676	1	1
680	1	1
686	1	1
690	1	1
691	2	2
692	1	1
693	1	1
697	1	1
701	1	1
702	1	1
706	1	1
710	1	1
711	1	1
715	1	1
716	1	1
720	1	1
721	1	1
724	1	1
725	1	1
729	0	1
730	0	1
733	1	1
734	1	1
			MISSING_ELSE
740	1	1
744	1	1
745	1	1
749	1	1
752	1	1
756	1	1
759	1	1
763	1	1
766	1	1
767	1	1
769	1	1
			MISSING_ELSE
774	1	1
775	1	1
776	1	1
780	1	1
784	1	1
788	1	1
789	1	1
793	1	1
794	1	1
798	1	1
799	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	0	1
812	0	1
813	0	1
817	0	1
818	0	1
822	0	1
823	0	1
825	0	1
831	0	1
832	0	1
836	0	1
837	0	1
			==> MISSING_ELSE
843	0	1
844	0	1
846	0	1
847	0	1
848	0	1
852	1	1
853	1	1
857	1	1
858	1	1
859	1	1
863	1	1
864	1	1
867	1	1
868	1	1
869	1	1
893	1	1
895	1	1
896	1	1
898	1	1
			MISSING_ELSE
902	1	1
903	1	1
907	1	1
916	1	1
921	1	1
925	1	1
926	1	1
927	1	1
928	1	1
929	1	1
930	1	1
931	1	1
932	1	1
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
943	1	1
946	2	2
947	1	1
948	2	2
			MISSING_ELSE
			MISSING_ELSE
950	1	1
954	1	1
955	1	1
956	1	1
957	1	1
958	1	1
			MISSING_ELSE
963	1	1
964	1	1
965	1	1
966	1	1
			MISSING_ELSE
971	1	1
972	1	1
973	1	1
974	1	1
			MISSING_ELSE
979	1	1
980	1	1
981	1	1
982	1	1
983	1	1
984	1	1
986	1	1
987	1	1
			MISSING_ELSE
993	1	1
994	1	1
995	1	1
996	1	1
997	1	1
			MISSING_ELSE
1002	1	1
1003	1	1
1004	1	1
1005	1	1
1006	1	1
1007	1	1
1008	1	1
1009	1	1
1011	1	1
1012	1	1
			MISSING_ELSE
1019	1	1
1020	1	1
1021	1	1
1022	1	1
			MISSING_ELSE
1027	1	1
1028	1	1
1029	1	1
1030	1	1
			MISSING_ELSE
1035	1	1
1036	1	1
1037	1	1
1038	1	1
1039	1	1
1041	1	1
1042	1	1
1043	1	1
			MISSING_ELSE
1049	1	1
1050	1	1
1051	1	1
1052	1	1
			MISSING_ELSE
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
			MISSING_ELSE
1066	1	1
1067	1	1
1068	1	1
1069	1	1
1070	1	1
1071	1	1
1072	1	1
1074	1	1
1075	1	1
			MISSING_ELSE
1082	1	1
1083	1	1
1084	1	1
1085	1	1
1086	1	1
			MISSING_ELSE
1091	1	1
1092	1	1
1093	1	1
1094	1	1
1095	1	1
			MISSING_ELSE
1100	1	1
1101	1	1
1102	1	1
1103	1	1
1104	1	1
1105	1	1
1106	1	1
1107	1	1
1109	1	1
1110	1	1
1111	1	1
1114	1	1
1115	1	1
1116	1	1
1117	1	1
			MISSING_ELSE
1123	1	1
1124	1	1
1125	1	1
1126	1	1
			MISSING_ELSE
1131	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
			MISSING_ELSE
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1148	1	1
1149	1	1
1150	1	1
			MISSING_ELSE
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1179	1	1
1180	1	1
1181	1	1
1183	1	1
1184	1	1
1185	1	1
1190	1	1
1192	1	1
1193	1	1
			MISSING_ELSE
1195	1	1
1199	1	1
1200	1	1
1201	1	1
1206	0	1
1207	0	1
1209	0	1
1210	0	1
1213	1	1
1215	1	1
1216	1	1
1219	1	1
			MISSING_ELSE
1225	1	1
1226	1	1
			MISSING_ELSE
1231	2	2
			MISSING_ELSE
1235	1	1
1236	1	1
1237	1	1
1238	1	1
			MISSING_ELSE
1243	1	1
1249	1	1
1250	0	1
1251	1	1
1252	1	1
1253	1	1
1254	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1260	1	1
1261	1	1
1263	1	1
1264	1	1
1265	1	1
1270	2	2
			MISSING_ELSE
1274	1	1
1275	1	1
1276	1	1
1277	1	1
			MISSING_ELSE
1282	1	1
1283	1	1
1284	1	1
1286	1	1
1287	1	1
1288	1	1
			MISSING_ELSE
1294	1	1
1295	1	1
			MISSING_ELSE
1301	1	1
1303	1	1
1304	1	1
1307	1	1
			MISSING_ELSE
1315	1	1
1319	1	1
1326	1	1
1327	0	1
1329	1	1
1331	1	1
1332	1	1
			MISSING_ELSE
1337	1	1
1338	1	1
			MISSING_ELSE
1343	2	2
			MISSING_ELSE
1347	1	1
1348	1	1
1349	1	1
1350	1	1
			MISSING_ELSE
1355	1	1
1358	1	1
			MISSING_ELSE
1363	0	1
1364	0	1
			==> MISSING_ELSE
1369	0	1
1370	0	1
			==> MISSING_ELSE
1375	0	1
1376	0	1
1377	0	1
1378	0	1
			==> MISSING_ELSE
1383	0	1
1385	0	1
			==> MISSING_ELSE
1395	0	1
1401	0	1
			==> MISSING_ELSE
1407	1	1
1408	1	1
1415	1	1
1416	1	1
1417	1	1
1420	1	1
			MISSING_ELSE
1425	1	1
1426	1	1
			MISSING_ELSE
1435	1	1
1436	1	1
			MISSING_ELSE
1460	1	1
1469	0	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
			MISSING_ELSE
1479	1	1
1480	1	1
1482	1	1
1488	1	1
1489	1	1
1490	1	1
1492	1	1
1493	1	1
1497	1	1
1498	1	1
1501	1	1
1504	1	1
1508	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	263	230	87.45
Logical	263	230	87.45
Non-Logical	0	0
Event	0	0

 LINE       185
 EXPRESSION ((stretch_idle_cnt == '0) || target_enable_i)
             ------------1-----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T1,T8

 LINE       185
 SUB-EXPRESSION (stretch_idle_cnt == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T1,T8

 LINE       211
 EXPRESSION (stretch_en && scl_d && ((!scl_i)))
             -----1----    --2--    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T9,T10

 LINE       216
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T12,T13,T14

 LINE       310
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T17

 LINE       322
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T18,T19,T20
1	1	Not Covered

 LINE       332
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       332
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T4,T2

 LINE       332
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       332
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       335
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       335
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T4
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T4,T2

 LINE       335
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       335
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T8,T4

 LINE       338
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T4,T2

 LINE       346
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       349
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T8
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T5,T6

 LINE       357
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       358
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       359
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       367
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T4,T2

 LINE       376
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T4,T2

 LINE       462
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T1,T2,T3

 LINE       467
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       478
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T8
0	1	Covered	T1,T8,T2
1	0	Covered	T2,T3,T21

 LINE       478
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T1,T8
1	1	1	Covered	T2,T3,T21

 LINE       478
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T7,T1,T8
1	1	0	Covered	T7,T1,T8
1	1	1	Covered	T1,T8,T2

 LINE       478
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       485
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T2

 LINE       504
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T22,T23,T24
1	0	1	1	Covered	T4,T5,T6
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T25,T26,T27

 LINE       533
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T8
1	1	Not Covered

 LINE       575
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T28

 LINE       576
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       595
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T30,T32,T33
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T34,T35,T36
1	1	1	1	Covered	T32,T34,T33

 LINE       597
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T28

 LINE       598
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T11
1	1	Covered	T28

 LINE       618
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       624
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T11

 LINE       624
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       624
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       637
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       644
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       648
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T11
1	1	Covered	T28

 LINE       649
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T31,T15,T37

 LINE       655
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       686
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T38
1	0	Covered	T18,T19,T20
1	1	Covered	T1,T2,T3

 LINE       724
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       801
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       825
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       846
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       893
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T8
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       896
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       907
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Not Covered

 LINE       916
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T1,T8

 LINE       946
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T1,T8

 LINE       954
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       963
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       971
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       980
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T2,T3

 LINE       994
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1003
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1007
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1019
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1027
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1035
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1049
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1057
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1066
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1069
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1083
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1092
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1101
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1103
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T3,T11

 LINE       1123
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1131
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1141
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1161
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T38
1	0	Covered	T18,T19,T20
1	1	Covered	T1,T2,T3

 LINE       1178
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1190
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       1225
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T39,T40
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1225
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       1243
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       1249
 EXPRESSION (stretch_addr && ((!nack_next_byte_q)))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       1282
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       1326
 EXPRESSION (acq_fifo_full_or_last_space || nack_next_byte_q)
             -------------1-------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

 LINE       1337
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T39,T40
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1337
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       1355
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T39,T40
1	Covered	T4,T5,T6

 LINE       1358
 EXPRESSION (stretch_rx ? StretchAcqFull : AcquireByte)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T41,T42,T43

 LINE       1363
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1363
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1383
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1395
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1401
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1425
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1435
 EXPRESSION (((~stretch_rx)) || nack_timeout)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Not Covered
1	0	Covered	T41,T42,T43

 LINE       1460
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       1501
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T9,T10

 LINE       1504
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T44
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T11,T12
1	1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	47	42	89.36	(Not included in score)
Transitions	155	71	45.81
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1348	Covered	T4,T5,T6
AcquireAckPulse	1343	Covered	T4,T5,T6
AcquireAckSetup	1338	Covered	T4,T5,T6
AcquireAckWait	1329	Covered	T4,T5,T6
AcquireByte	1254	Covered	T4,T5,T6
AcquireStart	1471	Covered	T4,T5,T6
Active	948	Covered	T7,T1,T8
AddrAckHold	1236	Covered	T4,T5,T6
AddrAckPulse	1231	Covered	T4,T5,T6
AddrAckSetup	1226	Covered	T4,T5,T6
AddrAckWait	1209	Covered	T4,T5,T6
AddrRead	1192	Covered	T4,T5,T6
ClockLow	972	Covered	T7,T1,T8
ClockLowAck	1008	Covered	T1,T2,T3
ClockPulse	986	Covered	T1,T2,T3
ClockPulseAck	1020	Covered	T1,T2,T3
ClockStart	964	Covered	T1,T2,T3
ClockStop	1037	Covered	T1,T2,T3
HoldBit	995	Covered	T1,T2,T3
HoldDevAck	1028	Covered	T1,T2,T3
HoldStart	955	Covered	T1,T2,T3
HoldStop	1132	Covered	T1,T2,T3
HostClockLowAck	1070	Covered	T2,T3,T11
HostClockPulseAck	1084	Covered	T2,T3,T11
HostHoldBitAck	1093	Covered	T2,T3,T11
Idle	946	Covered	T7,T1,T8
NackHold	1376	Not Covered
NackPulse	1370	Not Covered
NackSetup	1364	Not Covered
NackWait	1207	Not Covered
PopFmtFifo	1041	Covered	T1,T2,T3
ReadClockLow	1074	Covered	T2,T3,T11
ReadClockPulse	1050	Covered	T2,T3,T11
ReadHoldBit	1058	Covered	T2,T3,T11
SetupStart	983	Covered	T1,T2,T3
SetupStop	1124	Covered	T1,T2,T3
StretchAcqFull	1358	Covered	T41,T42,T43
StretchAddr	1250	Not Covered
StretchTx	1261	Covered	T4,T5,T6
StretchTxSetup	1415	Covered	T4,T5,T6
TransmitAck	1284	Covered	T4,T5,T6
TransmitAckPulse	1295	Covered	T4,T5,T6
TransmitHold	1275	Covered	T4,T5,T6
TransmitPulse	1270	Covered	T4,T5,T6
TransmitSetup	1263	Covered	T4,T5,T6
TransmitWait	1252	Covered	T4,T5,T6
WaitForStop	1307	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1358	Covered	T4,T5,T6
AcquireAckHold->AcquireStart	1471	Not Covered
AcquireAckHold->Idle	1469	Not Covered
AcquireAckHold->StretchAcqFull	1358	Covered	T41,T42,T43
AcquireAckPulse->AcquireAckHold	1348	Covered	T4,T5,T6
AcquireAckPulse->AcquireStart	1471	Not Covered
AcquireAckPulse->Idle	1469	Not Covered
AcquireAckSetup->AcquireAckPulse	1343	Covered	T4,T5,T6
AcquireAckSetup->AcquireStart	1471	Not Covered
AcquireAckSetup->Idle	1469	Not Covered
AcquireAckWait->AcquireAckSetup	1338	Covered	T4,T5,T6
AcquireAckWait->AcquireStart	1471	Not Covered
AcquireAckWait->Idle	1469	Not Covered
AcquireByte->AcquireAckWait	1329	Covered	T4,T5,T6
AcquireByte->AcquireStart	1471	Covered	T4,T5,T6
AcquireByte->Idle	1469	Covered	T4,T5,T6
AcquireByte->NackWait	1327	Not Covered
AcquireStart->AddrRead	1192	Covered	T4,T5,T6
AcquireStart->Idle	1469	Not Covered
Active->AcquireStart	1471	Not Covered
Active->ClockLow	1166	Covered	T7,T1,T8
Active->Idle	1469	Not Covered
Active->ReadClockLow	1158	Covered	T2,T3,T11
Active->SetupStart	1162	Covered	T1,T2,T3
AddrAckHold->AcquireByte	1254	Covered	T4,T5,T6
AddrAckHold->AcquireStart	1471	Not Covered
AddrAckHold->Idle	1469	Not Covered
AddrAckHold->StretchAddr	1250	Not Covered
AddrAckHold->TransmitWait	1252	Covered	T4,T5,T6
AddrAckPulse->AcquireStart	1471	Not Covered
AddrAckPulse->AddrAckHold	1236	Covered	T4,T5,T6
AddrAckPulse->Idle	1469	Not Covered
AddrAckSetup->AcquireStart	1471	Not Covered
AddrAckSetup->AddrAckPulse	1231	Covered	T4,T5,T6
AddrAckSetup->Idle	1469	Not Covered
AddrAckWait->AcquireStart	1471	Not Covered
AddrAckWait->AddrAckSetup	1226	Covered	T4,T5,T6
AddrAckWait->Idle	1469	Not Covered
AddrRead->AcquireStart	1471	Covered	T45,T46,T47
AddrRead->AddrAckWait	1209	Covered	T4,T5,T6
AddrRead->Idle	1219	Covered	T22,T25,T26
AddrRead->NackWait	1207	Not Covered
ClockLow->AcquireStart	1471	Not Covered
ClockLow->ClockPulse	986	Covered	T1,T2,T3
ClockLow->Idle	1469	Covered	T30,T48,T49
ClockLow->SetupStart	983	Covered	T18,T19,T20
ClockLowAck->AcquireStart	1471	Not Covered
ClockLowAck->ClockPulseAck	1020	Covered	T1,T2,T3
ClockLowAck->Idle	1469	Not Covered
ClockPulse->AcquireStart	1471	Not Covered
ClockPulse->HoldBit	995	Covered	T1,T2,T3
ClockPulse->Idle	1469	Covered	T30,T48,T49
ClockPulseAck->AcquireStart	1471	Not Covered
ClockPulseAck->HoldDevAck	1028	Covered	T1,T2,T3
ClockPulseAck->Idle	1469	Covered	T30,T48,T49
ClockStart->AcquireStart	1471	Not Covered
ClockStart->ClockLow	972	Covered	T1,T2,T3
ClockStart->Idle	1469	Not Covered
ClockStop->AcquireStart	1471	Not Covered
ClockStop->Idle	1469	Not Covered
ClockStop->SetupStop	1124	Covered	T1,T2,T3
HoldBit->AcquireStart	1471	Not Covered
HoldBit->ClockLow	1011	Covered	T1,T2,T3
HoldBit->ClockLowAck	1008	Covered	T1,T2,T3
HoldBit->Idle	1469	Covered	T50,T28,T51
HoldDevAck->AcquireStart	1471	Not Covered
HoldDevAck->ClockStop	1037	Covered	T1,T3,T52
HoldDevAck->Idle	1469	Not Covered
HoldDevAck->PopFmtFifo	1041	Covered	T1,T2,T3
HoldStart->AcquireStart	1471	Not Covered
HoldStart->ClockStart	964	Covered	T1,T2,T3
HoldStart->Idle	1469	Not Covered
HoldStop->AcquireStart	1471	Not Covered
HoldStop->Idle	1144	Covered	T53,T15,T16
HoldStop->PopFmtFifo	1148	Covered	T1,T2,T3
HostClockLowAck->AcquireStart	1471	Not Covered
HostClockLowAck->HostClockPulseAck	1084	Covered	T2,T3,T11
HostClockLowAck->Idle	1469	Not Covered
HostClockPulseAck->AcquireStart	1471	Not Covered
HostClockPulseAck->HostHoldBitAck	1093	Covered	T2,T3,T11
HostClockPulseAck->Idle	1469	Not Covered
HostHoldBitAck->AcquireStart	1471	Not Covered
HostHoldBitAck->ClockStop	1105	Covered	T2,T3,T11
HostHoldBitAck->Idle	1469	Not Covered
HostHoldBitAck->PopFmtFifo	1109	Covered	T2,T12,T18
HostHoldBitAck->ReadClockLow	1114	Covered	T2,T3,T11
Idle->AcquireStart	1471	Covered	T4,T5,T6
Idle->Active	948	Covered	T7,T1,T8
NackHold->AcquireStart	1471	Not Covered
NackHold->Idle	1385	Not Covered
NackPulse->AcquireStart	1471	Not Covered
NackPulse->Idle	1469	Not Covered
NackPulse->NackHold	1376	Not Covered
NackSetup->AcquireStart	1471	Not Covered
NackSetup->Idle	1469	Not Covered
NackSetup->NackPulse	1370	Not Covered
NackWait->AcquireStart	1471	Not Covered
NackWait->Idle	1469	Not Covered
NackWait->NackSetup	1364	Not Covered
PopFmtFifo->AcquireStart	1471	Not Covered
PopFmtFifo->Active	1183	Covered	T1,T2,T3
PopFmtFifo->ClockStop	1175	Covered	T53,T15,T16
PopFmtFifo->Idle	1179	Covered	T1,T2,T3
ReadClockLow->AcquireStart	1471	Not Covered
ReadClockLow->Idle	1469	Not Covered
ReadClockLow->ReadClockPulse	1050	Covered	T2,T3,T11
ReadClockPulse->AcquireStart	1471	Not Covered
ReadClockPulse->Idle	1469	Not Covered
ReadClockPulse->ReadHoldBit	1058	Covered	T2,T3,T11
ReadHoldBit->AcquireStart	1471	Not Covered
ReadHoldBit->HostClockLowAck	1070	Covered	T2,T3,T11
ReadHoldBit->Idle	1469	Not Covered
ReadHoldBit->ReadClockLow	1074	Covered	T2,T3,T11
SetupStart->AcquireStart	1471	Not Covered
SetupStart->HoldStart	955	Covered	T1,T2,T3
SetupStart->Idle	1469	Not Covered
SetupStop->AcquireStart	1471	Not Covered
SetupStop->HoldStop	1132	Covered	T1,T2,T3
SetupStop->Idle	1469	Not Covered
StretchAcqFull->AcquireByte	1436	Covered	T41,T42,T43
StretchAcqFull->AcquireStart	1471	Not Covered
StretchAcqFull->Idle	1469	Not Covered
StretchAddr->AcquireByte	1401	Not Covered
StretchAddr->AcquireStart	1471	Not Covered
StretchAddr->Idle	1469	Not Covered
StretchAddr->StretchTx	1401	Not Covered
StretchTx->AcquireStart	1471	Not Covered
StretchTx->Idle	1469	Not Covered
StretchTx->StretchTxSetup	1415	Covered	T4,T5,T6
StretchTxSetup->AcquireStart	1471	Not Covered
StretchTxSetup->Idle	1469	Not Covered
StretchTxSetup->TransmitSetup	1426	Covered	T4,T5,T6
TransmitAck->AcquireStart	1471	Not Covered
TransmitAck->Idle	1469	Not Covered
TransmitAck->TransmitAckPulse	1295	Covered	T4,T5,T6
TransmitAckPulse->AcquireStart	1471	Covered	T54
TransmitAckPulse->Idle	1469	Not Covered
TransmitAckPulse->TransmitWait	1304	Covered	T4,T5,T6
TransmitAckPulse->WaitForStop	1307	Covered	T4,T5,T6
TransmitHold->AcquireStart	1471	Not Covered
TransmitHold->Idle	1469	Not Covered
TransmitHold->TransmitAck	1284	Covered	T4,T5,T6
TransmitHold->TransmitSetup	1288	Covered	T4,T5,T6
TransmitPulse->AcquireStart	1471	Covered	T27,T55,T56
TransmitPulse->Idle	1469	Covered	T27,T55,T56
TransmitPulse->TransmitHold	1275	Covered	T4,T5,T6
TransmitSetup->AcquireStart	1471	Not Covered
TransmitSetup->Idle	1469	Not Covered
TransmitSetup->TransmitPulse	1270	Covered	T4,T5,T6
TransmitWait->AcquireStart	1471	Not Covered
TransmitWait->Idle	1469	Not Covered
TransmitWait->StretchTx	1261	Covered	T4,T5,T6
TransmitWait->TransmitSetup	1263	Covered	T4,T5,T6
WaitForStop->AcquireStart	1471	Covered	T4,T5,T6
WaitForStop->Idle	1469	Covered	T4,T5,T6

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		282	252	89.36
IF	170	14	13	92.86
IF	196	2	2	100.00
IF	209	5	5	100.00
IF	226	3	3	100.00
IF	239	4	3	75.00
IF	250	4	4	100.00
IF	263	4	4	100.00
IF	274	3	3	100.00
IF	281	4	4	100.00
IF	294	2	2	100.00
IF	308	5	5	100.00
IF	320	5	4	80.00
IF	342	5	5	100.00
IF	363	5	5	100.00
IF	374	4	4	100.00
IF	460	4	4	100.00
IF	483	3	3	100.00
CASE	527	79	70	88.61
IF	893	3	3	100.00
CASE	943	116	99	85.34
IF	1460	4	3	75.00
IF	1479	2	2	100.00
IF	1488	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	if (load_tcount)
-2-:	171	case (tcount_sel)
-3-:	185	if (((stretch_idle_cnt == '0) || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T1,T2,T3
1	tHoldStart	-	Covered	T1,T2,T3
1	tSetupData	-	Covered	T4,T5,T6
1	tClockStart	-	Covered	T1,T4,T2
1	tClockLow	-	Covered	T7,T1,T8
1	tClockPulse	-	Covered	T1,T2,T3
1	tHoldBit	-	Covered	T1,T2,T3
1	tClockStop	-	Covered	T1,T2,T3
1	tSetupStop	-	Covered	T1,T2,T3
1	tHoldStop	-	Covered	T1,T2,T3
1	tNoDelay	-	Covered	T1,T2,T3
1	default	-	Not Covered
0	-	1	Covered	T7,T1,T8
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	209	if ((!rst_ni))
-2-:	211	if (((stretch_en && scl_d) && (!scl_i)))
-3-:	213	if (((!target_idle_o) && event_host_timeout_o))
-4-:	216	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T7,T1,T8
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T6,T9,T10
0	0	0	1	Covered	T4,T5,T6
0	0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	226	if ((!rst_ni))
-2-:	228	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T41,T42,T43
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	239	if ((!rst_ni))
-2-:	241	if (set_nack_next_byte)
-3-:	243	if (clear_nack_next_byte)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	-	Not Covered
0	0	1	Covered	T7,T1,T8
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (bit_clr)
-3-:	254	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	263	if ((!rst_ni))
-2-:	265	if (read_byte_clr)
-3-:	267	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	-	Covered	T2,T3,T11
0	0	1	Covered	T2,T3,T11
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	274	if ((!fmt_flag_read_bytes_i))
-2-:	275	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T12,T13,T14
0	0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if (byte_clr)
-3-:	285	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	-	Covered	T2,T3,T11
0	0	1	Covered	T2,T3,T11
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	294	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	308	if ((!rst_ni))
-2-:	310	if ((trans_started && (!host_enable_i)))
-3-:	312	if (log_start)
-4-:	314	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T7,T1,T8
0	1	-	-	Covered	T15,T16,T17
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	322	if ((pend_restart && (!host_enable_i)))
-3-:	324	if (req_restart)
-4-:	326	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T7,T1,T8
0	1	-	-	Not Covered
0	0	1	-	Covered	T18,T19,T20
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	342	if ((!rst_ni))
-2-:	344	if (start_det)
-3-:	346	if ((scl_i_q && (!scl_i)))
-4-:	349	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T7,T1,T8
0	1	-	-	Covered	T4,T5,T6
0	0	1	1	Covered	T1,T4,T2
0	0	1	0	Covered	T7,T1,T8
0	0	0	-	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	363	if ((!rst_ni))
-2-:	365	if (input_byte_clr)
-3-:	367	if (((!scl_i_q) && scl_i))
-4-:	368	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T7,T1,T8
0	1	-	-	Covered	T4,T5,T6
0	0	1	1	Covered	T1,T4,T2
0	0	1	0	Covered	T1,T4,T2
0	0	0	-	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	374	if ((!rst_ni))
-2-:	376	if (((!scl_i_q) && scl_i))
-3-:	377	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	1	Covered	T1,T4,T2
0	1	0	Covered	T1,T4,T2
0	0	-	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	460	if ((!rst_ni))
-2-:	462	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	467	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T1,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T1,T8
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	483	if ((!rst_ni))
-2-:	485	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T1,T4,T2
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	527	case (state_q)
-2-:	533	if ((host_enable_i && trans_started))
-3-:	546	if (log_start)
-4-:	562	if (pend_restart)
-5-:	575	if ((scl_i_q && (!scl_i)))
-6-:	576	if ((sda_i_q != sda_i))
-7-:	595	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	597	if ((scl_i_q && (!scl_i)))
-9-:	598	if ((sda_i_q != sda_i))
-10-:	617	if ((scl_i_q && (!scl_i)))
-11-:	618	if ((sda_i_q != sda_i))
-12-:	624	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	636	if (fmt_flag_read_continue_i)
-14-:	637	if ((byte_index == 9'b1))
-15-:	643	if (fmt_flag_read_continue_i)
-16-:	644	if ((byte_index == 9'b1))
-17-:	648	if ((scl_i_q && (!scl_i)))
-18-:	649	if ((sda_i_q != sda_i))
-19-:	654	if (fmt_flag_read_continue_i)
-20-:	655	if ((byte_index == 9'b1))
-21-:	691	if (fmt_flag_stop_after_i)
-22-:	724	if ((tcount_q == 20'b1))
-23-:	725	if (nack_next_byte_q)
-24-:	767	if ((!scl_i))
-25-:	801	if ((tcount_q == 20'b1))
-26-:	825	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T1,T8
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T1,T8
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T34,T33
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T18
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T18
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T28
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T15,T37
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T12,T18
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T2,T3,T11
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T2,T3,T11
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T1,T8
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T4,T5,T6
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T39,T40
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T6
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T5,T6
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T5,T39,T40
NackWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	893	if ((start_det || stop_det))
-2-:	896	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	943	case (state_q)
-2-:	946	if (((!host_enable_i) && (!target_enable_i)))
-3-:	947	if (host_enable_i)
-4-:	948	if (fmt_fifo_rvalid_i)
-5-:	954	if ((tcount_q == 20'b1))
-6-:	963	if ((tcount_q == 20'b1))
-7-:	971	if ((tcount_q == 20'b1))
-8-:	980	if ((tcount_q == 20'b1))
-9-:	982	if (pend_restart)
-10-:	994	if ((tcount_q == 20'b1))
-11-:	1003	if ((tcount_q == 20'b1))
-12-:	1007	if ((bit_index == '0))
-13-:	1019	if ((tcount_q == 20'b1))
-14-:	1027	if ((tcount_q == 20'b1))
-15-:	1035	if ((tcount_q == 20'b1))
-16-:	1036	if (fmt_flag_stop_after_i)
-17-:	1049	if ((tcount_q == 20'b1))
-18-:	1057	if ((tcount_q == 20'b1))
-19-:	1066	if ((tcount_q == 20'b1))
-20-:	1069	if ((bit_index == '0))
-21-:	1083	if ((tcount_q == 20'b1))
-22-:	1092	if ((tcount_q == 20'b1))
-23-:	1101	if ((tcount_q == 20'b1))
-24-:	1103	if ((byte_index == 9'b1))
-25-:	1104	if (fmt_flag_stop_after_i)
-26-:	1123	if ((tcount_q == 20'b1))
-27-:	1131	if ((tcount_q == 20'b1))
-28-:	1141	if ((tcount_q == 20'b1))
-29-:	1143	if ((!host_enable_i))
-30-:	1156	if (fmt_flag_read_bytes_i)
-31-:	1161	if ((fmt_flag_start_before_i && (!trans_started)))
-32-:	1174	if ((!host_enable_i))
-33-:	1178	if ((fmt_fifo_depth_i == 7'b1))
-34-:	1190	if ((scl_i_q && (!scl_i)))
-35-:	1199	if (bit_ack)
-36-:	1200	if (address_match)
-37-:	1201	if (acq_fifo_full_or_last_space)
-38-:	1206	if (rw_bit_q)
-39-:	1225	if (((tcount_q == 20'b1) && (!scl_i)))
-40-:	1231	if (scl_i)
-41-:	1235	if ((!scl_i))
-42-:	1243	if ((tcount_q == 20'b1))
-43-:	1249	if ((stretch_addr && (!nack_next_byte_q)))
-44-:	1251	if (rw_bit_q)
-45-:	1253	if ((!rw_bit_q))
-46-:	1260	if (stretch_tx)
-47-:	1270	if (scl_i)
-48-:	1274	if ((!scl_i))
-49-:	1282	if ((tcount_q == 20'b1))
-50-:	1283	if (bit_ack)
-51-:	1294	if (scl_i)
-52-:	1301	if ((!scl_i))
-53-:	1303	if (host_ack)
-54-:	1319	if (bit_ack)
-55-:	1326	if ((acq_fifo_full_or_last_space || nack_next_byte_q))
-56-:	1337	if (((tcount_q == 20'b1) && (!scl_i)))
-57-:	1343	if (scl_i)
-58-:	1347	if ((!scl_i))
-59-:	1355	if ((tcount_q == 20'b1))
-60-:	1358	(stretch_rx) ? 
-61-:	1363	if (((tcount_q == 20'b1) && (!scl_i)))
-62-:	1369	if (scl_i)
-63-:	1375	if ((!scl_i))
-64-:	1383	if ((tcount_q == 20'b1))
-65-:	1395	if (((!stretch_addr) || nack_timeout))
-66-:	1401	(rw_bit_q) ? 
-67-:	1408	if ((!stretch_tx))
-68-:	1425	if ((tcount_q == 20'b1))
-69-:	1435	if (((~stretch_rx) || nack_timeout))

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T7,T1,T8
(1.Idle )->(!2)->(3)->(4)	Covered	T7,T1,T8
(1.Idle )->(!2)->(3)->(!4)	Covered	T7,T1,T8
(1.Idle )->(!2)->(!3)	Covered	T4,T5,T6
(1.SetupStart )->(5)	Covered	T1,T2,T3
(1.SetupStart )->(!5)	Covered	T1,T2,T3
(1.HoldStart )->(6)	Covered	T1,T2,T3
(1.HoldStart )->(!6)	Covered	T1,T2,T3
(1.ClockStart )->(7)	Covered	T1,T2,T3
(1.ClockStart )->(!7)	Covered	T1,T2,T3
(1.ClockLow )->(8)->(9)	Covered	T18,T19,T20
(1.ClockLow )->(8)->(!9)	Covered	T1,T2,T3
(1.ClockLow )->(!8)	Covered	T7,T1,T8
(1.ClockPulse )->(10)	Covered	T1,T2,T3
(1.ClockPulse )->(!10)	Covered	T1,T2,T3
(1.HoldBit )->(11)->(12)	Covered	T1,T2,T3
(1.HoldBit )->(11)->(!12)	Covered	T1,T2,T3
(1.HoldBit )->(!11)	Covered	T1,T2,T3
(1.ClockLowAck )->(13)	Covered	T1,T2,T3
(1.ClockLowAck )->(!13)	Covered	T1,T2,T3
(1.ClockPulseAck )->(14)	Covered	T1,T2,T3
(1.ClockPulseAck )->(!14)	Covered	T1,T2,T3
(1.HoldDevAck )->(15)->(16)	Covered	T1,T3,T52
(1.HoldDevAck )->(15)->(!16)	Covered	T1,T2,T3
(1.HoldDevAck )->(!15)	Covered	T1,T2,T3
(1.ReadClockLow )->(17)	Covered	T2,T3,T11
(1.ReadClockLow )->(!17)	Covered	T2,T3,T11
(1.ReadClockPulse )->(18)	Covered	T2,T3,T11
(1.ReadClockPulse )->(!18)	Covered	T2,T3,T11
(1.ReadHoldBit )->(19)->(20)	Covered	T2,T3,T11
(1.ReadHoldBit )->(19)->(!20)	Covered	T2,T3,T11
(1.ReadHoldBit )->(!19)	Covered	T2,T3,T11
(1.HostClockLowAck )->(21)	Covered	T2,T3,T11
(1.HostClockLowAck )->(!21)	Covered	T2,T3,T11
(1.HostClockPulseAck )->(22)	Covered	T2,T3,T11
(1.HostClockPulseAck )->(!22)	Covered	T2,T3,T11
(1.HostHoldBitAck )->(23)->(24)->(25)	Covered	T2,T3,T11
(1.HostHoldBitAck )->(23)->(24)->(!25)	Covered	T2,T12,T18
(1.HostHoldBitAck )->(23)->(!24)	Covered	T2,T3,T11
(1.HostHoldBitAck )->(!23)	Covered	T2,T3,T11
(1.ClockStop )->(26)	Covered	T1,T2,T3
(1.ClockStop )->(!26)	Covered	T1,T2,T3
(1.SetupStop )->(27)	Covered	T1,T2,T3
(1.SetupStop )->(!27)	Covered	T1,T2,T3
(1.HoldStop )->(28)->(29)	Covered	T53,T15,T16
(1.HoldStop )->(28)->(!29)	Covered	T1,T2,T3
(1.HoldStop )->(!28)	Covered	T1,T2,T3
(1.Active )->(30)	Covered	T2,T3,T11
(1.Active )->(!30)->(31)	Covered	T1,T2,T3
(1.Active )->(!30)->(!31)	Covered	T7,T1,T8
(1.PopFmtFifo )->(32)	Covered	T53,T15,T16
(1.PopFmtFifo )->(!32)->(33)	Covered	T1,T2,T3
(1.PopFmtFifo )->(!32)->(!33)	Covered	T1,T2,T3
(1.AcquireStart )->(34)	Covered	T4,T5,T6
(1.AcquireStart )->(!34)	Covered	T4,T5,T6
(1.AddrRead )->(35)->(36)->(37)->(38)	Not Covered
(1.AddrRead )->(35)->(36)->(37)->(!38)	Not Covered
(1.AddrRead )->(35)->(36)->(!37)	Covered	T4,T5,T6
(1.AddrRead )->(35)->(!36)	Covered	T22,T23,T24
(1.AddrRead )->(!35)	Covered	T4,T5,T6
(1.AddrAckWait )->(39)	Covered	T4,T5,T6
(1.AddrAckWait )->(!39)	Covered	T5,T39,T40
(1.AddrAckSetup )->(40)	Covered	T4,T5,T6
(1.AddrAckSetup )->(!40)	Covered	T4,T5,T6
(1.AddrAckPulse )->(41)	Covered	T4,T5,T6
(1.AddrAckPulse )->(!41)	Covered	T4,T5,T6
(1.AddrAckHold )->(42)->(43)	Not Covered
(1.AddrAckHold )->(42)->(!43)->(44)	Covered	T4,T5,T6
(1.AddrAckHold )->(42)->(!43)->(!44)->(45)	Covered	T4,T5,T6
(1.AddrAckHold )->(42)->(!43)->(!44)->(!45)	Not Covered
(1.AddrAckHold )->(!42)	Covered	T5,T39,T40
(1.TransmitWait )->(46)	Covered	T4,T5,T6
(1.TransmitWait )->(!46)	Covered	T4,T5,T6
(1.TransmitSetup )->(47)	Covered	T4,T5,T6
(1.TransmitSetup )->(!47)	Covered	T4,T5,T6
(1.TransmitPulse )->(48)	Covered	T4,T5,T6
(1.TransmitPulse )->(!48)	Covered	T4,T5,T6
(1.TransmitHold )->(49)->(50)	Covered	T4,T5,T6
(1.TransmitHold )->(49)->(!50)	Covered	T4,T5,T6
(1.TransmitHold )->(!49)	Covered	T5,T39,T40
(1.TransmitAck )->(51)	Covered	T4,T5,T6
(1.TransmitAck )->(!51)	Covered	T4,T5,T6
(1.TransmitAckPulse )->(52)->(53)	Covered	T4,T5,T6
(1.TransmitAckPulse )->(52)->(!53)	Covered	T4,T5,T6
(1.TransmitAckPulse )->(!52)	Covered	T4,T5,T6
(1.WaitForStop )	Covered	T4,T5,T6
(1.AcquireByte )->(54)->(55)	Not Covered
(1.AcquireByte )->(54)->(!55)	Covered	T4,T5,T6
(1.AcquireByte )->(!54)	Covered	T4,T5,T6
(1.AcquireAckWait )->(56)	Covered	T4,T5,T6
(1.AcquireAckWait )->(!56)	Covered	T5,T39,T40
(1.AcquireAckSetup )->(57)	Covered	T4,T5,T6
(1.AcquireAckSetup )->(!57)	Covered	T4,T5,T6
(1.AcquireAckPulse )->(58)	Covered	T4,T5,T6
(1.AcquireAckPulse )->(!58)	Covered	T4,T5,T6
(1.AcquireAckHold )->(59)->(60)	Covered	T41,T42,T43
(1.AcquireAckHold )->(59)->(!60)	Covered	T4,T5,T6
(1.AcquireAckHold )->(!59)	Covered	T5,T39,T40
(1.NackWait )->(61)	Not Covered
(1.NackWait )->(!61)	Not Covered
(1.NackSetup )->(62)	Not Covered
(1.NackSetup )->(!62)	Not Covered
(1.NackPulse )->(63)	Not Covered
(1.NackPulse )->(!63)	Not Covered
(1.NackHold )->(64)	Not Covered
(1.NackHold )->(!64)	Not Covered
(1.StretchAddr )->(65)->(66)	Not Covered
(1.StretchAddr )->(65)->(!66)	Not Covered
(1.StretchAddr )->(!65)	Not Covered
(1.StretchTx )->(67)	Covered	T4,T5,T6
(1.StretchTx )->(!67)	Covered	T4,T5,T6
(1.StretchTxSetup )->(68)	Covered	T4,T5,T6
(1.StretchTxSetup )->(!68)	Covered	T4,T5,T6
(1.StretchAcqFull )->(69)	Covered	T41,T42,T43
(1.StretchAcqFull )->(!69)	Covered	T41,T42,T43
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1460	if (((!target_idle) && (!target_enable_i)))
-2-:	1470	if (start_det)
-3-:	1472	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	1479	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	1488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	306079090	2805023	0	0
AcqFifoDeepEnough_A	306079090	305924833	0	0
SclInputGlitch_A	285486835	7550104	0	0
SclOutputGlitch_A	306079090	4364239	0	0
SclSdaChangeNotSimultaneous_A	306079090	305924833	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	2805023	0	0
T2	117710	0	0	0
T3	43581	0	0	0
T4	60317	421	0	0
T5	178251	53433	0	0
T6	0	471	0	0
T9	0	1415	0	0
T10	0	964	0	0
T11	12012	0	0	0
T21	1562	0	0	0
T39	0	694	0	0
T40	0	7114	0	0
T44	0	1059	0	0
T52	95850	0	0	0
T57	0	7064	0	0
T58	0	368	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285486835	7550104	0	0
T1	20602	820	0	0
T2	117710	4704	0	0
T3	43581	1534	0	0
T4	60317	4744	0	0
T5	0	7838	0	0
T8	10923	0	0	0
T11	12012	586	0	0
T21	1562	3	0	0
T52	95850	3559	0	0
T59	1462	0	0	0
T60	1657	3	0	0
T61	0	4	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	4364239	0	0
T1	20602	820	0	0
T2	117710	4704	0	0
T3	43581	1534	0	0
T4	60317	37	0	0
T5	0	253	0	0
T6	0	55	0	0
T8	10923	0	0	0
T11	12012	586	0	0
T12	0	7086	0	0
T21	1562	0	0	0
T44	0	34	0	0
T52	95850	3559	0	0
T59	1462	0	0	0
T60	1657	0	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0