Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	48	48	100.00
Total Bits 0->1	24	24	100.00
Total Bits 1->0	24	24	100.00

Ports	5	5	100.00
Port Bits	48	48	100.00
Port Bits 0->1	24	24	100.00
Port Bits 1->0	24	24	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T7,T1,T8	Yes	T7,T1,T8	INPUT
rst_ni	Yes	Yes	T30,T31,T53	Yes	T7,T1,T8	INPUT
oh_i[4:0]	Yes	Yes	*T7,*T1,*T8	Yes	T7,T1,T8	INPUT
oh_i[6:5]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[10:7]	Yes	Yes	*T7,T1,*T8	Yes	T7,T1,T8	INPUT
oh_i[12:11]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[13]	Yes	Yes	*T21,*T60,*T61	Yes	T21,T60,T61	INPUT
oh_i[14]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[21:15]	Yes	Yes	*T1,T4,*T2	Yes	T1,T4,T2	INPUT
oh_i[22]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[25:23]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
oh_i[26]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T7,T1,T8	Yes	T7,T1,T8	INPUT
err_o	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT

*Tests covering at least one bit in the range