Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_acqfifo	90.77	100.00	73.08			90.00	100.00
tb.dut.i2c_core.u_i2c_txfifo	95.19	100.00	80.77			100.00	100.00
tb.dut.i2c_core.u_i2c_fmtfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_acqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.02	100.00	73.08			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_txfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fmtfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 + Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_fmtfifo

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	LINE
95.19	100.00

tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=11,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Line Coverage for Module self-instances :

SCORE	LINE
90.77	100.00

tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T18,T19

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T1,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T15,T16
1	0	1	Covered	T7,T1,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T7,T1,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T18,T19

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	COND
95.19	80.77

tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T11,T18,T40

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Covered	T62,T63,T31
1	1	0	Not Covered
1	1	1	Covered	T4,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T4,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T18,T40
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T4,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T11,T18,T40

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T7,T1,T8

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=11,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Cond Coverage for Module self-instances :

SCORE	COND
90.77	73.08

tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T69
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T18
0	1	Covered	T7,T1,T8
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T7,T1,T8
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1224316360	409951037	0	0
DepthKnown_A	1224316360	1223699332	0	0
RvalidKnown_A	1224316360	1223699332	0	0
WreadyKnown_A	1224316360	1223699332	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1224316360	409951037	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224316360	409951037	0	0
T1	20602	19101	0	0
T2	470840	118555	0	0
T3	174324	40202	0	0
T4	180951	24595	0	0
T5	534753	176296	0	0
T6	112896	52084	0	0
T7	13301	11480	0	0
T8	10923	9067	0	0
T9	0	81037	0	0
T10	0	82884	0	0
T11	48048	21330	0	0
T12	0	239171	0	0
T18	0	189120	0	0
T19	0	31964	0	0
T21	6248	0	0	0
T39	0	29397	0	0
T40	0	323078	0	0
T44	0	40615	0	0
T52	287550	92686	0	0
T57	0	165985	0	0
T58	0	72785	0	0
T59	5848	0	0	0
T60	6628	0	0	0
T61	3210	0	0	0
T70	0	60427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224316360	1223699332	0	0
T1	82408	82064	0	0
T2	470840	470460	0	0
T3	174324	173988	0	0
T4	241268	240952	0	0
T7	53204	52804	0	0
T8	43692	43292	0	0
T11	48048	47676	0	0
T21	6248	5932	0	0
T59	5848	5472	0	0
T60	6628	6400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224316360	1223699332	0	0
T1	82408	82064	0	0
T2	470840	470460	0	0
T3	174324	173988	0	0
T4	241268	240952	0	0
T7	53204	52804	0	0
T8	43692	43292	0	0
T11	48048	47676	0	0
T21	6248	5932	0	0
T59	5848	5472	0	0
T60	6628	6400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224316360	1223699332	0	0
T1	82408	82064	0	0
T2	470840	470460	0	0
T3	174324	173988	0	0
T4	241268	240952	0	0
T7	53204	52804	0	0
T8	43692	43292	0	0
T11	48048	47676	0	0
T21	6248	5932	0	0
T59	5848	5472	0	0
T60	6628	6400	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224316360	409951037	0	0
T1	20602	19101	0	0
T2	470840	118555	0	0
T3	174324	40202	0	0
T4	180951	24595	0	0
T5	534753	176296	0	0
T6	112896	52084	0	0
T7	13301	11480	0	0
T8	10923	9067	0	0
T9	0	81037	0	0
T10	0	82884	0	0
T11	48048	21330	0	0
T12	0	239171	0	0
T18	0	189120	0	0
T19	0	31964	0	0
T21	6248	0	0	0
T39	0	29397	0	0
T40	0	323078	0	0
T44	0	40615	0	0
T52	287550	92686	0	0
T57	0	165985	0	0
T58	0	72785	0	0
T59	5848	0	0	0
T60	6628	0	0	0
T61	3210	0	0	0
T70	0	60427	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T69
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T7,T1,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T7,T1,T8
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T1,T8

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306079090	102548843	0	0
DepthKnown_A	306079090	305924833	0	0
RvalidKnown_A	306079090	305924833	0	0
WreadyKnown_A	306079090	305924833	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	306079090	102548843	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	102548843	0	0
T2	117710	0	0	0
T3	43581	0	0	0
T4	60317	24595	0	0
T5	178251	176296	0	0
T6	0	52084	0	0
T9	0	81037	0	0
T10	0	82884	0	0
T11	12012	0	0	0
T21	1562	0	0	0
T39	0	29397	0	0
T40	0	323078	0	0
T44	0	40615	0	0
T52	95850	0	0	0
T57	0	165985	0	0
T58	0	72785	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	102548843	0	0
T2	117710	0	0	0
T3	43581	0	0	0
T4	60317	24595	0	0
T5	178251	176296	0	0
T6	0	52084	0	0
T9	0	81037	0	0
T10	0	82884	0	0
T11	12012	0	0	0
T21	1562	0	0	0
T39	0	29397	0	0
T40	0	323078	0	0
T44	0	40615	0	0
T52	95850	0	0	0
T57	0	165985	0	0
T58	0	72785	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T40,T57,T64

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T57,T64
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T40,T57,T64

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T1,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T57,T64
0	1	Covered	T7,T1,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T7,T1,T8
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T1,T8

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306079090	111324087	0	0
DepthKnown_A	306079090	305924833	0	0
RvalidKnown_A	306079090	305924833	0	0
WreadyKnown_A	306079090	305924833	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	306079090	111324087	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	111324087	0	0
T2	117710	0	0	0
T3	43581	0	0	0
T4	60317	30923	0	0
T5	178251	175704	0	0
T6	0	50844	0	0
T9	0	60976	0	0
T10	0	48869	0	0
T11	12012	0	0	0
T21	1562	0	0	0
T39	0	26015	0	0
T40	0	490467	0	0
T44	0	36964	0	0
T52	95850	0	0	0
T57	0	247376	0	0
T58	0	62168	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	111324087	0	0
T2	117710	0	0	0
T3	43581	0	0	0
T4	60317	30923	0	0
T5	178251	175704	0	0
T6	0	50844	0	0
T9	0	60976	0	0
T10	0	48869	0	0
T11	12012	0	0	0
T21	1562	0	0	0
T39	0	26015	0	0
T40	0	490467	0	0
T44	0	36964	0	0
T52	95850	0	0	0
T57	0	247376	0	0
T58	0	62168	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T18,T19

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T1,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T15,T16
1	0	1	Covered	T7,T1,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T7,T1,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T1,T18,T19

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T19
0	1	Covered	T7,T1,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T7,T1,T8
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T7,T1,T8

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306079090	157209579	0	0
DepthKnown_A	306079090	305924833	0	0
RvalidKnown_A	306079090	305924833	0	0
WreadyKnown_A	306079090	305924833	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	306079090	157209579	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	157209579	0	0
T1	20602	19101	0	0
T2	117710	113977	0	0
T3	43581	38214	0	0
T4	60317	0	0	0
T7	13301	11480	0	0
T8	10923	9067	0	0
T11	12012	10848	0	0
T12	0	230428	0	0
T18	0	163975	0	0
T21	1562	0	0	0
T52	0	86670	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T70	0	60427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	157209579	0	0
T1	20602	19101	0	0
T2	117710	113977	0	0
T3	43581	38214	0	0
T4	60317	0	0	0
T7	13301	11480	0	0
T8	10923	9067	0	0
T11	12012	10848	0	0
T12	0	230428	0	0
T18	0	163975	0	0
T21	1562	0	0	0
T52	0	86670	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T70	0	60427	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T11,T18,T19

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T52
1	Covered	T7,T1,T8

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T52
1	Covered	T7,T1,T8

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T1,T8
1	0	1	Covered	T62,T63,T31
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T11
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T52

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T18,T19
1	0	Covered	T7,T1,T8
1	1	Covered	T7,T1,T8

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T8
1	0	Not Covered
1	1	Covered	T2,T3,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T11,T18,T19

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T7,T1,T8

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T7,T1,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T18,T19
0	1	Covered	T7,T1,T8
0	0	Covered	T2,T3,T52

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T8
0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T1,T8
0	1	Covered	T7,T1,T8
0	0	Covered	T7,T1,T8

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T7,T1,T8

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306079090	38868528	0	0
DepthKnown_A	306079090	305924833	0	0
RvalidKnown_A	306079090	305924833	0	0
WreadyKnown_A	306079090	305924833	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	306079090	38868528	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	38868528	0	0
T2	117710	4578	0	0
T3	43581	1988	0	0
T5	178251	0	0	0
T6	112896	0	0	0
T11	12012	10482	0	0
T12	0	8743	0	0
T18	0	25145	0	0
T19	0	31964	0	0
T20	0	22	0	0
T21	1562	0	0	0
T29	0	4029	0	0
T52	95850	6016	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0
T62	0	207886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	305924833	0	0
T1	20602	20516	0	0
T2	117710	117615	0	0
T3	43581	43497	0	0
T4	60317	60238	0	0
T7	13301	13201	0	0
T8	10923	10823	0	0
T11	12012	11919	0	0
T21	1562	1483	0	0
T59	1462	1368	0	0
T60	1657	1600	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	306079090	38868528	0	0
T2	117710	4578	0	0
T3	43581	1988	0	0
T5	178251	0	0	0
T6	112896	0	0	0
T11	12012	10482	0	0
T12	0	8743	0	0
T18	0	25145	0	0
T19	0	31964	0	0
T20	0	22	0	0
T21	1562	0	0	0
T29	0	4029	0	0
T52	95850	6016	0	0
T59	1462	0	0	0
T60	1657	0	0	0
T61	1070	0	0	0
T62	0	207886	0	0