Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	306718622	8521	0	0
ctrl_rd_A	306718622	1058	0	0
host_fifo_config_rd_A	306718622	3152	0	0
host_timeout_ctrl_rd_A	306718622	891	0	0
intr_enable_rd_A	306718622	2745	0	0
ovrd_rd_A	306718622	1748	0	0
target_fifo_config_rd_A	306718622	1092	0	0
target_id_rd_A	306718622	927	0	0
target_timeout_ctrl_rd_A	306718622	1008	0	0
timeout_ctrl_rd_A	306718622	964	0	0
timing0_rd_A	306718622	1019	0	0
timing1_rd_A	306718622	945	0	0
timing2_rd_A	306718622	879	0	0
timing3_rd_A	306718622	885	0	0
timing4_rd_A	306718622	982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	8521	0	0
T67	5855	1	0	0
T71	11068	404	0	0
T72	2973	13	0	0
T73	2024	38	0	0
T74	3847	488	0	0
T75	12298	620	0	0
T76	5879	2	0	0
T80	7781	3	0	0
T83	2046	68	0	0
T111	2061	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	1058	0	0
T72	2973	26	0	0
T75	12298	65	0	0
T82	11603	38	0	0
T86	6497	63	0	0
T114	1781	4	0	0
T115	5295	81	0	0
T117	8982	76	0	0
T135	1936	3	0	0
T137	2755	28	0	0
T138	2058	10	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	3152	0	0
T13	192727	245	0	0
T16	148932	0	0	0
T17	161769	0	0	0
T36	0	76	0	0
T139	0	55	0	0
T140	0	452	0	0
T141	0	124	0	0
T142	0	310	0	0
T143	0	86	0	0
T144	0	90	0	0
T145	0	133	0	0
T146	0	149	0	0
T147	150602	0	0	0
T148	164973	0	0	0
T149	62080	0	0	0
T150	257119	0	0	0
T151	107206	0	0	0
T152	2051	0	0	0
T153	1304	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	891	0	0
T72	2973	11	0	0
T75	12298	29	0	0
T82	11603	47	0	0
T86	6497	29	0	0
T115	5295	97	0	0
T117	8982	132	0	0
T118	1416	9	0	0
T135	1936	3	0	0
T137	2755	3	0	0
T138	2058	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	2745	0	0
T13	0	86	0	0
T26	40670	0	0	0
T27	717987	0	0	0
T31	867395	17	0	0
T36	0	12	0	0
T48	3766	0	0	0
T53	182401	0	0	0
T140	0	13	0	0
T142	0	8	0	0
T144	0	11	0	0
T154	0	22	0	0
T155	0	26	0	0
T156	0	19	0	0
T157	0	15	0	0
T158	1924	0	0	0
T159	129590	0	0	0
T160	21306	0	0	0
T161	1078	0	0	0
T162	776577	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	1748	0	0
T5	178251	0	0	0
T6	112896	0	0	0
T12	231681	0	0	0
T18	166360	0	0	0
T39	57198	0	0	0
T44	77345	0	0	0
T52	95850	0	0	0
T60	1657	51	0	0
T61	1070	0	0	0
T70	61871	0	0	0
T161	0	33	0	0
T163	0	82	0	0
T164	0	23	0	0
T165	0	54	0	0
T166	0	42	0	0
T167	0	56	0	0
T168	0	74	0	0
T169	0	77	0	0
T170	0	59	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	1092	0	0
T72	2973	32	0	0
T75	12298	28	0	0
T82	11603	48	0	0
T86	6497	59	0	0
T114	1781	3	0	0
T115	5295	84	0	0
T117	8982	127	0	0
T135	1936	7	0	0
T137	2755	1	0	0
T138	2058	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	927	0	0
T72	2973	23	0	0
T75	12298	13	0	0
T82	11603	28	0	0
T86	6497	64	0	0
T114	1781	10	0	0
T115	5295	77	0	0
T117	8982	75	0	0
T135	1936	7	0	0
T137	2755	19	0	0
T138	2058	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	1008	0	0
T72	2973	19	0	0
T75	12298	7	0	0
T82	11603	15	0	0
T86	6497	35	0	0
T114	1781	2	0	0
T115	5295	114	0	0
T117	8982	108	0	0
T135	1936	2	0	0
T137	2755	32	0	0
T138	2058	19	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	964	0	0
T72	2973	9	0	0
T75	12298	4	0	0
T82	11603	17	0	0
T86	6497	29	0	0
T114	1781	5	0	0
T115	5295	95	0	0
T117	8982	121	0	0
T135	1936	5	0	0
T137	2755	34	0	0
T138	2058	9	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	1019	0	0
T72	2973	17	0	0
T75	12298	50	0	0
T82	11603	16	0	0
T86	6497	34	0	0
T114	1781	10	0	0
T115	5295	94	0	0
T117	8982	105	0	0
T135	1936	6	0	0
T137	2755	27	0	0
T138	2058	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	945	0	0
T72	2973	9	0	0
T75	12298	18	0	0
T82	11603	24	0	0
T86	6497	73	0	0
T114	1781	1	0	0
T115	5295	88	0	0
T117	8982	112	0	0
T135	1936	1	0	0
T137	2755	29	0	0
T138	2058	5	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	879	0	0
T72	2973	23	0	0
T75	12298	20	0	0
T82	11603	29	0	0
T86	6497	28	0	0
T114	1781	4	0	0
T115	5295	101	0	0
T117	8982	90	0	0
T135	1936	3	0	0
T137	2755	29	0	0
T138	2058	14	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	885	0	0
T72	2973	10	0	0
T75	12298	1	0	0
T82	11603	15	0	0
T86	6497	17	0	0
T114	1781	14	0	0
T115	5295	78	0	0
T117	8982	102	0	0
T135	1936	10	0	0
T137	2755	4	0	0
T138	2058	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306718622	982	0	0
T72	2973	20	0	0
T75	12298	25	0	0
T82	11603	25	0	0
T86	6497	25	0	0
T114	1781	1	0	0
T115	5295	117	0	0
T117	8982	104	0	0
T135	1936	9	0	0
T137	2755	18	0	0
T138	2058	12	0	0