Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1903300	1			T1	3		T2	4576		T3	2
all_values[1]	1903300	1			T1	3		T2	4576		T3	2
all_values[2]	1903300	1			T1	3		T2	4576		T3	2
all_values[3]	1903300	1			T1	3		T2	4576		T3	2
all_values[4]	1903300	1			T1	3		T2	4576		T3	2
all_values[5]	1903300	1			T1	3		T2	4576		T3	2
all_values[6]	1903300	1			T1	3		T2	4576		T3	2
all_values[7]	1903300	1			T1	3		T2	4576		T3	2
all_values[8]	1903300	1			T1	3		T2	4576		T3	2
all_values[9]	1903300	1			T1	3		T2	4576		T3	2
all_values[10]	1903300	1			T1	3		T2	4576		T3	2
all_values[11]	1903300	1			T1	3		T2	4576		T3	2
all_values[12]	1903300	1			T1	3		T2	4576		T3	2
all_values[13]	1903300	1			T1	3		T2	4576		T3	2
all_values[14]	1903300	1			T1	3		T2	4576		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24585628

1

T1

37

T2

57887

T3

27

auto[1]

3963872

1

T1

8

T2

10753

T3

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26045038

1

T1

45

T2

68640

T3

30

auto[1]

2504462

1

T50

64

T64

165008

T65

125078

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3] , all_values[4]]	[auto[1]]	[auto[0]]	--	--	3
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	301857	1			T1	1		T2	50		T6	3
all_values[0]	auto[0]	auto[1]	7120	1			T50	3		T64	38		T65	369
all_values[0]	auto[1]	auto[0]	1423959	1			T1	2		T2	4526		T3	2
all_values[0]	auto[1]	auto[1]	170364	1			T50	1		T64	11748		T65	9251
all_values[1]	auto[0]	auto[0]	1736219	1			T1	3		T2	4576		T3	2
all_values[1]	auto[0]	auto[1]	166068	1			T50	5		T64	11774		T65	9619
all_values[1]	auto[1]	auto[0]	838	1			T210	17		T211	23		T50	47
all_values[1]	auto[1]	auto[1]	175	1			T50	1		T64	6		T65	1
all_values[2]	auto[0]	auto[0]	1725803	1			T1	3		T2	4576		T3	2
all_values[2]	auto[0]	auto[1]	177346	1			T64	11780		T65	9620		T66	19
all_values[2]	auto[1]	auto[1]	151	1			T64	6		T65	1		T66	1
all_values[3]	auto[0]	auto[0]	1725812	1			T1	3		T2	4576		T3	2
all_values[3]	auto[0]	auto[1]	177297	1			T50	4		T64	11776		T65	9618
all_values[3]	auto[1]	auto[1]	191	1			T50	1		T64	10		T65	4
all_values[4]	auto[0]	auto[0]	1725819	1			T1	3		T2	4576		T3	2
all_values[4]	auto[0]	auto[1]	177312	1			T64	11780		T65	9619		T66	17
all_values[4]	auto[1]	auto[1]	169	1			T64	6		T65	3		T66	4
all_values[5]	auto[0]	auto[0]	1725313	1			T1	3		T2	4576		T3	2
all_values[5]	auto[0]	auto[1]	177290	1			T50	3		T64	11773		T65	9618
all_values[5]	auto[1]	auto[0]	509	1			T11	509		-	-		-	-
all_values[5]	auto[1]	auto[1]	188	1			T50	2		T64	13		T65	4
all_values[6]	auto[0]	auto[0]	1758172	1			T1	2		T2	4555		T3	2
all_values[6]	auto[0]	auto[1]	140452	1			T50	3		T64	16		T65	9565
all_values[6]	auto[1]	auto[0]	3597	1			T1	1		T2	21		T6	1
all_values[6]	auto[1]	auto[1]	1079	1			T50	3		T64	3		T65	57
all_values[7]	auto[0]	auto[0]	1342139	1			T1	2		T2	3444		T3	2
all_values[7]	auto[0]	auto[1]	137375	1			T50	5		T64	6167		T66	18
all_values[7]	auto[1]	auto[0]	393279	1			T1	1		T2	1132		T10	1
all_values[7]	auto[1]	auto[1]	30507	1			T50	1		T64	5618		T66	3
all_values[8]	auto[0]	auto[0]	1704711	1			T1	2		T2	4103		T3	2
all_values[8]	auto[0]	auto[1]	164518	1			T50	2		T64	11745		T66	18
all_values[8]	auto[1]	auto[0]	30711	1			T1	1		T2	473		T10	1
all_values[8]	auto[1]	auto[1]	3360	1			T50	2		T64	36		T66	2
all_values[9]	auto[0]	auto[0]	1734574	1			T1	2		T2	4546		T3	2
all_values[9]	auto[0]	auto[1]	165793	1			T64	11771		T65	9554		T66	16
all_values[9]	auto[1]	auto[0]	2460	1			T1	1		T2	30		T4	1
all_values[9]	auto[1]	auto[1]	473	1			T64	14		T65	68		T66	5
all_values[10]	auto[0]	auto[0]	1794834	1			T1	3		T2	4576		T3	2
all_values[10]	auto[0]	auto[1]	108311	1			T50	4		T64	11780		T65	9620
all_values[10]	auto[1]	auto[1]	155	1			T50	1		T64	5		T65	2
all_values[11]	auto[0]	auto[0]	1800	1			T1	1		T2	5		T3	1
all_values[11]	auto[0]	auto[1]	333	1			T50	5		T64	39		T65	14
all_values[11]	auto[1]	auto[0]	1735252	1			T1	2		T2	4571		T3	1
all_values[11]	auto[1]	auto[1]	165915	1			T50	1		T64	11747		T65	9608
all_values[12]	auto[0]	auto[0]	1725813	1			T1	3		T2	4576		T3	2
all_values[12]	auto[0]	auto[1]	177340	1			T50	5		T64	11777		T65	9621
all_values[12]	auto[1]	auto[1]	147	1			T50	1		T64	9		T65	1
all_values[13]	auto[0]	auto[0]	1725773	1			T1	3		T2	4576		T3	2
all_values[13]	auto[0]	auto[1]	177325	1			T50	6		T64	11782		T65	9618
all_values[13]	auto[1]	auto[0]	12	1			T23	1		T212	1		T206	1
all_values[13]	auto[1]	auto[1]	190	1			T64	4		T65	2		T66	2
all_values[14]	auto[0]	auto[0]	1725782	1			T1	3		T2	4576		T3	2
all_values[14]	auto[0]	auto[1]	177327	1			T50	5		T64	11775		T65	9621
all_values[14]	auto[1]	auto[1]	191	1			T64	10		T66	1		T102	8