| | | | | | | |
|
i2c_fsm |
82.81 |
93.66 |
86.44 |
|
45.81 |
88.12 |
100.00 |
|
i2c_core |
89.78 |
96.77 |
71.43 |
|
|
90.91 |
100.00 |
|
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb |
94.60 |
87.50 |
96.30 |
|
|
100.00 |
|
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) |
50.00 |
50.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 ) |
83.33 |
100.00 |
66.67 |
|
|
|
|
|
prim_fifo_sync |
94.87 |
100.00 |
79.49 |
|
|
100.00 |
100.00 |
|
prim_fifo_sync |
100.00 |
|
|
|
|
100.00 |
100.00 |
|
prim_fifo_sync ( parameter Width=11,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 ) |
86.54 |
100.00 |
73.08 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 ) |
80.77 |
|
80.77 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 + Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 ) |
84.62 |
|
84.62 |
|
|
|
|
|
prim_subreg |
95.83 |
100.00 |
94.64 |
|
|
92.86 |
|
|
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=16,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=32,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=31,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 ) |
80.95 |
100.00 |
57.14 |
|
|
85.71 |
|
|
tlul_adapter_reg |
98.91 |
100.00 |
95.65 |
|
|
100.00 |
100.00 |
|
i2c_reg_top |
99.91 |
100.00 |
99.66 |
|
|
100.00 |
100.00 |
|
prim_fifo_sync_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
prim_fifo_sync_cnt |
100.00 |
|
|
|
|
100.00 |
|
|
prim_fifo_sync_cnt ( parameter Depth=268,Width=10,Secure=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_fifo_sync_cnt ( parameter Depth=64,Width=7,Secure=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
|
i2c |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_intr_hw |
100.00 |
|
|
|
|
|
100.00 |
|
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
|
i2c_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|