Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_stretch_cg

Group : i2c_env_pkg::i2c_scl_stretch_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group i2c_env_pkg::i2c_scl_stretch_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_fifo_size	2	0	2	100.00	100	1	1	0
cp_host_mode_stretch	1	0	1	100.00	100	1	1	0
cp_target_scl_stretch_addr_write	1	0	1	100.00	100	1	1	0
cp_tx_fifo_size	2	0	2	100.00	100	1	1	0

Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_target_scl_stretch_read	4	0	4	100.00	100	1	1	0

Summary for Variable cp_acq_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_acq_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

43067806

1

T3

42025

T22

650248

T55

211080

empty

47153518

1

T1

116410

T2

31203

T3

298

---

Summary for Variable cp_host_mode_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

stretch

29848998

1

T1

116410

T2

31203

T10

139368

---

Summary for Variable cp_target_scl_stretch_addr_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_target_scl_stretch_addr_write

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
addr_write_byte_stretch	1592	1			T41	1001		T34	591

---

Summary for Variable cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_tx_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

42739074

1

T3

41871

T4

147

T22

648695

empty

47482250

1

T1

116410

T2

31203

T3

452

---

Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins

cp_acq_fifo_size

cp_tx_fifo_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

not_empty

11853

1

T3

1

T4

147

T22

63

empty

empty

639315

1

T3

297

T4

1634

T22

1200

User Defined Cross Bins for cp_target_scl_stretch_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_byte_stretch

313969

1

T3

155

T22

1616

T55

2615

scl_stretch_read_request

43041190

1

T3

42025

T22

650248

T55

211080