Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1903300	1			T1	3		T2	4576		T3	2
all_pins[1]	1903300	1			T1	3		T2	4576		T3	2
all_pins[2]	1903300	1			T1	3		T2	4576		T3	2
all_pins[3]	1903300	1			T1	3		T2	4576		T3	2
all_pins[4]	1903300	1			T1	3		T2	4576		T3	2
all_pins[5]	1903300	1			T1	3		T2	4576		T3	2
all_pins[6]	1903300	1			T1	3		T2	4576		T3	2
all_pins[7]	1903300	1			T1	3		T2	4576		T3	2
all_pins[8]	1903300	1			T1	3		T2	4576		T3	2
all_pins[9]	1903300	1			T1	3		T2	4576		T3	2
all_pins[10]	1903300	1			T1	3		T2	4576		T3	2
all_pins[11]	1903300	1			T1	3		T2	4576		T3	2
all_pins[12]	1903300	1			T1	3		T2	4576		T3	2
all_pins[13]	1903300	1			T1	3		T2	4576		T3	2
all_pins[14]	1903300	1			T1	3		T2	4576		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24564747	1			T1	37		T2	57781		T3	27
values[0x1]	3984753	1			T1	8		T2	10859		T3	3
transitions[0x0=>0x1]	3967060	1			T1	5		T2	10827		T3	3
transitions[0x1=>0x0]	3966249	1			T1	4		T2	10826		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	309057	1			T1	1		T2	50		T6	3
all_pins[0]	values[0x1]	1594243	1			T1	2		T2	4526		T3	2
all_pins[0]	transitions[0x0=>0x1]	1593218	1			T1	2		T2	4526		T3	2
all_pins[0]	transitions[0x1=>0x0]	99	1			T50	45		T64	3		T102	2
all_pins[1]	values[0x0]	1902176	1			T1	3		T2	4576		T3	2
all_pins[1]	values[0x1]	1124	1			T210	26		T211	27		T50	52
all_pins[1]	transitions[0x0=>0x1]	1100	1			T210	26		T211	27		T50	52
all_pins[1]	transitions[0x1=>0x0]	47	1			T64	1		T102	5		T183	2
all_pins[2]	values[0x0]	1903229	1			T1	3		T2	4576		T3	2
all_pins[2]	values[0x1]	71	1			T64	2		T102	5		T183	2
all_pins[2]	transitions[0x0=>0x1]	54	1			T64	1		T102	4		T183	2
all_pins[2]	transitions[0x1=>0x0]	75	1			T50	1		T64	4		T65	3
all_pins[3]	values[0x0]	1903208	1			T1	3		T2	4576		T3	2
all_pins[3]	values[0x1]	92	1			T50	1		T64	5		T65	3
all_pins[3]	transitions[0x0=>0x1]	64	1			T50	1		T64	4		T65	3
all_pins[3]	transitions[0x1=>0x0]	52	1			T64	4		T66	1		T102	5
all_pins[4]	values[0x0]	1903220	1			T1	3		T2	4576		T3	2
all_pins[4]	values[0x1]	80	1			T64	5		T66	2		T102	5
all_pins[4]	transitions[0x0=>0x1]	55	1			T64	3		T66	2		T102	3
all_pins[4]	transitions[0x1=>0x0]	637	1			T11	561		T64	5		T65	3
all_pins[5]	values[0x0]	1902638	1			T1	3		T2	4576		T3	2
all_pins[5]	values[0x1]	662	1			T11	561		T64	7		T65	3
all_pins[5]	transitions[0x0=>0x1]	638	1			T11	561		T64	7		T65	2
all_pins[5]	transitions[0x1=>0x0]	5024	1			T1	1		T2	22		T6	1
all_pins[6]	values[0x0]	1898252	1			T1	2		T2	4554		T3	2
all_pins[6]	values[0x1]	5048	1			T1	1		T2	22		T6	1
all_pins[6]	transitions[0x0=>0x1]	3356	1			T2	18		T6	1		T67	1
all_pins[6]	transitions[0x1=>0x0]	439072	1			T2	1211		T72	1881		T73	1652
all_pins[7]	values[0x0]	1462536	1			T1	2		T2	3361		T3	2
all_pins[7]	values[0x1]	440764	1			T1	1		T2	1215		T10	1
all_pins[7]	transitions[0x0=>0x1]	426370	1			T2	1187		T72	1823		T73	1460
all_pins[7]	transitions[0x1=>0x0]	23741	1			T2	467		T67	1		T71	1
all_pins[8]	values[0x0]	1865165	1			T1	2		T2	4081		T3	2
all_pins[8]	values[0x1]	38135	1			T1	1		T2	495		T10	1
all_pins[8]	transitions[0x0=>0x1]	37818	1			T2	495		T72	393		T73	289
all_pins[8]	transitions[0x1=>0x0]	2765	1			T2	30		T4	1		T5	1
all_pins[9]	values[0x0]	1900218	1			T1	2		T2	4546		T3	2
all_pins[9]	values[0x1]	3082	1			T1	1		T2	30		T4	1
all_pins[9]	transitions[0x0=>0x1]	3058	1			T1	1		T2	30		T4	1
all_pins[9]	transitions[0x1=>0x0]	61	1			T50	1		T64	1		T66	1
all_pins[10]	values[0x0]	1903215	1			T1	3		T2	4576		T3	2
all_pins[10]	values[0x1]	85	1			T50	1		T64	1		T65	1
all_pins[10]	transitions[0x0=>0x1]	64	1			T50	1		T64	1		T66	2
all_pins[10]	transitions[0x1=>0x0]	1901069	1			T1	2		T2	4571		T3	1
all_pins[11]	values[0x0]	2210	1			T1	1		T2	5		T3	1
all_pins[11]	values[0x1]	1901090	1			T1	2		T2	4571		T3	1
all_pins[11]	transitions[0x0=>0x1]	1901070	1			T1	2		T2	4571		T3	1
all_pins[11]	transitions[0x1=>0x0]	56	1			T64	2		T66	2		T102	2
all_pins[12]	values[0x0]	1903224	1			T1	3		T2	4576		T3	2
all_pins[12]	values[0x1]	76	1			T50	1		T64	3		T65	1
all_pins[12]	transitions[0x0=>0x1]	57	1			T50	1		T64	3		T65	1
all_pins[12]	transitions[0x1=>0x0]	87	1			T23	1		T64	3		T65	2
all_pins[13]	values[0x0]	1903194	1			T1	3		T2	4576		T3	2
all_pins[13]	values[0x1]	106	1			T23	1		T64	3		T65	2
all_pins[13]	transitions[0x0=>0x1]	81	1			T23	1		T64	3		T65	2
all_pins[13]	transitions[0x1=>0x0]	70	1			T64	7		T102	3		T196	1
all_pins[14]	values[0x0]	1903205	1			T1	3		T2	4576		T3	2
all_pins[14]	values[0x1]	95	1			T64	7		T102	5		T196	1
all_pins[14]	transitions[0x0=>0x1]	57	1			T64	5		T102	2		T225	2
all_pins[14]	transitions[0x1=>0x0]	1593394	1			T1	1		T2	4525		T3	1