Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	377	1			T50	4		T64	15		T65	4
all_values[1]	377	1			T50	4		T64	15		T65	4
all_values[2]	377	1			T50	4		T64	15		T65	4
all_values[3]	377	1			T50	4		T64	15		T65	4
all_values[4]	377	1			T50	4		T64	15		T65	4
all_values[5]	377	1			T50	4		T64	15		T65	4
all_values[6]	377	1			T50	4		T64	15		T65	4
all_values[7]	377	1			T50	4		T64	15		T65	4
all_values[8]	377	1			T50	4		T64	15		T65	4
all_values[9]	377	1			T50	4		T64	15		T65	4
all_values[10]	377	1			T50	4		T64	15		T65	4
all_values[11]	377	1			T50	4		T64	15		T65	4
all_values[12]	377	1			T50	4		T64	15		T65	4
all_values[13]	377	1			T50	4		T64	15		T65	4
all_values[14]	377	1			T50	4		T64	15		T65	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3068

1

T50

34

T64

94

T65

22

auto[1]

2587

1

T50

26

T64

131

T65

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

976

1

T50

20

T64

23

T65

16

auto[1]

4679

1

T50

40

T64

202

T65

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3319

1

T50

43

T64

131

T65

42

auto[1]

2336

1

T50

17

T64

94

T65

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	38	1			T50	2		T65	2		T66	2
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T64	2		T102	9		T225	1
all_values[0]	auto[0]	auto[1]	auto[0]	29	1			T66	2		T226	4		T227	1
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T50	1		T64	7		T65	1
all_values[0]	auto[1]	auto[0]	auto[1]	88	1			T50	1		T64	1		T102	5
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T64	5		T65	1		T102	4
all_values[1]	auto[0]	auto[0]	auto[0]	39	1			T65	2		T66	1		T102	2
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T50	1		T64	1		T66	1
all_values[1]	auto[0]	auto[1]	auto[0]	27	1			T64	5		T196	1		T198	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T50	2		T64	3		T65	1
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T50	1		T64	1		T66	1
all_values[1]	auto[1]	auto[1]	auto[1]	60	1			T64	5		T65	1		T102	5
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T50	4		T66	1		T102	2
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T64	6		T65	2		T66	1
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T65	1		T228	1		T226	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T64	3		T66	1		T102	3
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T64	4		T66	1		T102	6
all_values[2]	auto[1]	auto[1]	auto[1]	69	1			T64	2		T65	1		T102	5
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T50	1		T225	1		T229	2
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T64	2		T66	1		T102	7
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T66	1		T196	1		T198	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T50	2		T64	6		T65	1
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T64	5		T65	2		T102	3
all_values[3]	auto[1]	auto[1]	auto[1]	59	1			T50	1		T64	2		T65	1
all_values[4]	auto[0]	auto[0]	auto[0]	38	1			T50	1		T196	2		T225	1
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T64	3		T65	2		T66	1
all_values[4]	auto[0]	auto[1]	auto[0]	37	1			T50	3		T196	2		T198	2
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T64	5		T66	1		T102	3
all_values[4]	auto[1]	auto[0]	auto[1]	88	1			T64	1		T65	2		T102	8
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T64	6		T66	2		T102	3
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T50	1		T102	1		T155	1
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T50	1		T64	2		T102	7
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T66	4		T226	4		T227	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T64	5		T65	3		T102	4
all_values[5]	auto[1]	auto[0]	auto[1]	76	1			T64	3		T102	6		T183	3
all_values[5]	auto[1]	auto[1]	auto[1]	79	1			T50	2		T64	5		T65	1
all_values[6]	auto[0]	auto[0]	auto[0]	54	1			T64	4		T102	7		T183	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T50	1		T64	1		T102	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T64	6		T102	1		T230	4
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T64	1		T65	3		T66	2
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T50	1		T64	1		T66	1
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T50	2		T64	2		T65	1
all_values[7]	auto[0]	auto[0]	auto[0]	36	1			T65	2		T183	2		T225	1
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T50	1		T64	2		T66	1
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T64	1		T65	2		T183	1
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T50	1		T64	4		T102	10
all_values[7]	auto[1]	auto[0]	auto[1]	90	1			T50	1		T64	2		T66	2
all_values[7]	auto[1]	auto[1]	auto[1]	67	1			T50	1		T64	6		T66	1
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T50	1		T64	1		T65	2
all_values[8]	auto[0]	auto[0]	auto[1]	69	1			T50	1		T64	2		T102	4
all_values[8]	auto[0]	auto[1]	auto[0]	30	1			T50	1		T64	3		T65	2
all_values[8]	auto[0]	auto[1]	auto[1]	75	1			T64	2		T66	1		T102	5
all_values[8]	auto[1]	auto[0]	auto[1]	91	1			T102	8		T183	2		T225	3
all_values[8]	auto[1]	auto[1]	auto[1]	76	1			T50	1		T64	7		T66	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T50	3		T227	1		T156	2
all_values[9]	auto[0]	auto[0]	auto[1]	86	1			T64	6		T65	2		T66	1
all_values[9]	auto[0]	auto[1]	auto[0]	14	1			T50	1		T64	1		T196	1
all_values[9]	auto[0]	auto[1]	auto[1]	80	1			T64	2		T65	1		T66	1
all_values[9]	auto[1]	auto[0]	auto[1]	103	1			T64	2		T102	7		T183	2
all_values[9]	auto[1]	auto[1]	auto[1]	62	1			T64	4		T65	1		T66	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T50	1		T183	1		T225	1
all_values[10]	auto[0]	auto[0]	auto[1]	85	1			T50	1		T64	6		T65	1
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T64	1		T225	3		T198	5
all_values[10]	auto[0]	auto[1]	auto[1]	71	1			T50	1		T64	3		T65	1
all_values[10]	auto[1]	auto[0]	auto[1]	75	1			T64	4		T65	1		T102	4
all_values[10]	auto[1]	auto[1]	auto[1]	80	1			T50	1		T64	1		T65	1
all_values[11]	auto[0]	auto[0]	auto[0]	34	1			T225	1		T230	1		T155	1
all_values[11]	auto[0]	auto[0]	auto[1]	77	1			T64	6		T65	1		T66	1
all_values[11]	auto[0]	auto[1]	auto[0]	30	1			T102	2		T198	5		T228	1
all_values[11]	auto[0]	auto[1]	auto[1]	83	1			T50	3		T64	4		T65	1
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T50	1		T64	3		T65	1
all_values[11]	auto[1]	auto[1]	auto[1]	73	1			T64	2		T65	1		T66	1
all_values[12]	auto[0]	auto[0]	auto[0]	48	1			T196	3		T228	2		T229	2
all_values[12]	auto[0]	auto[0]	auto[1]	82	1			T50	2		T64	3		T102	8
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T102	1		T196	1		T198	1
all_values[12]	auto[0]	auto[1]	auto[1]	75	1			T50	1		T64	3		T65	3
all_values[12]	auto[1]	auto[0]	auto[1]	83	1			T50	1		T64	6		T66	2
all_values[12]	auto[1]	auto[1]	auto[1]	64	1			T64	3		T65	1		T66	1
all_values[13]	auto[0]	auto[0]	auto[0]	28	1			T183	1		T225	1		T230	2
all_values[13]	auto[0]	auto[0]	auto[1]	83	1			T50	1		T64	4		T102	6
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T65	2		T198	2		T227	1
all_values[13]	auto[0]	auto[1]	auto[1]	75	1			T50	1		T64	6		T65	1
all_values[13]	auto[1]	auto[0]	auto[1]	90	1			T50	1		T64	3		T66	2
all_values[13]	auto[1]	auto[1]	auto[1]	77	1			T50	1		T64	2		T65	1
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T50	1		T66	1		T102	1
all_values[14]	auto[0]	auto[0]	auto[1]	86	1			T50	2		T64	3		T66	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T64	1		T65	1		T228	1
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T64	5		T65	2		T66	1
all_values[14]	auto[1]	auto[0]	auto[1]	90	1			T50	1		T64	4		T66	1
all_values[14]	auto[1]	auto[1]	auto[1]	73	1			T64	2		T65	1		T102	9

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal