Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.87 97.30 94.04 100.00 45.81 94.80 100.00 90.13


Total test records in report: 1198
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html
T1060 /workspace/coverage/default/28.i2c_target_stress_all.684337093 Mar 21 01:19:53 PM PDT 24 Mar 21 01:20:17 PM PDT 24 10415329344 ps
T1061 /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.694117485 Mar 21 01:18:13 PM PDT 24 Mar 21 01:18:19 PM PDT 24 354410526 ps
T1062 /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3667450835 Mar 21 01:20:50 PM PDT 24 Mar 21 01:20:54 PM PDT 24 250314994 ps
T104 /workspace/coverage/default/3.i2c_sec_cm.1172246475 Mar 21 01:17:28 PM PDT 24 Mar 21 01:17:29 PM PDT 24 135823707 ps
T1063 /workspace/coverage/default/20.i2c_target_fifo_reset_acq.4044591356 Mar 21 01:19:01 PM PDT 24 Mar 21 01:19:23 PM PDT 24 10298354149 ps
T1064 /workspace/coverage/default/12.i2c_host_error_intr.4036483337 Mar 21 01:18:18 PM PDT 24 Mar 21 01:18:20 PM PDT 24 43284389 ps
T1065 /workspace/coverage/default/18.i2c_target_timeout.651222264 Mar 21 01:18:48 PM PDT 24 Mar 21 01:18:54 PM PDT 24 2151184052 ps
T1066 /workspace/coverage/default/14.i2c_target_stress_rd.3617047623 Mar 21 01:18:26 PM PDT 24 Mar 21 01:19:25 PM PDT 24 1292522884 ps
T1067 /workspace/coverage/default/27.i2c_target_stretch.2708253475 Mar 21 01:19:29 PM PDT 24 Mar 21 01:33:06 PM PDT 24 19504516430 ps
T1068 /workspace/coverage/default/24.i2c_target_stress_rd.61412372 Mar 21 01:19:27 PM PDT 24 Mar 21 01:19:34 PM PDT 24 2019360568 ps
T1069 /workspace/coverage/default/19.i2c_target_stress_rd.2644867203 Mar 21 01:18:46 PM PDT 24 Mar 21 01:18:53 PM PDT 24 1814575024 ps
T1070 /workspace/coverage/default/48.i2c_host_override.122960572 Mar 21 01:21:24 PM PDT 24 Mar 21 01:21:25 PM PDT 24 18085813 ps
T1071 /workspace/coverage/default/40.i2c_host_smoke.1902916281 Mar 21 01:20:40 PM PDT 24 Mar 21 01:21:39 PM PDT 24 5022060845 ps
T1072 /workspace/coverage/default/19.i2c_host_fifo_reset_rx.302271499 Mar 21 01:18:45 PM PDT 24 Mar 21 01:18:54 PM PDT 24 562815256 ps
T1073 /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4109971688 Mar 21 01:20:34 PM PDT 24 Mar 21 01:20:47 PM PDT 24 10181399780 ps
T1074 /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2841374174 Mar 21 01:17:45 PM PDT 24 Mar 21 01:17:54 PM PDT 24 402959159 ps
T1075 /workspace/coverage/default/44.i2c_host_override.886066096 Mar 21 01:21:01 PM PDT 24 Mar 21 01:21:01 PM PDT 24 17419778 ps
T1076 /workspace/coverage/default/8.i2c_target_intr_smoke.8120112 Mar 21 01:17:54 PM PDT 24 Mar 21 01:17:59 PM PDT 24 980321732 ps
T1077 /workspace/coverage/default/42.i2c_target_hrst.2733973711 Mar 21 01:20:55 PM PDT 24 Mar 21 01:20:57 PM PDT 24 2907873327 ps
T1078 /workspace/coverage/default/17.i2c_target_intr_smoke.1055073424 Mar 21 01:18:37 PM PDT 24 Mar 21 01:18:42 PM PDT 24 2440154180 ps
T29 /workspace/coverage/default/33.i2c_host_error_intr.3646535127 Mar 21 01:20:06 PM PDT 24 Mar 21 01:20:08 PM PDT 24 49758716 ps
T1079 /workspace/coverage/default/6.i2c_target_timeout.1716077371 Mar 21 01:17:51 PM PDT 24 Mar 21 01:17:58 PM PDT 24 6638760675 ps
T1080 /workspace/coverage/default/22.i2c_target_stretch.1746932763 Mar 21 01:19:02 PM PDT 24 Mar 21 01:47:27 PM PDT 24 22888274898 ps
T1081 /workspace/coverage/default/19.i2c_target_smoke.4048514605 Mar 21 01:18:49 PM PDT 24 Mar 21 01:19:32 PM PDT 24 21631097881 ps
T1082 /workspace/coverage/default/43.i2c_host_error_intr.4219290001 Mar 21 01:20:48 PM PDT 24 Mar 21 01:20:49 PM PDT 24 44886745 ps
T1083 /workspace/coverage/default/18.i2c_host_error_intr.4046951047 Mar 21 01:18:45 PM PDT 24 Mar 21 01:18:47 PM PDT 24 86888909 ps
T1084 /workspace/coverage/default/21.i2c_target_stress_wr.3589814046 Mar 21 01:18:59 PM PDT 24 Mar 21 01:19:32 PM PDT 24 18483298549 ps
T1085 /workspace/coverage/default/8.i2c_host_override.4018066748 Mar 21 01:18:01 PM PDT 24 Mar 21 01:18:04 PM PDT 24 21777810 ps
T1086 /workspace/coverage/default/13.i2c_target_smoke.298504556 Mar 21 01:18:17 PM PDT 24 Mar 21 01:18:33 PM PDT 24 2412349723 ps
T1087 /workspace/coverage/default/31.i2c_target_stretch.728183141 Mar 21 01:19:49 PM PDT 24 Mar 21 01:23:38 PM PDT 24 27968117150 ps
T1088 /workspace/coverage/default/12.i2c_target_hrst.2416497485 Mar 21 01:18:22 PM PDT 24 Mar 21 01:18:24 PM PDT 24 1699420231 ps
T1089 /workspace/coverage/default/15.i2c_target_timeout.406572110 Mar 21 01:18:36 PM PDT 24 Mar 21 01:18:43 PM PDT 24 5529223953 ps
T1090 /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3077662650 Mar 21 01:21:17 PM PDT 24 Mar 21 01:21:26 PM PDT 24 10591610861 ps
T230 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1932713963 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 36836972 ps
T75 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2088744240 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:16 PM PDT 24 45873274 ps
T61 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2497486531 Mar 21 12:57:01 PM PDT 24 Mar 21 12:57:01 PM PDT 24 18185260 ps
T76 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2543452697 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:58 PM PDT 24 101840191 ps
T62 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3875267976 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:57 PM PDT 24 171135516 ps
T63 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3336845760 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:55 PM PDT 24 35896149 ps
T77 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2495360127 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 56524215 ps
T85 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2739091649 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 145800615 ps
T128 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1242180827 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:53 PM PDT 24 28159901 ps
T229 /workspace/coverage/cover_reg_top/44.i2c_intr_test.578930772 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 43584201 ps
T78 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2602952499 Mar 21 12:56:52 PM PDT 24 Mar 21 12:56:55 PM PDT 24 462456819 ps
T226 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3060083033 Mar 21 12:57:11 PM PDT 24 Mar 21 12:57:11 PM PDT 24 16039549 ps
T227 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2365450387 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 60066246 ps
T79 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.838535937 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:13 PM PDT 24 177361437 ps
T129 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3950632066 Mar 21 12:57:15 PM PDT 24 Mar 21 12:57:16 PM PDT 24 69393217 ps
T154 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1165596676 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:07 PM PDT 24 30907167 ps
T155 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1408424473 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:21 PM PDT 24 48277725 ps
T117 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3538455706 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:05 PM PDT 24 275586356 ps
T94 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1193238815 Mar 21 12:57:03 PM PDT 24 Mar 21 12:57:05 PM PDT 24 91449713 ps
T156 /workspace/coverage/cover_reg_top/15.i2c_intr_test.411817866 Mar 21 12:57:15 PM PDT 24 Mar 21 12:57:16 PM PDT 24 54516650 ps
T130 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1355761946 Mar 21 12:57:01 PM PDT 24 Mar 21 12:57:02 PM PDT 24 64545964 ps
T86 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.170799902 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 289907167 ps
T131 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.682804307 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:13 PM PDT 24 97882300 ps
T1091 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1443795728 Mar 21 12:57:22 PM PDT 24 Mar 21 12:57:23 PM PDT 24 16743916 ps
T1092 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3970190596 Mar 21 12:57:22 PM PDT 24 Mar 21 12:57:23 PM PDT 24 18331158 ps
T157 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2309348970 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 57131857 ps
T83 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2660729957 Mar 21 12:56:58 PM PDT 24 Mar 21 12:57:00 PM PDT 24 522850003 ps
T1093 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1484120688 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 18089543 ps
T132 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1921863122 Mar 21 12:57:01 PM PDT 24 Mar 21 12:57:02 PM PDT 24 133898745 ps
T133 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2783483887 Mar 21 12:57:02 PM PDT 24 Mar 21 12:57:03 PM PDT 24 78211840 ps
T113 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2814071605 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 76689106 ps
T1094 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1532564054 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 20367460 ps
T84 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2334964843 Mar 21 12:56:57 PM PDT 24 Mar 21 12:56:59 PM PDT 24 139761971 ps
T1095 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1617127506 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:08 PM PDT 24 29428803 ps
T114 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2625235380 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 87548113 ps
T87 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1903336554 Mar 21 12:57:02 PM PDT 24 Mar 21 12:57:04 PM PDT 24 49741990 ps
T88 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2359651483 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:16 PM PDT 24 115120960 ps
T1096 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2753194006 Mar 21 12:57:02 PM PDT 24 Mar 21 12:57:07 PM PDT 24 113475939 ps
T99 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2391522817 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:19 PM PDT 24 113027863 ps
T95 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2136851500 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 291743995 ps
T137 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3224212426 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:05 PM PDT 24 402187217 ps
T213 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.281807143 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 169332574 ps
T134 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2720502138 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 96046005 ps
T1097 /workspace/coverage/cover_reg_top/5.i2c_intr_test.4008386620 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:06 PM PDT 24 48926726 ps
T1098 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2456930477 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 72777387 ps
T1099 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1009121524 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:25 PM PDT 24 38410341 ps
T215 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1876016296 Mar 21 12:57:00 PM PDT 24 Mar 21 12:57:02 PM PDT 24 233581978 ps
T180 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1519055318 Mar 21 12:57:03 PM PDT 24 Mar 21 12:57:04 PM PDT 24 25403693 ps
T1100 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3751757894 Mar 21 12:57:09 PM PDT 24 Mar 21 12:57:09 PM PDT 24 25106302 ps
T135 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1044690278 Mar 21 12:57:18 PM PDT 24 Mar 21 12:57:19 PM PDT 24 17330196 ps
T96 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1238295183 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:09 PM PDT 24 444132764 ps
T1101 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.630685821 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:08 PM PDT 24 17500297 ps
T1102 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2722818566 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:09 PM PDT 24 488222391 ps
T136 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4167761910 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 59475214 ps
T1103 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.775112148 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 59167882 ps
T118 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2461644291 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:06 PM PDT 24 141215290 ps
T1104 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1398620383 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 52809827 ps
T119 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.212577179 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:06 PM PDT 24 16469097 ps
T1105 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.432955216 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:07 PM PDT 24 132729219 ps
T1106 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2047863901 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 129630945 ps
T214 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1343178834 Mar 21 12:56:55 PM PDT 24 Mar 21 12:56:56 PM PDT 24 79542396 ps
T1107 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1095583319 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 28139386 ps
T1108 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2267753269 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 17451680 ps
T1109 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3971978852 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:08 PM PDT 24 1072020038 ps
T1110 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3444423700 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:24 PM PDT 24 704220618 ps
T1111 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2681695183 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 85389220 ps
T1112 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2796915099 Mar 21 12:57:18 PM PDT 24 Mar 21 12:57:19 PM PDT 24 21098596 ps
T1113 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2352349328 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 166487821 ps
T93 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3464284491 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 661966129 ps
T1114 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3533052025 Mar 21 12:57:22 PM PDT 24 Mar 21 12:57:23 PM PDT 24 50102771 ps
T1115 /workspace/coverage/cover_reg_top/17.i2c_intr_test.859930013 Mar 21 12:57:17 PM PDT 24 Mar 21 12:57:18 PM PDT 24 29369515 ps
T1116 /workspace/coverage/cover_reg_top/27.i2c_intr_test.37337840 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 51449082 ps
T1117 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3099390282 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 32787653 ps
T1118 /workspace/coverage/cover_reg_top/46.i2c_intr_test.868593779 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:23 PM PDT 24 18281321 ps
T120 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1571603796 Mar 21 12:57:15 PM PDT 24 Mar 21 12:57:16 PM PDT 24 23412856 ps
T1119 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1372318026 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:21 PM PDT 24 17466752 ps
T92 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4061053945 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:57 PM PDT 24 89615360 ps
T1120 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3999927333 Mar 21 12:57:18 PM PDT 24 Mar 21 12:57:19 PM PDT 24 100470765 ps
T1121 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2792834564 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:21 PM PDT 24 21220169 ps
T121 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3150909323 Mar 21 12:56:52 PM PDT 24 Mar 21 12:56:54 PM PDT 24 43148484 ps
T1122 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.366383546 Mar 21 12:57:17 PM PDT 24 Mar 21 12:57:18 PM PDT 24 31962916 ps
T1123 /workspace/coverage/cover_reg_top/8.i2c_intr_test.972080938 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:05 PM PDT 24 48340789 ps
T1124 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.517005570 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:56 PM PDT 24 23992966 ps
T1125 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.447029699 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:57 PM PDT 24 91765186 ps
T1126 /workspace/coverage/cover_reg_top/22.i2c_intr_test.199835310 Mar 21 12:57:22 PM PDT 24 Mar 21 12:57:23 PM PDT 24 17945167 ps
T1127 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2351257743 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:14 PM PDT 24 46745667 ps
T1128 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.589124933 Mar 21 12:57:01 PM PDT 24 Mar 21 12:57:03 PM PDT 24 381269467 ps
T1129 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.223665108 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:13 PM PDT 24 26349517 ps
T1130 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2098525233 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:21 PM PDT 24 41896750 ps
T1131 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.285283558 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:57 PM PDT 24 31519583 ps
T122 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1852178575 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 20705746 ps
T1132 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3242561458 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:21 PM PDT 24 25723903 ps
T123 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1687877294 Mar 21 12:56:56 PM PDT 24 Mar 21 12:56:58 PM PDT 24 63358072 ps
T97 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.664983630 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:06 PM PDT 24 348214443 ps
T1133 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2046384805 Mar 21 12:56:54 PM PDT 24 Mar 21 12:56:57 PM PDT 24 375125919 ps
T1134 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3401131400 Mar 21 12:57:02 PM PDT 24 Mar 21 12:57:04 PM PDT 24 86501662 ps
T1135 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1227821194 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:05 PM PDT 24 61212811 ps
T1136 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3717450179 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:23 PM PDT 24 55967603 ps
T1137 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.912415029 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 55598762 ps
T1138 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.938925547 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 133030296 ps
T1139 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1475582569 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:09 PM PDT 24 910322380 ps
T1140 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1894242459 Mar 21 12:57:11 PM PDT 24 Mar 21 12:57:12 PM PDT 24 18906770 ps
T1141 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2047367741 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:23 PM PDT 24 19577032 ps
T1142 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1628335315 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 118465385 ps
T124 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3230695306 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 53948348 ps
T1143 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2298050192 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 28044231 ps
T1144 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3521995096 Mar 21 12:57:09 PM PDT 24 Mar 21 12:57:10 PM PDT 24 339012412 ps
T1145 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4032862118 Mar 21 12:57:01 PM PDT 24 Mar 21 12:57:05 PM PDT 24 117638923 ps
T1146 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1758586871 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 18333282 ps
T1147 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4225039809 Mar 21 12:57:02 PM PDT 24 Mar 21 12:57:02 PM PDT 24 61936102 ps
T1148 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1639225118 Mar 21 12:57:03 PM PDT 24 Mar 21 12:57:04 PM PDT 24 44484869 ps
T1149 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2018485827 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:23 PM PDT 24 35492043 ps
T1150 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2203806978 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:24 PM PDT 24 15753320 ps
T1151 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2882216535 Mar 21 12:56:55 PM PDT 24 Mar 21 12:56:58 PM PDT 24 715974983 ps
T1152 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2899207189 Mar 21 12:57:31 PM PDT 24 Mar 21 12:57:32 PM PDT 24 19039002 ps
T1153 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2963084675 Mar 21 12:57:22 PM PDT 24 Mar 21 12:57:23 PM PDT 24 24094131 ps
T1154 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4237216619 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:08 PM PDT 24 75034475 ps
T1155 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.845772702 Mar 21 12:56:52 PM PDT 24 Mar 21 12:56:57 PM PDT 24 680115579 ps
T1156 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1343039002 Mar 21 12:56:50 PM PDT 24 Mar 21 12:56:51 PM PDT 24 194018735 ps
T1157 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4260614578 Mar 21 12:57:06 PM PDT 24 Mar 21 12:57:07 PM PDT 24 20966429 ps
T1158 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.150208098 Mar 21 12:57:15 PM PDT 24 Mar 21 12:57:16 PM PDT 24 28627861 ps
T1159 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2487432709 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 52019631 ps
T125 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2518760603 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 45073637 ps
T1160 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1709673519 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 17021037 ps
T1161 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1866186493 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:05 PM PDT 24 44427950 ps
T1162 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1101014007 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 17206688 ps
T1163 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3553736685 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:21 PM PDT 24 18251366 ps
T1164 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4107601268 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 217455951 ps
T1165 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2226246708 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 57570283 ps
T1166 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2734792151 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:16 PM PDT 24 287556282 ps
T1167 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1761597853 Mar 21 12:56:57 PM PDT 24 Mar 21 12:56:58 PM PDT 24 39076203 ps
T1168 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2445660290 Mar 21 12:57:17 PM PDT 24 Mar 21 12:57:19 PM PDT 24 74127675 ps
T1169 /workspace/coverage/cover_reg_top/30.i2c_intr_test.213742094 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 26550381 ps
T1170 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2337837402 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:13 PM PDT 24 60180873 ps
T1171 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1605144372 Mar 21 12:57:23 PM PDT 24 Mar 21 12:57:24 PM PDT 24 15326330 ps
T1172 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1531979128 Mar 21 12:57:03 PM PDT 24 Mar 21 12:57:05 PM PDT 24 185368739 ps
T98 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2166720573 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:06 PM PDT 24 247345523 ps
T1173 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3102229944 Mar 21 12:56:53 PM PDT 24 Mar 21 12:56:54 PM PDT 24 23076448 ps
T1174 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2622404635 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 81575810 ps
T1175 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2830963466 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 28633780 ps
T1176 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4223901160 Mar 21 12:57:19 PM PDT 24 Mar 21 12:57:20 PM PDT 24 31950234 ps
T1177 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2861334985 Mar 21 12:57:20 PM PDT 24 Mar 21 12:57:22 PM PDT 24 483489242 ps
T1178 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4093580185 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 120042766 ps
T1179 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1373633577 Mar 21 12:57:24 PM PDT 24 Mar 21 12:57:25 PM PDT 24 43557351 ps
T127 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.638766900 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 18917686 ps
T1180 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1033533250 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:05 PM PDT 24 119196765 ps
T1181 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1457127706 Mar 21 12:57:15 PM PDT 24 Mar 21 12:57:17 PM PDT 24 545610291 ps
T1182 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1067731116 Mar 21 12:57:11 PM PDT 24 Mar 21 12:57:12 PM PDT 24 128813242 ps
T1183 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.751397 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:15 PM PDT 24 90107295 ps
T1184 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1598514885 Mar 21 12:57:04 PM PDT 24 Mar 21 12:57:04 PM PDT 24 44958084 ps
T1185 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1527519012 Mar 21 12:56:52 PM PDT 24 Mar 21 12:56:53 PM PDT 24 87198114 ps
T1186 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3088150372 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:08 PM PDT 24 27366275 ps
T1187 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3715962394 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 34824599 ps
T126 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2975467198 Mar 21 12:56:54 PM PDT 24 Mar 21 12:56:55 PM PDT 24 21784934 ps
T1188 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1588056967 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:06 PM PDT 24 17917941 ps
T1189 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3491181920 Mar 21 12:57:05 PM PDT 24 Mar 21 12:57:05 PM PDT 24 60413582 ps
T1190 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2040559650 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:17 PM PDT 24 49050514 ps
T1191 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2789826624 Mar 21 12:57:07 PM PDT 24 Mar 21 12:57:08 PM PDT 24 98703651 ps
T1192 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1497318358 Mar 21 12:57:00 PM PDT 24 Mar 21 12:57:01 PM PDT 24 72659198 ps
T1193 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4179905301 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 15979927 ps
T1194 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1901197852 Mar 21 12:57:16 PM PDT 24 Mar 21 12:57:18 PM PDT 24 94644201 ps
T1195 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2513390131 Mar 21 12:57:21 PM PDT 24 Mar 21 12:57:22 PM PDT 24 33617045 ps
T1196 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3610181399 Mar 21 12:57:14 PM PDT 24 Mar 21 12:57:15 PM PDT 24 55741813 ps
T1197 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1310475570 Mar 21 12:57:12 PM PDT 24 Mar 21 12:57:12 PM PDT 24 40250657 ps
T1198 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2049917631 Mar 21 12:57:13 PM PDT 24 Mar 21 12:57:14 PM PDT 24 82781186 ps

Test location /workspace/coverage/default/9.i2c_host_fifo_full.853054916
Short name T1
Test name
Test status
Simulation time 10052244960 ps
CPU time 48.52 seconds
Started Mar 21 01:17:55 PM PDT 24
Finished Mar 21 01:18:44 PM PDT 24
Peak memory 494880 kb
Host smart-561f2648-af48-4cc0-ab53-23906bdb69d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853054916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.853054916
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1842341895
Short name T57
Test name
Test status
Simulation time 10063597030 ps
CPU time 36.78 seconds
Started Mar 21 01:18:20 PM PDT 24
Finished Mar 21 01:18:56 PM PDT 24
Peak memory 410520 kb
Host smart-e0e1bee3-079c-4dd5-8e80-168a210dd9ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842341895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1842341895
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2570270994
Short name T64
Test name
Test status
Simulation time 7414885021 ps
CPU time 554.5 seconds
Started Mar 21 01:17:58 PM PDT 24
Finished Mar 21 01:27:12 PM PDT 24
Peak memory 1650928 kb
Host smart-90f785b5-6ecf-4bde-b999-15016cecfee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570270994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2570270994
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2739091649
Short name T85
Test name
Test status
Simulation time 145800615 ps
CPU time 0.84 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203440 kb
Host smart-76a1481b-7f41-498b-84ef-7389a6c3fb1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739091649 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2739091649
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2703716936
Short name T34
Test name
Test status
Simulation time 10185984431 ps
CPU time 7.58 seconds
Started Mar 21 01:19:36 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 242184 kb
Host smart-3a9dc7cf-6561-4c28-b230-31d5940962e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703716936 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2703716936
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.211105335
Short name T50
Test name
Test status
Simulation time 15432115648 ps
CPU time 884.86 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:35:06 PM PDT 24
Peak memory 1478312 kb
Host smart-b2a2969e-b3dd-4b6d-8c94-c98d6b0db2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211105335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.211105335
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_override.3524495397
Short name T166
Test name
Test status
Simulation time 19819553 ps
CPU time 0.66 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:17:26 PM PDT 24
Peak memory 202448 kb
Host smart-01fff4b7-9b2a-4c2d-b223-b469b1b57bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524495397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3524495397
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2211407609
Short name T11
Test name
Test status
Simulation time 3147001137 ps
CPU time 13.76 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:07 PM PDT 24
Peak memory 265816 kb
Host smart-e4e5d3f9-2fb3-4c1c-a230-aeb9c2f22076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211407609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2211407609
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.1257361655
Short name T52
Test name
Test status
Simulation time 11751016322 ps
CPU time 5.64 seconds
Started Mar 21 01:17:50 PM PDT 24
Finished Mar 21 01:17:56 PM PDT 24
Peak memory 203356 kb
Host smart-75ef0cee-8398-4357-81e7-baddbf795f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257361655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.1257361655
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.838535937
Short name T79
Test name
Test status
Simulation time 177361437 ps
CPU time 1.2 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:13 PM PDT 24
Peak memory 203568 kb
Host smart-7878f5d1-3b4e-4c98-bc47-fca155543571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838535937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.838535937
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.603883876
Short name T225
Test name
Test status
Simulation time 40532288053 ps
CPU time 857.05 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:33:05 PM PDT 24
Peak memory 1102180 kb
Host smart-8f4e05e2-0bce-49b2-9f1f-79956444ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603883876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.603883876
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_alert_test.504026210
Short name T306
Test name
Test status
Simulation time 15123328 ps
CPU time 0.65 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:17:36 PM PDT 24
Peak memory 203148 kb
Host smart-67148580-28a3-44c7-b2a2-5d186dad62ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504026210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.504026210
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3150909323
Short name T121
Test name
Test status
Simulation time 43148484 ps
CPU time 1.57 seconds
Started Mar 21 12:56:52 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203364 kb
Host smart-c73b5657-cecd-4b0e-b0ab-8d01d24cd293
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150909323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3150909323
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.982184305
Short name T251
Test name
Test status
Simulation time 2220395049 ps
CPU time 3.6 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:20:24 PM PDT 24
Peak memory 211552 kb
Host smart-ba4dfec9-3407-4ee0-a945-ad939e8cccdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982184305 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.982184305
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2088744240
Short name T75
Test name
Test status
Simulation time 45873274 ps
CPU time 2.09 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203652 kb
Host smart-4e355ed3-4fad-41d1-9b5e-336bbbdee471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088744240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2088744240
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.338887588
Short name T6
Test name
Test status
Simulation time 138343344 ps
CPU time 1.15 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 202860 kb
Host smart-234084a7-6385-4a9d-be31-07d6bde1c7bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338887588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.338887588
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3675424226
Short name T80
Test name
Test status
Simulation time 40140401 ps
CPU time 0.86 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 220468 kb
Host smart-0b542e6e-4523-4ca7-bdaa-ec4679e3dfda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675424226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3675424226
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2749160661
Short name T1037
Test name
Test status
Simulation time 516024960 ps
CPU time 3.03 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:18:14 PM PDT 24
Peak memory 203332 kb
Host smart-1f9f98d8-80be-4cda-86b0-2815d2b6e5ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749160661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2749160661
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1027426271
Short name T370
Test name
Test status
Simulation time 4918485120 ps
CPU time 6.43 seconds
Started Mar 21 01:18:04 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 213304 kb
Host smart-89ed90c4-2e95-45a4-8e22-09cb93fb7d7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027426271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1027426271
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.4083371369
Short name T72
Test name
Test status
Simulation time 5242225072 ps
CPU time 56.41 seconds
Started Mar 21 01:20:18 PM PDT 24
Finished Mar 21 01:21:16 PM PDT 24
Peak memory 327792 kb
Host smart-1147dce4-d3d9-4b00-b912-6ea1067ebc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083371369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4083371369
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2365450387
Short name T227
Test name
Test status
Simulation time 60066246 ps
CPU time 0.75 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203260 kb
Host smart-106441cf-a8a8-4bf9-8807-96cfc9fd78d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365450387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2365450387
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.22043944
Short name T141
Test name
Test status
Simulation time 3676681645 ps
CPU time 93.83 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:21:12 PM PDT 24
Peak memory 1117316 kb
Host smart-671abd73-0537-425e-9144-27424b79bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22043944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.22043944
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1394127534
Short name T204
Test name
Test status
Simulation time 2988466010 ps
CPU time 103.55 seconds
Started Mar 21 01:18:50 PM PDT 24
Finished Mar 21 01:20:33 PM PDT 24
Peak memory 420116 kb
Host smart-b752832d-6ef0-4637-9c1e-b40f72a5236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394127534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1394127534
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1023532225
Short name T206
Test name
Test status
Simulation time 1568703333 ps
CPU time 2.6 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:37 PM PDT 24
Peak memory 203408 kb
Host smart-d1da4bed-f159-439f-93a9-789eafecb3a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023532225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1023532225
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1450166466
Short name T28
Test name
Test status
Simulation time 49985553 ps
CPU time 1.36 seconds
Started Mar 21 01:17:46 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 211504 kb
Host smart-dd558f3d-d24f-4803-a56f-bddda3d33ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450166466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1450166466
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2275626862
Short name T450
Test name
Test status
Simulation time 876142238 ps
CPU time 7.47 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:30 PM PDT 24
Peak memory 203184 kb
Host smart-06d6651c-b013-4a17-915b-1fb8b6a09d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275626862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2275626862
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.4164457862
Short name T66
Test name
Test status
Simulation time 17734620934 ps
CPU time 2056.75 seconds
Started Mar 21 01:18:06 PM PDT 24
Finished Mar 21 01:52:24 PM PDT 24
Peak memory 1757544 kb
Host smart-f6e4c7d7-c57b-4e82-aece-77a793f0ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164457862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.4164457862
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1238295183
Short name T96
Test name
Test status
Simulation time 444132764 ps
CPU time 2.04 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:09 PM PDT 24
Peak memory 203472 kb
Host smart-83cd0a3a-7cd1-4b28-b05f-457a723ab692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238295183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1238295183
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1242180827
Short name T128
Test name
Test status
Simulation time 28159901 ps
CPU time 0.69 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:53 PM PDT 24
Peak memory 202988 kb
Host smart-da2eb307-0f8b-45f7-937d-579de5770c29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242180827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1242180827
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3868339147
Short name T193
Test name
Test status
Simulation time 192287441 ps
CPU time 0.86 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 203160 kb
Host smart-46ff271e-e639-4565-8aeb-7bf09583cf3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868339147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3868339147
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.965473940
Short name T185
Test name
Test status
Simulation time 11125107269 ps
CPU time 4.47 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:18:15 PM PDT 24
Peak memory 216136 kb
Host smart-b1d2df8e-8764-4024-8cdb-a2759bf65fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965473940 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.965473940
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3893420115
Short name T234
Test name
Test status
Simulation time 1121436027 ps
CPU time 5.27 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:18:32 PM PDT 24
Peak memory 203312 kb
Host smart-b6f53109-f166-4898-9f44-6278cfe5057b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893420115 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3893420115
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.187561078
Short name T150
Test name
Test status
Simulation time 8104070205 ps
CPU time 145.06 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:20:59 PM PDT 24
Peak memory 688564 kb
Host smart-4a141f26-31dd-45d8-bcf7-7f767c2b4b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187561078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.187561078
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1435180393
Short name T198
Test name
Test status
Simulation time 58012832590 ps
CPU time 2346.88 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:59:28 PM PDT 24
Peak memory 2728856 kb
Host smart-57b7f8cf-f44e-46d2-8356-c643c5cd8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435180393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1435180393
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1548502478
Short name T195
Test name
Test status
Simulation time 225224188 ps
CPU time 1.06 seconds
Started Mar 21 01:21:17 PM PDT 24
Finished Mar 21 01:21:18 PM PDT 24
Peak memory 202888 kb
Host smart-35c56849-9bfa-4afa-915b-190a713c3f48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548502478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1548502478
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_override.4064668088
Short name T202
Test name
Test status
Simulation time 51780909 ps
CPU time 0.62 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:17:54 PM PDT 24
Peak memory 202440 kb
Host smart-d984f407-3e3c-4a4b-861c-9338a18dd5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064668088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.4064668088
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2232257994
Short name T235
Test name
Test status
Simulation time 5821458966 ps
CPU time 96.98 seconds
Started Mar 21 01:18:14 PM PDT 24
Finished Mar 21 01:19:52 PM PDT 24
Peak memory 537132 kb
Host smart-44e09d46-5334-4fd6-aece-a94275ae08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232257994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2232257994
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2660729957
Short name T83
Test name
Test status
Simulation time 522850003 ps
CPU time 2.14 seconds
Started Mar 21 12:56:58 PM PDT 24
Finished Mar 21 12:57:00 PM PDT 24
Peak memory 203504 kb
Host smart-c7886e04-1860-42c2-b2e7-521dd1ebc76b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660729957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2660729957
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2602952499
Short name T78
Test name
Test status
Simulation time 462456819 ps
CPU time 2.24 seconds
Started Mar 21 12:56:52 PM PDT 24
Finished Mar 21 12:56:55 PM PDT 24
Peak memory 203580 kb
Host smart-631758b0-0352-49c9-aa0a-307d10fe6da0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602952499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2602952499
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2326033833
Short name T22
Test name
Test status
Simulation time 36751932415 ps
CPU time 269.39 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:21:53 PM PDT 24
Peak memory 1861260 kb
Host smart-1caa5af1-4ce5-4ba9-8a8c-c4db568b7317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326033833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2326033833
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2397283401
Short name T208
Test name
Test status
Simulation time 1805651403 ps
CPU time 75.28 seconds
Started Mar 21 01:18:25 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 206548 kb
Host smart-572edb32-4728-4471-b7c4-c172e603ee03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397283401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2397283401
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1146373384
Short name T231
Test name
Test status
Simulation time 10050636096 ps
CPU time 70.63 seconds
Started Mar 21 01:18:23 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 625196 kb
Host smart-df943ea5-5e31-4646-905e-d99186f02e8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146373384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1146373384
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.999047924
Short name T218
Test name
Test status
Simulation time 12632588805 ps
CPU time 68.83 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:20:07 PM PDT 24
Peak memory 958372 kb
Host smart-c12713bd-57c9-4d98-9a65-419397483f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999047924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.999047924
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1325654477
Short name T222
Test name
Test status
Simulation time 4749771686 ps
CPU time 60.44 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 770476 kb
Host smart-b10a56bf-157a-4967-bdc9-baef3ab9c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325654477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1325654477
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3793229388
Short name T223
Test name
Test status
Simulation time 7376692582 ps
CPU time 103.82 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:19:33 PM PDT 24
Peak memory 1158684 kb
Host smart-5eb76d1c-3c57-4bbe-85de-5d8bd2e9aa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793229388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3793229388
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3464284491
Short name T93
Test name
Test status
Simulation time 661966129 ps
CPU time 2.05 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203440 kb
Host smart-04890edf-1321-4e15-b10a-2699f4d7d51c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464284491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3464284491
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4061053945
Short name T92
Test name
Test status
Simulation time 89615360 ps
CPU time 1.33 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203436 kb
Host smart-95e22d28-ce6a-4069-941d-5c69340db3c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061053945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.4061053945
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3646535127
Short name T29
Test name
Test status
Simulation time 49758716 ps
CPU time 1.7 seconds
Started Mar 21 01:20:06 PM PDT 24
Finished Mar 21 01:20:08 PM PDT 24
Peak memory 211524 kb
Host smart-4ef86514-7098-43fc-a22a-01f24c15b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646535127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3646535127
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.845772702
Short name T1155
Test name
Test status
Simulation time 680115579 ps
CPU time 4.81 seconds
Started Mar 21 12:56:52 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203404 kb
Host smart-0bb3113e-202d-4231-b8a0-4284ad985e99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845772702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.845772702
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3099390282
Short name T1117
Test name
Test status
Simulation time 32787653 ps
CPU time 0.68 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 202544 kb
Host smart-27fc96c0-23be-4467-99aa-248f177cfb14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099390282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3099390282
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.775112148
Short name T1103
Test name
Test status
Simulation time 59167882 ps
CPU time 0.93 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203388 kb
Host smart-19b5d56e-882f-452a-8f55-5c8efcc44fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775112148 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.775112148
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3102229944
Short name T1173
Test name
Test status
Simulation time 23076448 ps
CPU time 0.69 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203236 kb
Host smart-d05eea64-add1-46b1-9b12-4c1811408373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102229944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3102229944
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1343039002
Short name T1156
Test name
Test status
Simulation time 194018735 ps
CPU time 0.77 seconds
Started Mar 21 12:56:50 PM PDT 24
Finished Mar 21 12:56:51 PM PDT 24
Peak memory 203296 kb
Host smart-51b1d060-7d71-458b-8acd-b9deb69e59d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343039002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1343039002
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1527519012
Short name T1185
Test name
Test status
Simulation time 87198114 ps
CPU time 1.27 seconds
Started Mar 21 12:56:52 PM PDT 24
Finished Mar 21 12:56:53 PM PDT 24
Peak memory 203564 kb
Host smart-bbeb7ff1-eb2f-4952-aabe-7748cdc227ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527519012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1527519012
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3336845760
Short name T63
Test name
Test status
Simulation time 35896149 ps
CPU time 1.59 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:55 PM PDT 24
Peak memory 203648 kb
Host smart-41986c99-b1e7-49b2-bbc5-7eb29500e688
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336845760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3336845760
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2046384805
Short name T1133
Test name
Test status
Simulation time 375125919 ps
CPU time 2.71 seconds
Started Mar 21 12:56:54 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203368 kb
Host smart-1d99757c-b79f-4ded-a5d5-1efff666a7a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046384805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2046384805
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1532564054
Short name T1094
Test name
Test status
Simulation time 20367460 ps
CPU time 0.69 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203236 kb
Host smart-bf2ad0d4-146a-4fc1-be9d-48fbd976ccb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532564054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1532564054
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2495360127
Short name T77
Test name
Test status
Simulation time 56524215 ps
CPU time 0.86 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203640 kb
Host smart-9cca2e49-9db8-472f-bf49-8b074028e544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495360127 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2495360127
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.517005570
Short name T1124
Test name
Test status
Simulation time 23992966 ps
CPU time 0.66 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:56 PM PDT 24
Peak memory 202932 kb
Host smart-8bf69aaf-acdb-41af-9078-bce3a0a78f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517005570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.517005570
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1484120688
Short name T1093
Test name
Test status
Simulation time 18089543 ps
CPU time 0.65 seconds
Started Mar 21 12:56:53 PM PDT 24
Finished Mar 21 12:56:54 PM PDT 24
Peak memory 203228 kb
Host smart-13aef91c-1c3a-4cf6-8cfb-67d168983aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484120688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1484120688
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.447029699
Short name T1125
Test name
Test status
Simulation time 91765186 ps
CPU time 0.78 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203336 kb
Host smart-0ff8a00d-e509-4715-9469-80e60729aff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447029699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.447029699
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1343178834
Short name T214
Test name
Test status
Simulation time 79542396 ps
CPU time 1.44 seconds
Started Mar 21 12:56:55 PM PDT 24
Finished Mar 21 12:56:56 PM PDT 24
Peak memory 203544 kb
Host smart-406a8927-6b67-4feb-bc88-66524f2f67a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343178834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1343178834
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1894242459
Short name T1140
Test name
Test status
Simulation time 18906770 ps
CPU time 0.74 seconds
Started Mar 21 12:57:11 PM PDT 24
Finished Mar 21 12:57:12 PM PDT 24
Peak memory 203368 kb
Host smart-abb69eb1-db8d-46f7-b069-a455003c2171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894242459 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1894242459
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3230695306
Short name T124
Test name
Test status
Simulation time 53948348 ps
CPU time 0.68 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 202908 kb
Host smart-3f42f6c8-b0e2-4cf1-b88f-5110069a81c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230695306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3230695306
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3060083033
Short name T226
Test name
Test status
Simulation time 16039549 ps
CPU time 0.65 seconds
Started Mar 21 12:57:11 PM PDT 24
Finished Mar 21 12:57:11 PM PDT 24
Peak memory 203312 kb
Host smart-662e3146-1278-4c8a-8c14-129f05d2ac91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060083033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3060083033
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.682804307
Short name T131
Test name
Test status
Simulation time 97882300 ps
CPU time 1.01 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:13 PM PDT 24
Peak memory 203556 kb
Host smart-97eb702d-3aa4-4bd2-949a-10379fb7a134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682804307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.682804307
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2352349328
Short name T1113
Test name
Test status
Simulation time 166487821 ps
CPU time 1.14 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203552 kb
Host smart-c7e81378-6560-47f1-8ba9-5139814a9136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352349328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2352349328
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4093580185
Short name T1178
Test name
Test status
Simulation time 120042766 ps
CPU time 1.39 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203496 kb
Host smart-5ed989e9-b25f-493c-88d3-b405dcd1ac1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093580185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4093580185
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2040559650
Short name T1190
Test name
Test status
Simulation time 49050514 ps
CPU time 0.86 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203436 kb
Host smart-19bddeb0-14ff-4cd4-a6b0-777a25a78bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040559650 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2040559650
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.638766900
Short name T127
Test name
Test status
Simulation time 18917686 ps
CPU time 0.69 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203012 kb
Host smart-b7c0dc50-a97e-40ed-af0c-c6b9eb1284f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638766900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.638766900
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2309348970
Short name T157
Test name
Test status
Simulation time 57131857 ps
CPU time 0.65 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203288 kb
Host smart-62dca3e3-927e-4841-b135-eff794b27cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309348970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2309348970
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2720502138
Short name T134
Test name
Test status
Simulation time 96046005 ps
CPU time 0.78 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203340 kb
Host smart-54bcd955-1696-48a7-9f8c-085c33bbb300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720502138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2720502138
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2445660290
Short name T1168
Test name
Test status
Simulation time 74127675 ps
CPU time 1.91 seconds
Started Mar 21 12:57:17 PM PDT 24
Finished Mar 21 12:57:19 PM PDT 24
Peak memory 203588 kb
Host smart-b150fbd4-6a31-4c06-b2ad-140c75dae06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445660290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2445660290
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2047863901
Short name T1106
Test name
Test status
Simulation time 129630945 ps
CPU time 1.02 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203372 kb
Host smart-3cdd7dc5-e1b4-4e6d-877c-45935467ccc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047863901 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2047863901
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1571603796
Short name T120
Test name
Test status
Simulation time 23412856 ps
CPU time 0.69 seconds
Started Mar 21 12:57:15 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203232 kb
Host smart-0f7d555a-0297-4cf3-b152-6437455d20a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571603796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1571603796
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2830963466
Short name T1175
Test name
Test status
Simulation time 28633780 ps
CPU time 0.66 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203220 kb
Host smart-a57b2666-1385-4a85-a517-292f28accf5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830963466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2830963466
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2351257743
Short name T1127
Test name
Test status
Simulation time 46745667 ps
CPU time 1 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203512 kb
Host smart-98beff7c-43a5-4ef1-a18e-9ba1b848cdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351257743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2351257743
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.751397
Short name T1183
Test name
Test status
Simulation time 90107295 ps
CPU time 2.06 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203668 kb
Host smart-e9d74397-f7a6-4a93-bc8e-91359fd5d6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.751397
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2622404635
Short name T1174
Test name
Test status
Simulation time 81575810 ps
CPU time 1.47 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203496 kb
Host smart-e3c658f3-7e1e-4bd0-a076-619c06002a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622404635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2622404635
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2049917631
Short name T1198
Test name
Test status
Simulation time 82781186 ps
CPU time 0.79 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203348 kb
Host smart-22ebd1ea-3d20-45db-91e2-a03828e2dd25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049917631 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2049917631
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2337837402
Short name T1170
Test name
Test status
Simulation time 60180873 ps
CPU time 0.68 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:13 PM PDT 24
Peak memory 203360 kb
Host smart-d736ec9a-1114-49f9-b267-8c8c6d102a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337837402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2337837402
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3610181399
Short name T1196
Test name
Test status
Simulation time 55741813 ps
CPU time 0.66 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203196 kb
Host smart-039bcf87-1a23-494d-8dff-fdbfe6436a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610181399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3610181399
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4167761910
Short name T136
Test name
Test status
Simulation time 59475214 ps
CPU time 0.79 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203272 kb
Host smart-66584355-9654-41f8-b649-9ed403de1871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167761910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.4167761910
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2391522817
Short name T99
Test name
Test status
Simulation time 113027863 ps
CPU time 2.47 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:19 PM PDT 24
Peak memory 203600 kb
Host smart-a0a0caa9-80d9-446e-b950-bbd33cbe4809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391522817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2391522817
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.223665108
Short name T1129
Test name
Test status
Simulation time 26349517 ps
CPU time 0.72 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:13 PM PDT 24
Peak memory 203184 kb
Host smart-0416840c-c1b8-4ce0-9e0f-47542d84125e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223665108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.223665108
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1310475570
Short name T1197
Test name
Test status
Simulation time 40250657 ps
CPU time 0.62 seconds
Started Mar 21 12:57:12 PM PDT 24
Finished Mar 21 12:57:12 PM PDT 24
Peak memory 203232 kb
Host smart-03bfce5e-b920-4a55-a3b2-6ef2431d7c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310475570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1310475570
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.912415029
Short name T1137
Test name
Test status
Simulation time 55598762 ps
CPU time 0.94 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203572 kb
Host smart-3724ea6d-9b03-43bd-a83d-83c69c6daf1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912415029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.912415029
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2359651483
Short name T88
Test name
Test status
Simulation time 115120960 ps
CPU time 2.01 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203556 kb
Host smart-631381a9-249b-408b-96f7-30836a10b57a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359651483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2359651483
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1901197852
Short name T1194
Test name
Test status
Simulation time 94644201 ps
CPU time 1.88 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203496 kb
Host smart-caa246d7-52e2-45be-91e7-989f692628ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901197852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1901197852
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3999927333
Short name T1120
Test name
Test status
Simulation time 100470765 ps
CPU time 0.73 seconds
Started Mar 21 12:57:18 PM PDT 24
Finished Mar 21 12:57:19 PM PDT 24
Peak memory 203320 kb
Host smart-d2c34901-32c0-4c32-bbba-88749b130f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999927333 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3999927333
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2226246708
Short name T1165
Test name
Test status
Simulation time 57570283 ps
CPU time 0.68 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203032 kb
Host smart-8b75f54d-57df-4298-adb9-fb7c9435e60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226246708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2226246708
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.411817866
Short name T156
Test name
Test status
Simulation time 54516650 ps
CPU time 0.67 seconds
Started Mar 21 12:57:15 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203184 kb
Host smart-076d04e3-bcef-4bfd-921b-5fd544b5ee60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411817866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.411817866
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.366383546
Short name T1122
Test name
Test status
Simulation time 31962916 ps
CPU time 0.79 seconds
Started Mar 21 12:57:17 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203320 kb
Host smart-b74d2e38-ca1e-4ddb-bd08-5fa46d91ed11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366383546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.366383546
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2681695183
Short name T1111
Test name
Test status
Simulation time 85389220 ps
CPU time 1.28 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203468 kb
Host smart-061a3c05-c106-4e54-b517-270c6683753b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681695183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2681695183
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2625235380
Short name T114
Test name
Test status
Simulation time 87548113 ps
CPU time 0.85 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203424 kb
Host smart-a2876177-5014-4d37-8680-1164303aa3df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625235380 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2625235380
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1852178575
Short name T122
Test name
Test status
Simulation time 20705746 ps
CPU time 0.65 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203228 kb
Host smart-7ce21ce0-db61-4819-b4be-c026cd4ad54b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852178575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1852178575
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2796915099
Short name T1112
Test name
Test status
Simulation time 21098596 ps
CPU time 0.74 seconds
Started Mar 21 12:57:18 PM PDT 24
Finished Mar 21 12:57:19 PM PDT 24
Peak memory 203276 kb
Host smart-14184200-5023-4b55-be7b-179773889ea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796915099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2796915099
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3715962394
Short name T1187
Test name
Test status
Simulation time 34824599 ps
CPU time 0.81 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203300 kb
Host smart-72c73931-690a-4b41-88ee-6f39ffcf3653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715962394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3715962394
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1457127706
Short name T1181
Test name
Test status
Simulation time 545610291 ps
CPU time 2.38 seconds
Started Mar 21 12:57:15 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203580 kb
Host smart-d9fb69ce-fbd5-4ea1-8bc9-b402cc979a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457127706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1457127706
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.281807143
Short name T213
Test name
Test status
Simulation time 169332574 ps
CPU time 1.32 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203460 kb
Host smart-6240314e-826b-47ca-b6f8-5a25593cf91c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281807143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.281807143
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4223901160
Short name T1176
Test name
Test status
Simulation time 31950234 ps
CPU time 0.88 seconds
Started Mar 21 12:57:19 PM PDT 24
Finished Mar 21 12:57:20 PM PDT 24
Peak memory 203348 kb
Host smart-2d24ecb4-7086-40a2-86da-3456dea3a4a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223901160 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.4223901160
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1044690278
Short name T135
Test name
Test status
Simulation time 17330196 ps
CPU time 0.66 seconds
Started Mar 21 12:57:18 PM PDT 24
Finished Mar 21 12:57:19 PM PDT 24
Peak memory 203176 kb
Host smart-fddd3691-8fac-43b7-ba58-5c08b59a83bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044690278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1044690278
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.859930013
Short name T1115
Test name
Test status
Simulation time 29369515 ps
CPU time 0.64 seconds
Started Mar 21 12:57:17 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203288 kb
Host smart-5e3bfc26-c485-42da-8db3-416a88a11084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859930013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.859930013
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3950632066
Short name T129
Test name
Test status
Simulation time 69393217 ps
CPU time 0.8 seconds
Started Mar 21 12:57:15 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203272 kb
Host smart-1f775221-7493-40be-861f-043ba6068e58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950632066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3950632066
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.170799902
Short name T86
Test name
Test status
Simulation time 289907167 ps
CPU time 1.54 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 203608 kb
Host smart-dac01ad9-7152-4643-8d1d-aba48614e97b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170799902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.170799902
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2136851500
Short name T95
Test name
Test status
Simulation time 291743995 ps
CPU time 1.38 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 203596 kb
Host smart-6653db7f-e57f-499a-8cca-2152d98438da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136851500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2136851500
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1373633577
Short name T1179
Test name
Test status
Simulation time 43557351 ps
CPU time 0.88 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 203428 kb
Host smart-a9b9e89d-47a7-44f5-be35-6d978814547a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373633577 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1373633577
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2298050192
Short name T1143
Test name
Test status
Simulation time 28044231 ps
CPU time 0.76 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 202764 kb
Host smart-9e80c50f-f2b1-452a-9130-d9abcbcc9983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298050192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2298050192
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1408424473
Short name T155
Test name
Test status
Simulation time 48277725 ps
CPU time 0.68 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203212 kb
Host smart-036f0dc7-8899-450c-a931-bdcddde25a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408424473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1408424473
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2734792151
Short name T1166
Test name
Test status
Simulation time 287556282 ps
CPU time 1.03 seconds
Started Mar 21 12:57:14 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203572 kb
Host smart-3ce66d58-52d7-4307-82a1-3346b7a14bc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734792151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2734792151
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3444423700
Short name T1110
Test name
Test status
Simulation time 704220618 ps
CPU time 3 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203516 kb
Host smart-28c4b4bf-526d-414f-9442-102da02ac9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444423700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3444423700
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2861334985
Short name T1177
Test name
Test status
Simulation time 483489242 ps
CPU time 1.34 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203492 kb
Host smart-d2e71303-bd94-4d3e-a5cd-e61a89a56556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861334985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2861334985
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.150208098
Short name T1158
Test name
Test status
Simulation time 28627861 ps
CPU time 1.13 seconds
Started Mar 21 12:57:15 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 203644 kb
Host smart-51bb9d11-8d00-43bb-a032-c5dc9442db09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150208098 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.150208098
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2518760603
Short name T125
Test name
Test status
Simulation time 45073637 ps
CPU time 0.75 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203164 kb
Host smart-5cb50379-35f3-420d-a74a-217225123528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518760603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2518760603
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2267753269
Short name T1108
Test name
Test status
Simulation time 17451680 ps
CPU time 0.72 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203292 kb
Host smart-163a28b9-0b78-4815-8402-cb8d6dc786fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267753269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2267753269
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4107601268
Short name T1164
Test name
Test status
Simulation time 217455951 ps
CPU time 0.85 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 203364 kb
Host smart-9a3eb169-9418-4598-b56d-2aaa9264667f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107601268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.4107601268
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1009121524
Short name T1099
Test name
Test status
Simulation time 38410341 ps
CPU time 1.69 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 203624 kb
Host smart-c06aee88-fe40-4ce1-a05c-285eb8860496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009121524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1009121524
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.938925547
Short name T1138
Test name
Test status
Simulation time 133030296 ps
CPU time 1.37 seconds
Started Mar 21 12:57:16 PM PDT 24
Finished Mar 21 12:57:18 PM PDT 24
Peak memory 203528 kb
Host smart-ba4519cd-4978-491c-b15a-1d2f18e18c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938925547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.938925547
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1687877294
Short name T123
Test name
Test status
Simulation time 63358072 ps
CPU time 1.67 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:58 PM PDT 24
Peak memory 203564 kb
Host smart-b2220f3f-0dea-41ce-9378-62471ff60a4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687877294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1687877294
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2882216535
Short name T1151
Test name
Test status
Simulation time 715974983 ps
CPU time 2.74 seconds
Started Mar 21 12:56:55 PM PDT 24
Finished Mar 21 12:56:58 PM PDT 24
Peak memory 203404 kb
Host smart-5ac22076-4d37-400e-b8f0-f3fc6f66b65d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882216535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2882216535
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2497486531
Short name T61
Test name
Test status
Simulation time 18185260 ps
CPU time 0.7 seconds
Started Mar 21 12:57:01 PM PDT 24
Finished Mar 21 12:57:01 PM PDT 24
Peak memory 202692 kb
Host smart-de159a17-9438-4545-a0e2-16909b05e560
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497486531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2497486531
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1227821194
Short name T1135
Test name
Test status
Simulation time 61212811 ps
CPU time 1.48 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203668 kb
Host smart-8fcbf093-c7f3-4c7a-a834-72acc377eba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227821194 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1227821194
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2975467198
Short name T126
Test name
Test status
Simulation time 21784934 ps
CPU time 0.69 seconds
Started Mar 21 12:56:54 PM PDT 24
Finished Mar 21 12:56:55 PM PDT 24
Peak memory 202732 kb
Host smart-b64e7b7d-07e3-469f-867d-3443ae2118b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975467198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2975467198
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1761597853
Short name T1167
Test name
Test status
Simulation time 39076203 ps
CPU time 0.65 seconds
Started Mar 21 12:56:57 PM PDT 24
Finished Mar 21 12:56:58 PM PDT 24
Peak memory 203256 kb
Host smart-7e7f50e2-e2f7-4e61-89ed-bd3311b9c2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761597853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1761597853
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3875267976
Short name T62
Test name
Test status
Simulation time 171135516 ps
CPU time 0.96 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203444 kb
Host smart-944cb764-d289-4ccd-8194-2dbd10eee0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875267976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3875267976
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2543452697
Short name T76
Test name
Test status
Simulation time 101840191 ps
CPU time 1.73 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:58 PM PDT 24
Peak memory 203620 kb
Host smart-4c7435df-1ca8-4729-adfb-cdfcb191e0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543452697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2543452697
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1095583319
Short name T1107
Test name
Test status
Simulation time 28139386 ps
CPU time 0.67 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 203220 kb
Host smart-99e6e40c-0344-497e-9c58-39bf6639435a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095583319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1095583319
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2513390131
Short name T1195
Test name
Test status
Simulation time 33617045 ps
CPU time 0.64 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203360 kb
Host smart-f388dff6-26c8-4e31-804d-ad9513e7cca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513390131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2513390131
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.199835310
Short name T1126
Test name
Test status
Simulation time 17945167 ps
CPU time 0.69 seconds
Started Mar 21 12:57:22 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203236 kb
Host smart-79d71952-5179-472a-bebb-216bcaf6047d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199835310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.199835310
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2792834564
Short name T1121
Test name
Test status
Simulation time 21220169 ps
CPU time 0.66 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203232 kb
Host smart-caeb8998-35a2-4df4-a104-b05f8d1dee1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792834564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2792834564
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2487432709
Short name T1159
Test name
Test status
Simulation time 52019631 ps
CPU time 0.66 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203232 kb
Host smart-83099078-9412-423d-82d9-e027eec736b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487432709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2487432709
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1758586871
Short name T1146
Test name
Test status
Simulation time 18333282 ps
CPU time 0.73 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203216 kb
Host smart-05d41971-3b06-4f23-8dd5-a410371a6e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758586871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1758586871
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1398620383
Short name T1104
Test name
Test status
Simulation time 52809827 ps
CPU time 0.65 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203284 kb
Host smart-f33fed2c-e9e7-4b92-97f8-443dbb64319b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398620383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1398620383
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.37337840
Short name T1116
Test name
Test status
Simulation time 51449082 ps
CPU time 0.62 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 202368 kb
Host smart-7db377c9-cb7d-4ede-9bf0-227bd564a735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.37337840
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2456930477
Short name T1098
Test name
Test status
Simulation time 72777387 ps
CPU time 0.69 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203212 kb
Host smart-c20d84fe-3d71-4373-ba21-ea8d6b16e2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456930477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2456930477
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3970190596
Short name T1092
Test name
Test status
Simulation time 18331158 ps
CPU time 0.6 seconds
Started Mar 21 12:57:22 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 202336 kb
Host smart-59a44cfd-d62b-42ac-be34-c53be7622d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970190596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3970190596
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3538455706
Short name T117
Test name
Test status
Simulation time 275586356 ps
CPU time 1.48 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203392 kb
Host smart-26cbb9f1-242b-4bd1-afc7-61c37202f513
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538455706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3538455706
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2753194006
Short name T1096
Test name
Test status
Simulation time 113475939 ps
CPU time 4.41 seconds
Started Mar 21 12:57:02 PM PDT 24
Finished Mar 21 12:57:07 PM PDT 24
Peak memory 203456 kb
Host smart-1ed2278b-e1dd-450f-ae75-55405d5b61bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753194006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2753194006
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3751757894
Short name T1100
Test name
Test status
Simulation time 25106302 ps
CPU time 0.71 seconds
Started Mar 21 12:57:09 PM PDT 24
Finished Mar 21 12:57:09 PM PDT 24
Peak memory 202840 kb
Host smart-f6fff86b-02d9-4c2d-8380-365f3905398f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751757894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3751757894
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3224212426
Short name T137
Test name
Test status
Simulation time 402187217 ps
CPU time 0.93 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203368 kb
Host smart-f5c1cea9-584d-45d7-ad00-605e9532c3ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224212426 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3224212426
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3491181920
Short name T1189
Test name
Test status
Simulation time 60413582 ps
CPU time 0.72 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 202608 kb
Host smart-abbcdab3-de8e-4740-97d3-4cb5209b62ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491181920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3491181920
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1165596676
Short name T154
Test name
Test status
Simulation time 30907167 ps
CPU time 0.68 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:07 PM PDT 24
Peak memory 203188 kb
Host smart-2517bebd-db7d-4386-a99e-12dca21fa49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165596676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1165596676
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1355761946
Short name T130
Test name
Test status
Simulation time 64545964 ps
CPU time 1.14 seconds
Started Mar 21 12:57:01 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 203608 kb
Host smart-99b9bb27-a8dc-4a5b-bc82-fdd34f99926b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355761946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1355761946
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.285283558
Short name T1131
Test name
Test status
Simulation time 31519583 ps
CPU time 0.94 seconds
Started Mar 21 12:56:56 PM PDT 24
Finished Mar 21 12:56:57 PM PDT 24
Peak memory 203380 kb
Host smart-73e834f4-cdc7-4897-9872-43af5e20da70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285283558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.285283558
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2334964843
Short name T84
Test name
Test status
Simulation time 139761971 ps
CPU time 2.01 seconds
Started Mar 21 12:56:57 PM PDT 24
Finished Mar 21 12:56:59 PM PDT 24
Peak memory 203488 kb
Host smart-4109405c-7985-4283-977a-fdb04db3d08b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334964843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2334964843
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.213742094
Short name T1169
Test name
Test status
Simulation time 26550381 ps
CPU time 0.63 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203292 kb
Host smart-48301e22-a09e-4df0-9735-0894050068c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213742094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.213742094
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3553736685
Short name T1163
Test name
Test status
Simulation time 18251366 ps
CPU time 0.62 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203268 kb
Host smart-9b76f11f-faf9-498d-8481-53360b41a112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553736685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3553736685
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3533052025
Short name T1114
Test name
Test status
Simulation time 50102771 ps
CPU time 0.68 seconds
Started Mar 21 12:57:22 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203292 kb
Host smart-ec7c8a06-c729-456a-8d2e-4ab338e25ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533052025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3533052025
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1372318026
Short name T1119
Test name
Test status
Simulation time 17466752 ps
CPU time 0.67 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203280 kb
Host smart-6d7319f8-efd5-4866-bc62-879cc555a9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372318026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1372318026
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2203806978
Short name T1150
Test name
Test status
Simulation time 15753320 ps
CPU time 0.68 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203284 kb
Host smart-eac21f4a-857b-4962-af2d-f98c3209885f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203806978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2203806978
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2098525233
Short name T1130
Test name
Test status
Simulation time 41896750 ps
CPU time 0.65 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203260 kb
Host smart-796aba84-295e-4f88-b35c-fdf572d09c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098525233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2098525233
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3717450179
Short name T1136
Test name
Test status
Simulation time 55967603 ps
CPU time 0.64 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203152 kb
Host smart-29a8c665-4ab1-40cf-9a0e-1a5a8e4d8696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717450179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3717450179
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2047367741
Short name T1141
Test name
Test status
Simulation time 19577032 ps
CPU time 0.67 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203236 kb
Host smart-90650b34-0ee8-4f66-8311-e408f94a9ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047367741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2047367741
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3242561458
Short name T1132
Test name
Test status
Simulation time 25723903 ps
CPU time 0.62 seconds
Started Mar 21 12:57:20 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 203216 kb
Host smart-781384f3-ac4b-44b1-9556-b767a75435a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242561458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3242561458
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1617127506
Short name T1095
Test name
Test status
Simulation time 29428803 ps
CPU time 1.09 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 203436 kb
Host smart-ef6ac79f-d978-46de-ba61-a784f9a082c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617127506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1617127506
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4032862118
Short name T1145
Test name
Test status
Simulation time 117638923 ps
CPU time 4.28 seconds
Started Mar 21 12:57:01 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203488 kb
Host smart-2d804b19-bdf2-411d-bc1b-79a5fa3525d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032862118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4032862118
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.630685821
Short name T1101
Test name
Test status
Simulation time 17500297 ps
CPU time 0.67 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 202464 kb
Host smart-7f0f6c70-9859-40f0-ba77-009d61aef4ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630685821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.630685821
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3521995096
Short name T1144
Test name
Test status
Simulation time 339012412 ps
CPU time 0.96 seconds
Started Mar 21 12:57:09 PM PDT 24
Finished Mar 21 12:57:10 PM PDT 24
Peak memory 203352 kb
Host smart-2cd1b581-6775-4835-88de-bff074af0eca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521995096 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3521995096
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1497318358
Short name T1192
Test name
Test status
Simulation time 72659198 ps
CPU time 0.79 seconds
Started Mar 21 12:57:00 PM PDT 24
Finished Mar 21 12:57:01 PM PDT 24
Peak memory 203192 kb
Host smart-48afa5c6-e065-402b-9622-216b2773214d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497318358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1497318358
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3088150372
Short name T1186
Test name
Test status
Simulation time 27366275 ps
CPU time 0.62 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 203220 kb
Host smart-557f1972-f80d-4360-93bb-944a963fbec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088150372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3088150372
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4237216619
Short name T1154
Test name
Test status
Simulation time 75034475 ps
CPU time 0.85 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 203208 kb
Host smart-d3ae19ec-9639-4c6c-b48a-6ceb639d281c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237216619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.4237216619
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1866186493
Short name T1161
Test name
Test status
Simulation time 44427950 ps
CPU time 1.24 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203548 kb
Host smart-fa7d7744-76b1-4055-b09c-e6bac30218f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866186493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1866186493
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1876016296
Short name T215
Test name
Test status
Simulation time 233581978 ps
CPU time 1.37 seconds
Started Mar 21 12:57:00 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 203536 kb
Host smart-8864ad59-43c1-4623-88c6-56a3022fa0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876016296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1876016296
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4179905301
Short name T1193
Test name
Test status
Simulation time 15979927 ps
CPU time 0.63 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203152 kb
Host smart-b2f4a66b-2cb9-4ccd-b91f-e4ab91e5cab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179905301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4179905301
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2963084675
Short name T1153
Test name
Test status
Simulation time 24094131 ps
CPU time 0.63 seconds
Started Mar 21 12:57:22 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203300 kb
Host smart-c0193742-bfb8-4733-be22-f45896849a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963084675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2963084675
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1101014007
Short name T1162
Test name
Test status
Simulation time 17206688 ps
CPU time 0.66 seconds
Started Mar 21 12:57:24 PM PDT 24
Finished Mar 21 12:57:25 PM PDT 24
Peak memory 203228 kb
Host smart-8a98bc43-db0f-4baf-a8d7-d0add4519499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101014007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1101014007
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2899207189
Short name T1152
Test name
Test status
Simulation time 19039002 ps
CPU time 0.7 seconds
Started Mar 21 12:57:31 PM PDT 24
Finished Mar 21 12:57:32 PM PDT 24
Peak memory 203272 kb
Host smart-9ba699a7-c7d4-48d4-a2fe-7b92fe2663d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899207189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2899207189
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.578930772
Short name T229
Test name
Test status
Simulation time 43584201 ps
CPU time 0.7 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:22 PM PDT 24
Peak memory 203280 kb
Host smart-e91fd1b6-96d6-4b82-ab10-c76f4bb048bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578930772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.578930772
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1932713963
Short name T230
Test name
Test status
Simulation time 36836972 ps
CPU time 0.68 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 203216 kb
Host smart-03fa7930-87ce-4770-b6d1-e18c0ddeac64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932713963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1932713963
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.868593779
Short name T1118
Test name
Test status
Simulation time 18281321 ps
CPU time 0.69 seconds
Started Mar 21 12:57:21 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203244 kb
Host smart-1cd00a78-948e-407d-8128-522ac67d3e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868593779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.868593779
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1605144372
Short name T1171
Test name
Test status
Simulation time 15326330 ps
CPU time 0.63 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:24 PM PDT 24
Peak memory 202448 kb
Host smart-f59b53c2-2ab0-400b-8378-10f512c425f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605144372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1605144372
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2018485827
Short name T1149
Test name
Test status
Simulation time 35492043 ps
CPU time 0.64 seconds
Started Mar 21 12:57:23 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203192 kb
Host smart-eb8afe1e-46be-4295-857a-798307ca54ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018485827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2018485827
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1443795728
Short name T1091
Test name
Test status
Simulation time 16743916 ps
CPU time 0.68 seconds
Started Mar 21 12:57:22 PM PDT 24
Finished Mar 21 12:57:23 PM PDT 24
Peak memory 203200 kb
Host smart-150e5da1-5596-48d3-b192-014c6a02b372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443795728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1443795728
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.432955216
Short name T1105
Test name
Test status
Simulation time 132729219 ps
CPU time 0.96 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:07 PM PDT 24
Peak memory 203484 kb
Host smart-40a096a0-4084-4666-b8e1-f3870ce7b6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432955216 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.432955216
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2461644291
Short name T118
Test name
Test status
Simulation time 141215290 ps
CPU time 0.69 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 202760 kb
Host smart-d22af4bc-a465-408f-8599-825ad452d670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461644291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2461644291
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.4008386620
Short name T1097
Test name
Test status
Simulation time 48926726 ps
CPU time 0.65 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 203336 kb
Host smart-36a88f12-7e66-4b27-8f40-87fcd5a72001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008386620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.4008386620
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1921863122
Short name T132
Test name
Test status
Simulation time 133898745 ps
CPU time 0.82 seconds
Started Mar 21 12:57:01 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 203244 kb
Host smart-bfcae0eb-4088-4c06-9314-8a15cb8cf9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921863122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1921863122
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1903336554
Short name T87
Test name
Test status
Simulation time 49741990 ps
CPU time 2.19 seconds
Started Mar 21 12:57:02 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 203568 kb
Host smart-976cf187-df2c-4582-818b-d889c090f440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903336554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1903336554
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.664983630
Short name T97
Test name
Test status
Simulation time 348214443 ps
CPU time 1.27 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 203456 kb
Host smart-d7a1f70c-5d45-4a03-abff-d9fb3d7d7c46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664983630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.664983630
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3401131400
Short name T1134
Test name
Test status
Simulation time 86501662 ps
CPU time 1.39 seconds
Started Mar 21 12:57:02 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 203568 kb
Host smart-8f357c94-43f9-453c-96e4-e98636745987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401131400 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3401131400
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.212577179
Short name T119
Test name
Test status
Simulation time 16469097 ps
CPU time 0.67 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 202908 kb
Host smart-59d7e3b7-51a3-4f53-896b-cb81c46d2143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212577179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.212577179
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1639225118
Short name T1148
Test name
Test status
Simulation time 44484869 ps
CPU time 0.64 seconds
Started Mar 21 12:57:03 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 203296 kb
Host smart-be3b13cc-768f-45ae-90b3-f3954a2e152d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639225118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1639225118
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2783483887
Short name T133
Test name
Test status
Simulation time 78211840 ps
CPU time 0.94 seconds
Started Mar 21 12:57:02 PM PDT 24
Finished Mar 21 12:57:03 PM PDT 24
Peak memory 203272 kb
Host smart-f0b30d02-0f39-46b3-b5f7-1fab78616fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783483887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2783483887
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1475582569
Short name T1139
Test name
Test status
Simulation time 910322380 ps
CPU time 2.81 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:09 PM PDT 24
Peak memory 203524 kb
Host smart-1758a185-b94f-489b-825b-91f325214c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475582569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1475582569
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2166720573
Short name T98
Test name
Test status
Simulation time 247345523 ps
CPU time 1.34 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 203480 kb
Host smart-1999dd7a-5489-4878-89ef-f974f7dfbf89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166720573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2166720573
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1519055318
Short name T180
Test name
Test status
Simulation time 25403693 ps
CPU time 0.77 seconds
Started Mar 21 12:57:03 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 203352 kb
Host smart-91ced269-ac39-4d8f-9131-a4796d29061e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519055318 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1519055318
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1033533250
Short name T1180
Test name
Test status
Simulation time 119196765 ps
CPU time 0.74 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203260 kb
Host smart-0b5991b0-2c6b-4ffd-b31c-022e2b8f2bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033533250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1033533250
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1588056967
Short name T1188
Test name
Test status
Simulation time 17917941 ps
CPU time 0.6 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:06 PM PDT 24
Peak memory 202396 kb
Host smart-70013d83-a9f1-4410-b3e1-c825c1d65a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588056967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1588056967
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4260614578
Short name T1157
Test name
Test status
Simulation time 20966429 ps
CPU time 0.76 seconds
Started Mar 21 12:57:06 PM PDT 24
Finished Mar 21 12:57:07 PM PDT 24
Peak memory 203248 kb
Host smart-a22081c9-3487-4b35-a223-9548d15fbf04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260614578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.4260614578
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1531979128
Short name T1172
Test name
Test status
Simulation time 185368739 ps
CPU time 2.23 seconds
Started Mar 21 12:57:03 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203556 kb
Host smart-89e82bef-9c40-459e-aa61-35e2d3a604cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531979128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1531979128
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.589124933
Short name T1128
Test name
Test status
Simulation time 381269467 ps
CPU time 1.36 seconds
Started Mar 21 12:57:01 PM PDT 24
Finished Mar 21 12:57:03 PM PDT 24
Peak memory 203592 kb
Host smart-5182b51f-03b1-4bcd-babd-7257918006c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589124933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.589124933
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2789826624
Short name T1191
Test name
Test status
Simulation time 98703651 ps
CPU time 0.88 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 203236 kb
Host smart-20e3276f-ab03-45a2-8069-dbc1132679c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789826624 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2789826624
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4225039809
Short name T1147
Test name
Test status
Simulation time 61936102 ps
CPU time 0.72 seconds
Started Mar 21 12:57:02 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 202868 kb
Host smart-96ecb56c-a767-4cce-9a37-28dd891b9631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225039809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.4225039809
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.972080938
Short name T1123
Test name
Test status
Simulation time 48340789 ps
CPU time 0.67 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 202588 kb
Host smart-79818ef0-fe8d-400f-a5b0-eac53e5ce8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972080938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.972080938
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1598514885
Short name T1184
Test name
Test status
Simulation time 44958084 ps
CPU time 0.82 seconds
Started Mar 21 12:57:04 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 203252 kb
Host smart-4368bda8-36b9-4dee-89bf-a56ea0ac09f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598514885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1598514885
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3971978852
Short name T1109
Test name
Test status
Simulation time 1072020038 ps
CPU time 1.98 seconds
Started Mar 21 12:57:05 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 203600 kb
Host smart-1deaac09-4d61-433b-91d7-1c1ac61b38f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971978852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3971978852
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2722818566
Short name T1102
Test name
Test status
Simulation time 488222391 ps
CPU time 2.07 seconds
Started Mar 21 12:57:07 PM PDT 24
Finished Mar 21 12:57:09 PM PDT 24
Peak memory 203532 kb
Host smart-7fed1672-d0e7-44c7-9c14-7c89dd8b008f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722818566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2722818566
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2814071605
Short name T113
Test name
Test status
Simulation time 76689106 ps
CPU time 1.05 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203444 kb
Host smart-f670ebc6-b323-495b-96ee-55d5e92353cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814071605 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2814071605
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1628335315
Short name T1142
Test name
Test status
Simulation time 118465385 ps
CPU time 0.73 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203180 kb
Host smart-59ca95ce-f9bf-4ac2-8a5c-3caeb398b181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628335315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1628335315
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1709673519
Short name T1160
Test name
Test status
Simulation time 17021037 ps
CPU time 0.63 seconds
Started Mar 21 12:57:13 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 203208 kb
Host smart-ea6afd35-ca6e-40b9-bfc1-1a866f95c001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709673519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1709673519
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1067731116
Short name T1182
Test name
Test status
Simulation time 128813242 ps
CPU time 0.8 seconds
Started Mar 21 12:57:11 PM PDT 24
Finished Mar 21 12:57:12 PM PDT 24
Peak memory 203228 kb
Host smart-9916719d-ff2e-4ea1-831e-ec7d0d260543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067731116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1067731116
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1193238815
Short name T94
Test name
Test status
Simulation time 91449713 ps
CPU time 1.47 seconds
Started Mar 21 12:57:03 PM PDT 24
Finished Mar 21 12:57:05 PM PDT 24
Peak memory 203600 kb
Host smart-3bd978f9-d913-46b5-8666-5ba30d46857a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193238815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1193238815
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1567434300
Short name T380
Test name
Test status
Simulation time 130711046 ps
CPU time 0.58 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 203032 kb
Host smart-4b489d0d-ae66-45c2-b07f-2138ea17085b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567434300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1567434300
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.272130999
Short name T346
Test name
Test status
Simulation time 80852188 ps
CPU time 1.33 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 211588 kb
Host smart-909b6b7e-8adb-4dd5-b6f9-4f66623e97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272130999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.272130999
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2065390529
Short name T931
Test name
Test status
Simulation time 440112192 ps
CPU time 4.98 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:28 PM PDT 24
Peak memory 245496 kb
Host smart-57677c45-2fa2-4e27-bdff-0dfbfc5ea552
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065390529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2065390529
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.423684625
Short name T107
Test name
Test status
Simulation time 6442609170 ps
CPU time 115.52 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:19:18 PM PDT 24
Peak memory 416872 kb
Host smart-246b205c-bee2-425f-bc70-c54df6266fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423684625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.423684625
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.4114391612
Short name T541
Test name
Test status
Simulation time 2365036210 ps
CPU time 36.09 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 415268 kb
Host smart-1cdd003c-ee21-47fb-b2e9-aaded4a7056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114391612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.4114391612
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1873934907
Short name T810
Test name
Test status
Simulation time 120550787 ps
CPU time 0.86 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:20 PM PDT 24
Peak memory 203048 kb
Host smart-ec2a41da-2a05-4910-b00d-2c2aa0577fd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873934907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1873934907
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2659282642
Short name T140
Test name
Test status
Simulation time 11555621840 ps
CPU time 63.53 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:18:26 PM PDT 24
Peak memory 805864 kb
Host smart-58789957-6b37-4301-a28a-07f5d2718b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659282642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2659282642
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.4225311676
Short name T504
Test name
Test status
Simulation time 17436382 ps
CPU time 0.65 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 202500 kb
Host smart-814553b8-7bcf-4b85-b605-74ab96c6b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225311676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4225311676
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3008812424
Short name T184
Test name
Test status
Simulation time 6484607831 ps
CPU time 1377.72 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:40:21 PM PDT 24
Peak memory 609400 kb
Host smart-ddc7b82d-b8ca-45b8-baf0-ee5aab27b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008812424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3008812424
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3000510562
Short name T855
Test name
Test status
Simulation time 15313702806 ps
CPU time 58.44 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 247236 kb
Host smart-504ad611-38aa-47f4-a06d-1e32671b6893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000510562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3000510562
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2289480908
Short name T631
Test name
Test status
Simulation time 620974964 ps
CPU time 2.93 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 203400 kb
Host smart-b8b2f913-f5b5-46d4-84fb-a83b0d20cac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289480908 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2289480908
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1486706069
Short name T409
Test name
Test status
Simulation time 10075301477 ps
CPU time 75.02 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:18:35 PM PDT 24
Peak memory 607232 kb
Host smart-11e2d0eb-c470-4188-ae4a-b832bed9f075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486706069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1486706069
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.4234573040
Short name T1036
Test name
Test status
Simulation time 10031433445 ps
CPU time 88.66 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 734096 kb
Host smart-b7bbfc24-9412-4e12-b61f-bb47ae0b4a66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234573040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.4234573040
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1161498741
Short name T212
Test name
Test status
Simulation time 1545968467 ps
CPU time 2.48 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 203312 kb
Host smart-98972c6e-adc8-4314-aca1-b8ff4aa3cae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161498741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1161498741
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3695577641
Short name T269
Test name
Test status
Simulation time 3436915985 ps
CPU time 4.52 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:32 PM PDT 24
Peak memory 208816 kb
Host smart-5bdfddd3-fdf7-45b7-98f5-fa65186d1b18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695577641 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3695577641
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4162035791
Short name T768
Test name
Test status
Simulation time 1347097469 ps
CPU time 17.11 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:36 PM PDT 24
Peak memory 203284 kb
Host smart-b733a232-b73a-46d9-89f3-8674309e9b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162035791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4162035791
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1570118555
Short name T348
Test name
Test status
Simulation time 3781992346 ps
CPU time 14.2 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:35 PM PDT 24
Peak memory 213160 kb
Host smart-e2d0e5b0-ad4b-4e07-8dbe-7f4f203aee67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570118555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1570118555
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3258345731
Short name T7
Test name
Test status
Simulation time 4682414775 ps
CPU time 6.34 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:29 PM PDT 24
Peak memory 211692 kb
Host smart-c375f60e-3a51-4e6d-941f-5821b14cd365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258345731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3258345731
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2090479852
Short name T513
Test name
Test status
Simulation time 22230671 ps
CPU time 0.62 seconds
Started Mar 21 01:17:36 PM PDT 24
Finished Mar 21 01:17:37 PM PDT 24
Peak memory 203032 kb
Host smart-ac81d225-56f4-481e-8509-29629fda589f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090479852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2090479852
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3240342742
Short name T424
Test name
Test status
Simulation time 44163665 ps
CPU time 1.31 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:17:27 PM PDT 24
Peak memory 211352 kb
Host smart-92db3ed8-7c07-4319-aa93-49e8e5d3560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240342742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3240342742
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2709281552
Short name T26
Test name
Test status
Simulation time 1481696258 ps
CPU time 5.93 seconds
Started Mar 21 01:17:24 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 247852 kb
Host smart-717f7ba6-44c2-40ab-a84e-161ab7b07be9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709281552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2709281552
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1294558109
Short name T531
Test name
Test status
Simulation time 7695600026 ps
CPU time 125.38 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:19:28 PM PDT 24
Peak memory 607536 kb
Host smart-ad6dce10-0d94-477e-9f66-917a7bb17e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294558109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1294558109
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3249344887
Short name T421
Test name
Test status
Simulation time 2125003626 ps
CPU time 68.44 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 461776 kb
Host smart-5c79a94a-80e1-437d-96b2-152873f3baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249344887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3249344887
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3105389719
Short name T751
Test name
Test status
Simulation time 1498609922 ps
CPU time 1.14 seconds
Started Mar 21 01:17:30 PM PDT 24
Finished Mar 21 01:17:32 PM PDT 24
Peak memory 203248 kb
Host smart-a27479f4-2323-4315-9494-443b35072be4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105389719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3105389719
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3215857471
Short name T188
Test name
Test status
Simulation time 408588124 ps
CPU time 6.25 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 219608 kb
Host smart-4478b273-3494-4813-a945-61e641fa0777
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215857471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3215857471
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.48469106
Short name T144
Test name
Test status
Simulation time 3791194209 ps
CPU time 94.43 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:18:58 PM PDT 24
Peak memory 1088120 kb
Host smart-8cb505c9-be72-4c15-9e94-55f2ba3f086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48469106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.48469106
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.720582722
Short name T906
Test name
Test status
Simulation time 16572657 ps
CPU time 0.65 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202416 kb
Host smart-47cc5628-913f-4e4d-9047-dd03be458ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720582722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.720582722
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.485307858
Short name T37
Test name
Test status
Simulation time 30735980335 ps
CPU time 141.46 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:19:47 PM PDT 24
Peak memory 203160 kb
Host smart-9da5b1c1-7efb-4f6f-930a-fc1009436040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485307858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.485307858
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2467426858
Short name T384
Test name
Test status
Simulation time 3134855968 ps
CPU time 147.24 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 316596 kb
Host smart-98687860-5f9d-4f04-951c-48f60c812ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467426858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2467426858
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2419228469
Short name T82
Test name
Test status
Simulation time 139581591 ps
CPU time 0.81 seconds
Started Mar 21 01:17:33 PM PDT 24
Finished Mar 21 01:17:34 PM PDT 24
Peak memory 220132 kb
Host smart-daa05190-bd58-4a11-8ce4-2dc9ec4dbfe3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419228469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2419228469
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.476748383
Short name T953
Test name
Test status
Simulation time 4276583696 ps
CPU time 3.12 seconds
Started Mar 21 01:17:34 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 203468 kb
Host smart-c60c1287-cb0b-4abe-bbbf-40885f3c6c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476748383 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.476748383
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1766885715
Short name T943
Test name
Test status
Simulation time 10179320565 ps
CPU time 28.59 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 370040 kb
Host smart-8f1cd45b-2594-497e-8104-ee933b43a75c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766885715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1766885715
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.634738632
Short name T708
Test name
Test status
Simulation time 10130434960 ps
CPU time 89.41 seconds
Started Mar 21 01:17:26 PM PDT 24
Finished Mar 21 01:18:56 PM PDT 24
Peak memory 675632 kb
Host smart-04d65167-c1a5-4b41-b76c-0c665b498cff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634738632 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.634738632
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.4023676834
Short name T287
Test name
Test status
Simulation time 329572382 ps
CPU time 2 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:17:41 PM PDT 24
Peak memory 203328 kb
Host smart-c02383fa-0ee4-40cb-af79-dec5c0831803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023676834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.4023676834
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1038366746
Short name T799
Test name
Test status
Simulation time 7368767423 ps
CPU time 7.62 seconds
Started Mar 21 01:17:33 PM PDT 24
Finished Mar 21 01:17:41 PM PDT 24
Peak memory 219540 kb
Host smart-879f5a14-7a9c-4672-8f24-ec868456bff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038366746 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1038366746
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3483064619
Short name T1051
Test name
Test status
Simulation time 869025493 ps
CPU time 32.35 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 203388 kb
Host smart-27c25011-e2a2-420a-8736-689cf11a48f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483064619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3483064619
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.273261209
Short name T535
Test name
Test status
Simulation time 1331454582 ps
CPU time 11.32 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:39 PM PDT 24
Peak memory 205000 kb
Host smart-b9b910c2-5692-458b-bc78-21df9edf97b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273261209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.273261209
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1431135211
Short name T149
Test name
Test status
Simulation time 44578566728 ps
CPU time 230.58 seconds
Started Mar 21 01:17:27 PM PDT 24
Finished Mar 21 01:21:18 PM PDT 24
Peak memory 1933820 kb
Host smart-c68945a5-aa49-4e31-ab74-2a0f24ff98df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431135211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1431135211
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.254089834
Short name T681
Test name
Test status
Simulation time 4869305113 ps
CPU time 7.73 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:35 PM PDT 24
Peak memory 218616 kb
Host smart-c860a408-1f39-44db-9c08-09a4f993195b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254089834 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.254089834
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.1231732440
Short name T850
Test name
Test status
Simulation time 689966161 ps
CPU time 3.95 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:17:42 PM PDT 24
Peak memory 203660 kb
Host smart-be9d1ccb-012e-4aa0-a9f4-85d6b6c73a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231732440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.1231732440
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.4206682068
Short name T888
Test name
Test status
Simulation time 56428345 ps
CPU time 0.63 seconds
Started Mar 21 01:18:07 PM PDT 24
Finished Mar 21 01:18:09 PM PDT 24
Peak memory 203032 kb
Host smart-1e6a48be-1fc9-41c1-a222-75cfa7de669d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206682068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.4206682068
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.268530209
Short name T735
Test name
Test status
Simulation time 34497873 ps
CPU time 1.13 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:10 PM PDT 24
Peak memory 203232 kb
Host smart-c39f3e74-22e8-45e3-8c23-1f242986ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268530209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.268530209
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2424815143
Short name T427
Test name
Test status
Simulation time 686705750 ps
CPU time 3.12 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 222788 kb
Host smart-2790aba7-55f6-4826-a60c-fb9ef8e3b09d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424815143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2424815143
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3146471577
Short name T439
Test name
Test status
Simulation time 7623361925 ps
CPU time 122.95 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 594140 kb
Host smart-51380c3e-eb78-4bf4-b04a-ff2099ce78be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146471577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3146471577
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1098335439
Short name T605
Test name
Test status
Simulation time 1314754045 ps
CPU time 89.45 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 515776 kb
Host smart-ee112c5c-2f20-41fc-813d-381fcc4f8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098335439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1098335439
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.986055628
Short name T633
Test name
Test status
Simulation time 327676121 ps
CPU time 3.73 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:07 PM PDT 24
Peak memory 203200 kb
Host smart-b9b56324-c6ed-47f7-9285-1dee5f86c0d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986055628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
986055628
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3304471788
Short name T716
Test name
Test status
Simulation time 67806524019 ps
CPU time 83.65 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:19:23 PM PDT 24
Peak memory 1047976 kb
Host smart-22783593-870f-40a1-b8ac-af134fd06934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304471788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3304471788
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_override.3545700946
Short name T812
Test name
Test status
Simulation time 56066752 ps
CPU time 0.67 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 202460 kb
Host smart-04bd1520-b6c9-42c8-b79d-3956769bbfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545700946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3545700946
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3642297176
Short name T305
Test name
Test status
Simulation time 811295631 ps
CPU time 3.38 seconds
Started Mar 21 01:18:17 PM PDT 24
Finished Mar 21 01:18:20 PM PDT 24
Peak memory 211564 kb
Host smart-231ca897-c7de-4bdf-8aa6-daac4ad23d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642297176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3642297176
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3948885055
Short name T381
Test name
Test status
Simulation time 5680963849 ps
CPU time 44.73 seconds
Started Mar 21 01:18:13 PM PDT 24
Finished Mar 21 01:18:58 PM PDT 24
Peak memory 300024 kb
Host smart-17e5cf7d-2541-448f-8cb4-d3ac2240ebae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948885055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3948885055
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1927462822
Short name T836
Test name
Test status
Simulation time 4186722789 ps
CPU time 2.65 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 203456 kb
Host smart-beb70b7d-b7de-468b-ab8b-4704ac6e14c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927462822 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1927462822
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3500336278
Short name T579
Test name
Test status
Simulation time 10157232310 ps
CPU time 38.37 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 466368 kb
Host smart-d7a71f23-e00c-4430-8e62-e16843fcda8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500336278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3500336278
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2230535581
Short name T382
Test name
Test status
Simulation time 1114794577 ps
CPU time 4.63 seconds
Started Mar 21 01:18:18 PM PDT 24
Finished Mar 21 01:18:24 PM PDT 24
Peak memory 203328 kb
Host smart-48812524-59aa-4fc3-999e-db0f59cc59c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230535581 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2230535581
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.829891263
Short name T333
Test name
Test status
Simulation time 1452616074 ps
CPU time 19.79 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:18:32 PM PDT 24
Peak memory 203344 kb
Host smart-91e6edc6-e77b-446d-9d52-964895ce2d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829891263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.829891263
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.717677062
Short name T1025
Test name
Test status
Simulation time 1565777578 ps
CPU time 25.26 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:34 PM PDT 24
Peak memory 217816 kb
Host smart-8a6409f9-ae4f-4da4-b916-26a4681bea88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717677062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.717677062
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2951512757
Short name T1015
Test name
Test status
Simulation time 23474268223 ps
CPU time 1428.02 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:42:00 PM PDT 24
Peak memory 5213544 kb
Host smart-98216d04-9c79-47e5-9e01-2f88878690b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951512757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2951512757
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_alert_test.29078637
Short name T448
Test name
Test status
Simulation time 15851230 ps
CPU time 0.62 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 203104 kb
Host smart-2b6eb7f6-9c46-4357-bdef-6d53575e0693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.29078637
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1025514361
Short name T344
Test name
Test status
Simulation time 57461580 ps
CPU time 1.49 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 216216 kb
Host smart-67fa4693-c9c1-4318-9d4d-cab1d0a2115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025514361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1025514361
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1143904866
Short name T712
Test name
Test status
Simulation time 1105830984 ps
CPU time 15 seconds
Started Mar 21 01:18:15 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 263004 kb
Host smart-fe5feb97-d7f3-4e8b-86cc-4918e732ddee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143904866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1143904866
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1169180882
Short name T363
Test name
Test status
Simulation time 3294682354 ps
CPU time 101.42 seconds
Started Mar 21 01:18:09 PM PDT 24
Finished Mar 21 01:19:51 PM PDT 24
Peak memory 536276 kb
Host smart-4d141740-97a7-4810-86f7-3e75c9229b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169180882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1169180882
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1922428499
Short name T815
Test name
Test status
Simulation time 9318682876 ps
CPU time 74.13 seconds
Started Mar 21 01:18:07 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 715316 kb
Host smart-1cdab13c-7378-4a84-a364-204a35f95ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922428499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1922428499
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2417740676
Short name T947
Test name
Test status
Simulation time 323706239 ps
CPU time 0.9 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203160 kb
Host smart-f0e8138a-1c89-41a3-8900-0b6435535375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417740676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2417740676
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2830042002
Short name T911
Test name
Test status
Simulation time 174289150 ps
CPU time 8.44 seconds
Started Mar 21 01:18:07 PM PDT 24
Finished Mar 21 01:18:17 PM PDT 24
Peak memory 226056 kb
Host smart-0429f8d3-1323-4127-8ce5-e9e92b40aab2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830042002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2830042002
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1336954131
Short name T824
Test name
Test status
Simulation time 32600864632 ps
CPU time 262.55 seconds
Started Mar 21 01:18:13 PM PDT 24
Finished Mar 21 01:22:36 PM PDT 24
Peak memory 1073784 kb
Host smart-6fd5463b-59b7-4dcd-8b73-98ab4fb1dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336954131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1336954131
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_override.75689412
Short name T805
Test name
Test status
Simulation time 72888363 ps
CPU time 0.63 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 202456 kb
Host smart-71c06bac-6111-4d37-aaf0-887a8503ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75689412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.75689412
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3361154952
Short name T677
Test name
Test status
Simulation time 1557479394 ps
CPU time 8.57 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:18 PM PDT 24
Peak memory 203216 kb
Host smart-7a5a9b21-0dbe-46ed-91a5-3e8c3fdef949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361154952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3361154952
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3683183614
Short name T151
Test name
Test status
Simulation time 2997080948 ps
CPU time 99.62 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:19:52 PM PDT 24
Peak memory 276680 kb
Host smart-27ebb0e3-2eaa-4be2-9a5d-60f10f0f3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683183614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3683183614
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3313805824
Short name T739
Test name
Test status
Simulation time 646846182 ps
CPU time 3.17 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 203332 kb
Host smart-7708c64e-d3ee-4d4e-aaa1-111071792d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313805824 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3313805824
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1448159283
Short name T483
Test name
Test status
Simulation time 10101759034 ps
CPU time 85.37 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 712888 kb
Host smart-91808cd3-9a36-4831-9749-8cdc3eb7eb35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448159283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1448159283
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2926614399
Short name T795
Test name
Test status
Simulation time 4659177406 ps
CPU time 2.09 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:18:28 PM PDT 24
Peak memory 203464 kb
Host smart-c1b0b6c5-94d0-4554-a9f6-4bbf9ab05238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926614399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2926614399
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2804324819
Short name T702
Test name
Test status
Simulation time 1537876188 ps
CPU time 3.83 seconds
Started Mar 21 01:18:17 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 203388 kb
Host smart-c0d0f16c-14b0-4e28-a784-b0ba76f7f960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804324819 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2804324819
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2253673112
Short name T249
Test name
Test status
Simulation time 1327991673 ps
CPU time 16.64 seconds
Started Mar 21 01:18:04 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 203316 kb
Host smart-60bf25c4-85dd-4b99-bb84-124ce77a6f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253673112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2253673112
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1935324299
Short name T161
Test name
Test status
Simulation time 1187602501 ps
CPU time 21.99 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:18:53 PM PDT 24
Peak memory 216704 kb
Host smart-391b356e-a9ff-4d48-b88b-d7444c43673b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935324299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1935324299
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.73903749
Short name T423
Test name
Test status
Simulation time 16523830174 ps
CPU time 91.91 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 1043680 kb
Host smart-15e13cb3-4644-4da7-b9c2-18a60766bac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73903749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_stretch.73903749
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.28585022
Short name T663
Test name
Test status
Simulation time 2473110357 ps
CPU time 6.66 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:18:17 PM PDT 24
Peak memory 211688 kb
Host smart-31da7693-243e-400b-9eba-82997d98cb9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585022 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_timeout.28585022
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.14536083
Short name T916
Test name
Test status
Simulation time 16290541 ps
CPU time 0.62 seconds
Started Mar 21 01:18:28 PM PDT 24
Finished Mar 21 01:18:29 PM PDT 24
Peak memory 203132 kb
Host smart-9d76d486-2dcc-4244-b795-19a36b1ce2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.14536083
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.4036483337
Short name T1064
Test name
Test status
Simulation time 43284389 ps
CPU time 1.2 seconds
Started Mar 21 01:18:18 PM PDT 24
Finished Mar 21 01:18:20 PM PDT 24
Peak memory 211524 kb
Host smart-d04f04f0-47e9-4caa-8212-242be2f77bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036483337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.4036483337
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.694117485
Short name T1061
Test name
Test status
Simulation time 354410526 ps
CPU time 5.74 seconds
Started Mar 21 01:18:13 PM PDT 24
Finished Mar 21 01:18:19 PM PDT 24
Peak memory 263088 kb
Host smart-cc089ee9-c094-4b97-9490-1163a35a2b18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694117485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.694117485
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.45999975
Short name T918
Test name
Test status
Simulation time 2123322915 ps
CPU time 158.19 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 709552 kb
Host smart-e1ce8d70-d10d-4e65-856c-978d7b43fd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45999975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.45999975
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.99800758
Short name T711
Test name
Test status
Simulation time 271712324 ps
CPU time 1.02 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:18:14 PM PDT 24
Peak memory 203016 kb
Host smart-33b0ec52-8c43-4e7b-ac9b-7f9f437d531d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99800758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt
.99800758
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.397630331
Short name T399
Test name
Test status
Simulation time 196333580 ps
CPU time 5.69 seconds
Started Mar 21 01:18:19 PM PDT 24
Finished Mar 21 01:18:25 PM PDT 24
Peak memory 217160 kb
Host smart-009a9620-a382-4d7a-9091-77b8e1695b4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397630331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
397630331
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_override.475302491
Short name T245
Test name
Test status
Simulation time 41541437 ps
CPU time 0.66 seconds
Started Mar 21 01:18:07 PM PDT 24
Finished Mar 21 01:18:09 PM PDT 24
Peak memory 202492 kb
Host smart-aea29941-8638-46b6-84c1-e0f8387e88a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475302491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.475302491
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.4252619990
Short name T922
Test name
Test status
Simulation time 31215032405 ps
CPU time 3548.7 seconds
Started Mar 21 01:18:11 PM PDT 24
Finished Mar 21 02:17:21 PM PDT 24
Peak memory 1889200 kb
Host smart-4a2d9fa6-f210-496b-8301-78aa560f4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252619990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.4252619990
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3273244136
Short name T441
Test name
Test status
Simulation time 2820715400 ps
CPU time 50.31 seconds
Started Mar 21 01:18:12 PM PDT 24
Finished Mar 21 01:19:02 PM PDT 24
Peak memory 324680 kb
Host smart-d9b1b995-2800-4c04-a052-1e9c56e3b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273244136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3273244136
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1814480025
Short name T727
Test name
Test status
Simulation time 2435731706 ps
CPU time 3.15 seconds
Started Mar 21 01:18:18 PM PDT 24
Finished Mar 21 01:18:22 PM PDT 24
Peak memory 211648 kb
Host smart-03a64033-79ef-4fcc-8357-9cb4acfbd21f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814480025 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1814480025
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.633900955
Short name T372
Test name
Test status
Simulation time 10068842185 ps
CPU time 85.88 seconds
Started Mar 21 01:18:16 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 644812 kb
Host smart-f19904e5-fbc6-43e4-8a14-bce3dd4b46ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633900955 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.633900955
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2636317757
Short name T518
Test name
Test status
Simulation time 10069098385 ps
CPU time 12.7 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:18:40 PM PDT 24
Peak memory 298644 kb
Host smart-3d369d36-ff10-4b32-963c-5affb76307ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636317757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2636317757
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2416497485
Short name T1088
Test name
Test status
Simulation time 1699420231 ps
CPU time 2.41 seconds
Started Mar 21 01:18:22 PM PDT 24
Finished Mar 21 01:18:24 PM PDT 24
Peak memory 202844 kb
Host smart-e2d3a3ee-1993-416c-b16f-f2cdfbd0ea61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416497485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2416497485
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.460128078
Short name T455
Test name
Test status
Simulation time 1002299945 ps
CPU time 4.51 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:18:32 PM PDT 24
Peak memory 203332 kb
Host smart-e97adc65-a658-44d8-8a38-627c3d097894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460128078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.460128078
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.182096925
Short name T165
Test name
Test status
Simulation time 4766745720 ps
CPU time 45.08 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:19:15 PM PDT 24
Peak memory 203352 kb
Host smart-72d57556-1033-4241-86a6-4f237059da71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182096925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.182096925
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2474387716
Short name T688
Test name
Test status
Simulation time 6729507108 ps
CPU time 3.98 seconds
Started Mar 21 01:18:17 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 203396 kb
Host smart-f0ae3606-d1ee-4b12-be5b-ea19cb959ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474387716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2474387716
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3666924973
Short name T667
Test name
Test status
Simulation time 38496460476 ps
CPU time 389.17 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:25:01 PM PDT 24
Peak memory 2775104 kb
Host smart-cc93be1c-a31d-40be-a519-2dea98191c44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666924973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3666924973
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3633211200
Short name T340
Test name
Test status
Simulation time 2187649910 ps
CPU time 6.89 seconds
Started Mar 21 01:18:19 PM PDT 24
Finished Mar 21 01:18:26 PM PDT 24
Peak memory 211568 kb
Host smart-b81edaf7-cf0a-443f-9069-baf1520b4687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633211200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3633211200
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.1441325673
Short name T53
Test name
Test status
Simulation time 6870406407 ps
CPU time 9.35 seconds
Started Mar 21 01:18:22 PM PDT 24
Finished Mar 21 01:18:31 PM PDT 24
Peak memory 211640 kb
Host smart-de98e808-6c09-4cb1-878d-ac998954f59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441325673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.1441325673
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.716572541
Short name T630
Test name
Test status
Simulation time 40632981 ps
CPU time 0.62 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:18:40 PM PDT 24
Peak memory 203116 kb
Host smart-9d733189-6f99-4392-863b-f160d464be61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716572541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.716572541
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1561350454
Short name T979
Test name
Test status
Simulation time 33685203 ps
CPU time 1.4 seconds
Started Mar 21 01:18:34 PM PDT 24
Finished Mar 21 01:18:36 PM PDT 24
Peak memory 211540 kb
Host smart-7ceddf96-1296-447a-9d48-b1e6cfd9b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561350454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1561350454
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2889688406
Short name T895
Test name
Test status
Simulation time 745403507 ps
CPU time 4.28 seconds
Started Mar 21 01:18:23 PM PDT 24
Finished Mar 21 01:18:27 PM PDT 24
Peak memory 226980 kb
Host smart-8ff32a5c-eef4-4ea4-965d-f64d2af34340
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889688406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2889688406
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1582086303
Short name T902
Test name
Test status
Simulation time 6204480425 ps
CPU time 50.18 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 590424 kb
Host smart-ccd17db5-4a12-4613-bb00-03997080f310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582086303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1582086303
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1670633326
Short name T386
Test name
Test status
Simulation time 1740499965 ps
CPU time 56.99 seconds
Started Mar 21 01:18:25 PM PDT 24
Finished Mar 21 01:19:23 PM PDT 24
Peak memory 622260 kb
Host smart-aed0049a-d4b6-48fe-aeed-dfc38ee09d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670633326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1670633326
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2019738706
Short name T376
Test name
Test status
Simulation time 177271547 ps
CPU time 0.93 seconds
Started Mar 21 01:18:25 PM PDT 24
Finished Mar 21 01:18:26 PM PDT 24
Peak memory 202700 kb
Host smart-f5de433c-6765-475e-97c5-fec40277b5f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019738706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2019738706
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.490764830
Short name T270
Test name
Test status
Simulation time 315562930 ps
CPU time 4.68 seconds
Started Mar 21 01:18:20 PM PDT 24
Finished Mar 21 01:18:24 PM PDT 24
Peak memory 231464 kb
Host smart-a95ae000-5464-4d1d-9964-6031a1ef641a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490764830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
490764830
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2498672089
Short name T790
Test name
Test status
Simulation time 10685682294 ps
CPU time 174.9 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:21:21 PM PDT 24
Peak memory 841968 kb
Host smart-fa0e92ca-ab6f-4d88-a549-dcca7a575639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498672089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2498672089
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_override.1338147484
Short name T658
Test name
Test status
Simulation time 27947000 ps
CPU time 0.64 seconds
Started Mar 21 01:18:28 PM PDT 24
Finished Mar 21 01:18:29 PM PDT 24
Peak memory 202424 kb
Host smart-1aaa96a0-96e1-4271-8d70-4a08b6a7d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338147484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1338147484
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1846086320
Short name T40
Test name
Test status
Simulation time 30333862363 ps
CPU time 165.82 seconds
Started Mar 21 01:18:14 PM PDT 24
Finished Mar 21 01:21:00 PM PDT 24
Peak memory 219588 kb
Host smart-4b2d4b9f-8fa6-43cb-99d4-aef78a5360c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846086320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1846086320
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2654030553
Short name T635
Test name
Test status
Simulation time 5755472366 ps
CPU time 46.4 seconds
Started Mar 21 01:18:17 PM PDT 24
Finished Mar 21 01:19:04 PM PDT 24
Peak memory 314344 kb
Host smart-562a3bd7-9f47-4102-b4d0-9c1a5a0a81b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654030553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2654030553
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.694950966
Short name T360
Test name
Test status
Simulation time 1249797463 ps
CPU time 5.07 seconds
Started Mar 21 01:18:25 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 211452 kb
Host smart-cc2f76be-d5ca-4bed-9cb5-98c84f377ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694950966 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.694950966
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2537862291
Short name T752
Test name
Test status
Simulation time 10072147411 ps
CPU time 87.8 seconds
Started Mar 21 01:18:28 PM PDT 24
Finished Mar 21 01:19:57 PM PDT 24
Peak memory 680748 kb
Host smart-566cd7e7-a0db-4fda-91f6-89080143e970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537862291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2537862291
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2814087216
Short name T940
Test name
Test status
Simulation time 3913289506 ps
CPU time 5.38 seconds
Started Mar 21 01:18:28 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 203328 kb
Host smart-4af6a844-1181-4168-a311-61fbaac817af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814087216 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2814087216
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.298504556
Short name T1086
Test name
Test status
Simulation time 2412349723 ps
CPU time 15.54 seconds
Started Mar 21 01:18:17 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 203428 kb
Host smart-e576aea7-3467-4aa1-97f4-7c8d363b8ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298504556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.298504556
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2161407462
Short name T532
Test name
Test status
Simulation time 418960649 ps
CPU time 5.51 seconds
Started Mar 21 01:18:24 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 203324 kb
Host smart-e8c9bc71-ad45-4a9f-9535-0e3397ee2928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161407462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2161407462
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.691001304
Short name T844
Test name
Test status
Simulation time 21071346238 ps
CPU time 617.59 seconds
Started Mar 21 01:18:22 PM PDT 24
Finished Mar 21 01:28:40 PM PDT 24
Peak memory 3324712 kb
Host smart-1591a65a-1c4b-49eb-97db-bcdf449a1215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691001304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.691001304
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.383445825
Short name T643
Test name
Test status
Simulation time 1250396226 ps
CPU time 6.42 seconds
Started Mar 21 01:18:19 PM PDT 24
Finished Mar 21 01:18:26 PM PDT 24
Peak memory 209056 kb
Host smart-af755f49-ca70-471f-96de-6e58de80294b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383445825 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.383445825
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.2107158027
Short name T493
Test name
Test status
Simulation time 6452598627 ps
CPU time 4.93 seconds
Started Mar 21 01:18:18 PM PDT 24
Finished Mar 21 01:18:24 PM PDT 24
Peak memory 203460 kb
Host smart-16cac0ce-13e7-406a-99ad-ed77303d48ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107158027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.2107158027
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3028207733
Short name T517
Test name
Test status
Simulation time 46498439 ps
CPU time 0.6 seconds
Started Mar 21 01:18:39 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 202968 kb
Host smart-28dd47d6-5e51-45e5-98bd-9e7579479ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028207733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3028207733
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.883443110
Short name T648
Test name
Test status
Simulation time 38514096 ps
CPU time 1.17 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 211516 kb
Host smart-f16c9482-7829-456b-85c9-651c49d9d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883443110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.883443110
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1522952208
Short name T757
Test name
Test status
Simulation time 2225459399 ps
CPU time 11.65 seconds
Started Mar 21 01:18:24 PM PDT 24
Finished Mar 21 01:18:36 PM PDT 24
Peak memory 249600 kb
Host smart-64ff4161-03fd-44c8-b9fe-2f4f299601c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522952208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1522952208
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2729469656
Short name T865
Test name
Test status
Simulation time 8667106144 ps
CPU time 76.31 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 722516 kb
Host smart-3dfffcd9-f263-463f-af88-4bffaec88b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729469656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2729469656
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1190472462
Short name T935
Test name
Test status
Simulation time 1758743400 ps
CPU time 62.4 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:19:45 PM PDT 24
Peak memory 639764 kb
Host smart-72de7e10-5881-4ce6-8365-2642812d388d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190472462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1190472462
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1627328853
Short name T33
Test name
Test status
Simulation time 317848760 ps
CPU time 0.78 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 203012 kb
Host smart-4e2df003-b85d-480b-9b77-cb7bc5c3d68e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627328853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1627328853
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.585660972
Short name T241
Test name
Test status
Simulation time 167041561 ps
CPU time 8.89 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:39 PM PDT 24
Peak memory 203244 kb
Host smart-56318b68-8486-44b7-b34a-05c95ed5d613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585660972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
585660972
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2723830285
Short name T641
Test name
Test status
Simulation time 3636194961 ps
CPU time 108.26 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:20:14 PM PDT 24
Peak memory 1089164 kb
Host smart-0e5c3740-201d-4c75-9754-cabe5339c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723830285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2723830285
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_override.4226831961
Short name T686
Test name
Test status
Simulation time 28801011 ps
CPU time 0.66 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:44 PM PDT 24
Peak memory 202440 kb
Host smart-fa754e33-3a28-4a38-a433-46d52c23c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226831961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4226831961
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3320740383
Short name T791
Test name
Test status
Simulation time 5346457028 ps
CPU time 1060.88 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:36:08 PM PDT 24
Peak memory 948284 kb
Host smart-325e657e-7bce-446f-acc7-bd8c4f0e56d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320740383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3320740383
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1082873350
Short name T905
Test name
Test status
Simulation time 2451349184 ps
CPU time 56.77 seconds
Started Mar 21 01:18:40 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 340424 kb
Host smart-e778a736-e68c-47ec-9db8-51d7b44da064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082873350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1082873350
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2541427936
Short name T833
Test name
Test status
Simulation time 614994612 ps
CPU time 3.04 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:18:34 PM PDT 24
Peak memory 203324 kb
Host smart-31e0dace-e59f-4d0e-aac2-59b7c74b29e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541427936 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2541427936
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.4129630569
Short name T1052
Test name
Test status
Simulation time 10119018840 ps
CPU time 15.42 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 292172 kb
Host smart-4ef8ba42-5702-4d64-8c7f-90ae55d430be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129630569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.4129630569
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3071377463
Short name T629
Test name
Test status
Simulation time 10069629572 ps
CPU time 18.92 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:18:46 PM PDT 24
Peak memory 347028 kb
Host smart-d5d355ce-cb2c-4e52-aa4b-c5d91dbf7f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071377463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3071377463
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.908322804
Short name T44
Test name
Test status
Simulation time 368170698 ps
CPU time 2.15 seconds
Started Mar 21 01:18:29 PM PDT 24
Finished Mar 21 01:18:32 PM PDT 24
Peak memory 203412 kb
Host smart-a4a1144f-ccd9-46e0-9a0c-04b18f3902ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908322804 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.908322804
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1625382739
Short name T764
Test name
Test status
Simulation time 3257309163 ps
CPU time 4.16 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 207060 kb
Host smart-b68ec4f6-94c2-4b68-9e01-8e405f1d2adc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625382739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1625382739
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1459819084
Short name T498
Test name
Test status
Simulation time 1017114366 ps
CPU time 17.12 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 203336 kb
Host smart-acf4ced5-b2c4-4105-bcfe-1504b1d1d6c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459819084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1459819084
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3617047623
Short name T1066
Test name
Test status
Simulation time 1292522884 ps
CPU time 59.06 seconds
Started Mar 21 01:18:26 PM PDT 24
Finished Mar 21 01:19:25 PM PDT 24
Peak memory 205560 kb
Host smart-95253077-c787-4219-9c67-118c633dae91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617047623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3617047623
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3255026776
Short name T848
Test name
Test status
Simulation time 12380254459 ps
CPU time 23.63 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:18:51 PM PDT 24
Peak memory 203380 kb
Host smart-53c7d45e-3dbc-4b1d-bd47-14f2362a1a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255026776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3255026776
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.935141800
Short name T759
Test name
Test status
Simulation time 13230646230 ps
CPU time 27.9 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:19:01 PM PDT 24
Peak memory 271684 kb
Host smart-0b61e49c-f971-4f05-8d7d-e5b7d5218249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935141800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.935141800
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3060977781
Short name T479
Test name
Test status
Simulation time 4053715172 ps
CPU time 5.29 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:39 PM PDT 24
Peak memory 203348 kb
Host smart-f0a892a8-8976-4ab7-9820-4416e3504bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060977781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3060977781
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2405695460
Short name T955
Test name
Test status
Simulation time 15715304 ps
CPU time 0.67 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 203132 kb
Host smart-4ba8fe24-fc85-44d2-9d69-e6f0a94bc506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405695460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2405695460
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3929522318
Short name T1017
Test name
Test status
Simulation time 106274981 ps
CPU time 1.46 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 211492 kb
Host smart-bdf83261-c392-48b7-9c71-9eda2a4be6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929522318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3929522318
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1683097303
Short name T560
Test name
Test status
Simulation time 229364269 ps
CPU time 12.18 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 246804 kb
Host smart-a66fb4ed-fa93-46b3-831e-c883065b8a17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683097303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1683097303
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1409117888
Short name T31
Test name
Test status
Simulation time 1836247308 ps
CPU time 127.01 seconds
Started Mar 21 01:18:40 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 627076 kb
Host smart-246da327-fa6a-4bfc-a4eb-f9885bb047fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409117888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1409117888
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3101722483
Short name T704
Test name
Test status
Simulation time 133208799 ps
CPU time 0.97 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:35 PM PDT 24
Peak memory 203028 kb
Host smart-1ccfa5d1-7dad-4031-8aef-d9f0b55f0479
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101722483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3101722483
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3342407304
Short name T186
Test name
Test status
Simulation time 127211391 ps
CPU time 7.32 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:38 PM PDT 24
Peak memory 203384 kb
Host smart-dadc94a9-4729-4d93-8f1a-e6dab7a1cac8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342407304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3342407304
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1164435664
Short name T10
Test name
Test status
Simulation time 2953431774 ps
CPU time 84.64 seconds
Started Mar 21 01:18:38 PM PDT 24
Finished Mar 21 01:20:03 PM PDT 24
Peak memory 885848 kb
Host smart-bd06896e-d967-48cb-9e47-ad75cdba3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164435664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1164435664
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_override.2573212517
Short name T723
Test name
Test status
Simulation time 50965217 ps
CPU time 0.65 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 202432 kb
Host smart-28b0cc1a-72ff-4188-9756-6af33fa8c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573212517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2573212517
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.659766438
Short name T272
Test name
Test status
Simulation time 1255797477 ps
CPU time 12.12 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:43 PM PDT 24
Peak memory 203268 kb
Host smart-93e3f708-3cba-49f9-9b6c-c33dcd1b4dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659766438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.659766438
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3305764805
Short name T869
Test name
Test status
Simulation time 7986677258 ps
CPU time 80.57 seconds
Started Mar 21 01:18:39 PM PDT 24
Finished Mar 21 01:20:02 PM PDT 24
Peak memory 384584 kb
Host smart-5c83662a-919c-4df2-85b7-c002ecfb5117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305764805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3305764805
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2186498459
Short name T817
Test name
Test status
Simulation time 10289584911 ps
CPU time 3.09 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 203284 kb
Host smart-a4678a9c-1ed1-43bb-98bf-b52818c76864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186498459 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2186498459
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1895058248
Short name T588
Test name
Test status
Simulation time 10380854866 ps
CPU time 9.85 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:44 PM PDT 24
Peak memory 255652 kb
Host smart-772ef9dc-56e3-4d5a-a885-02bb3ef59e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895058248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1895058248
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.135906532
Short name T628
Test name
Test status
Simulation time 10972041022 ps
CPU time 8.24 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:18:41 PM PDT 24
Peak memory 276084 kb
Host smart-7b4aadc5-1fd9-49b7-ad5d-539f0641f649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135906532 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.135906532
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2413348780
Short name T406
Test name
Test status
Simulation time 379234069 ps
CPU time 2.37 seconds
Started Mar 21 01:18:30 PM PDT 24
Finished Mar 21 01:18:32 PM PDT 24
Peak memory 203428 kb
Host smart-c9970330-ee5f-4000-8cb0-acdcb83df2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413348780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2413348780
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.635713967
Short name T300
Test name
Test status
Simulation time 3298866179 ps
CPU time 4.33 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 203332 kb
Host smart-22b4c55d-f841-4a46-91cd-e84cbc99e8c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635713967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.635713967
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2154957673
Short name T1034
Test name
Test status
Simulation time 2512721224 ps
CPU time 17.18 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 203388 kb
Host smart-b59942aa-8745-4075-b87b-a248c2fb09dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154957673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2154957673
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.661908674
Short name T565
Test name
Test status
Simulation time 4193380390 ps
CPU time 13.39 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 206164 kb
Host smart-46dcdf36-347e-4a23-b7dc-c4cfddaa3897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661908674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.661908674
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.963583002
Short name T724
Test name
Test status
Simulation time 8680623232 ps
CPU time 66.91 seconds
Started Mar 21 01:18:32 PM PDT 24
Finished Mar 21 01:19:41 PM PDT 24
Peak memory 596000 kb
Host smart-d46cdaf1-36b6-4da5-afbc-26352156683c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963583002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.963583002
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.406572110
Short name T1089
Test name
Test status
Simulation time 5529223953 ps
CPU time 6.47 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:18:43 PM PDT 24
Peak memory 211596 kb
Host smart-7a7f0644-3028-4894-9179-97f4a0037504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406572110 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.406572110
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.641852862
Short name T857
Test name
Test status
Simulation time 32328090 ps
CPU time 0.6 seconds
Started Mar 21 01:18:40 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 203132 kb
Host smart-0f64b15c-f0dd-4903-8c9d-7bcba294c7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641852862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.641852862
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2852014148
Short name T48
Test name
Test status
Simulation time 255331961 ps
CPU time 1.22 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:18:29 PM PDT 24
Peak memory 211492 kb
Host smart-24d96633-2ca9-4060-9f10-def15901fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852014148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2852014148
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.647401021
Short name T274
Test name
Test status
Simulation time 1332729443 ps
CPU time 2.89 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 212888 kb
Host smart-7bd7b69d-9682-4c1f-8fd8-96e344fe5d37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647401021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.647401021
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1589931399
Short name T438
Test name
Test status
Simulation time 6415112230 ps
CPU time 44.55 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 485676 kb
Host smart-cecd7c8d-9541-4b79-a24d-83e622da2d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589931399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1589931399
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.768883293
Short name T291
Test name
Test status
Simulation time 1185610964 ps
CPU time 37.84 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 01:19:21 PM PDT 24
Peak memory 493568 kb
Host smart-351e8c46-ef02-466b-99cb-726df241d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768883293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.768883293
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.917303996
Short name T939
Test name
Test status
Simulation time 1124737544 ps
CPU time 0.9 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 202912 kb
Host smart-a864c385-cf57-46dd-b048-4aaa9e7f51e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917303996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.917303996
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.374888535
Short name T693
Test name
Test status
Simulation time 105105622 ps
CPU time 3.76 seconds
Started Mar 21 01:18:31 PM PDT 24
Finished Mar 21 01:18:37 PM PDT 24
Peak memory 217648 kb
Host smart-6708438d-6e69-4dda-901d-9065664c9dad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374888535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
374888535
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1116071810
Short name T520
Test name
Test status
Simulation time 86328561428 ps
CPU time 141.35 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:21:05 PM PDT 24
Peak memory 1279144 kb
Host smart-8ee9bbae-b572-4889-b200-8a5d0de077f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116071810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1116071810
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_override.3075765075
Short name T170
Test name
Test status
Simulation time 27591879 ps
CPU time 0.68 seconds
Started Mar 21 01:18:27 PM PDT 24
Finished Mar 21 01:18:27 PM PDT 24
Peak memory 202440 kb
Host smart-630b1747-66c3-4ef2-9227-b21fe7905868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075765075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3075765075
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3205158541
Short name T463
Test name
Test status
Simulation time 25486735404 ps
CPU time 1258.56 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:39:44 PM PDT 24
Peak memory 622872 kb
Host smart-28c7972c-c7b8-47b0-b397-141dac971a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205158541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3205158541
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1937976040
Short name T290
Test name
Test status
Simulation time 1706208539 ps
CPU time 32.73 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 295096 kb
Host smart-ea8e2dc3-fb31-4480-b70f-472781cdeb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937976040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1937976040
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1474346521
Short name T307
Test name
Test status
Simulation time 1082430890 ps
CPU time 4.2 seconds
Started Mar 21 01:18:38 PM PDT 24
Finished Mar 21 01:18:43 PM PDT 24
Peak memory 203400 kb
Host smart-99be3372-a1ae-44c2-bb36-08da68d6acd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474346521 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1474346521
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1470923308
Short name T843
Test name
Test status
Simulation time 10059712599 ps
CPU time 31.52 seconds
Started Mar 21 01:18:39 PM PDT 24
Finished Mar 21 01:19:11 PM PDT 24
Peak memory 400544 kb
Host smart-89b3695f-87e6-4f80-8c12-82cd2dca239f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470923308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1470923308
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3909416834
Short name T56
Test name
Test status
Simulation time 10105959480 ps
CPU time 15.14 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:18:51 PM PDT 24
Peak memory 324036 kb
Host smart-077e695f-e691-46cb-8a37-62cdb7a5ca17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909416834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3909416834
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.431291789
Short name T45
Test name
Test status
Simulation time 1112892027 ps
CPU time 3.26 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:18:39 PM PDT 24
Peak memory 203436 kb
Host smart-117541ca-ded3-42c8-aa0e-34287e2b51ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431291789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.431291789
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.775407480
Short name T263
Test name
Test status
Simulation time 10351316673 ps
CPU time 5.71 seconds
Started Mar 21 01:18:38 PM PDT 24
Finished Mar 21 01:18:45 PM PDT 24
Peak memory 219980 kb
Host smart-5298affb-1ca7-40a9-ae95-fecf75284a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775407480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.775407480
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3150894654
Short name T398
Test name
Test status
Simulation time 4729045345 ps
CPU time 12.57 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:18:51 PM PDT 24
Peak memory 203332 kb
Host smart-c10003b1-ac89-4f0b-a1c4-21bf4c03c27a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150894654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3150894654
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1281976817
Short name T665
Test name
Test status
Simulation time 1059980063 ps
CPU time 45.73 seconds
Started Mar 21 01:18:40 PM PDT 24
Finished Mar 21 01:19:27 PM PDT 24
Peak memory 203808 kb
Host smart-cb58f6d2-5ad7-4804-9229-ab3a5bee2007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281976817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1281976817
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1578442283
Short name T942
Test name
Test status
Simulation time 8220509127 ps
CPU time 22.67 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:18:59 PM PDT 24
Peak memory 473528 kb
Host smart-f2e93326-b990-48c8-813a-9cab5fe9c373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578442283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1578442283
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3177602988
Short name T464
Test name
Test status
Simulation time 5957644112 ps
CPU time 6.89 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:18:44 PM PDT 24
Peak memory 203404 kb
Host smart-8d3de525-d612-4729-932c-c16cdb8556da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177602988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3177602988
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3911852373
Short name T90
Test name
Test status
Simulation time 54513265 ps
CPU time 0.62 seconds
Started Mar 21 01:18:41 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 203032 kb
Host smart-e173c572-fcbb-4e33-9a42-5dd433ae20bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911852373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3911852373
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.973501239
Short name T574
Test name
Test status
Simulation time 34556411 ps
CPU time 1.77 seconds
Started Mar 21 01:18:34 PM PDT 24
Finished Mar 21 01:18:36 PM PDT 24
Peak memory 211504 kb
Host smart-7eee8b21-1f10-4015-8460-1a3f874ef233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973501239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.973501239
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3412455659
Short name T866
Test name
Test status
Simulation time 1281512332 ps
CPU time 6.55 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 273684 kb
Host smart-a1705f6b-09ae-42dc-b55a-0b2e87f32d02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412455659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3412455659
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1799465590
Short name T314
Test name
Test status
Simulation time 2422727647 ps
CPU time 173.92 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:21:31 PM PDT 24
Peak memory 759460 kb
Host smart-89519d4a-7f26-428a-8279-b9ad38be44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799465590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1799465590
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.474038721
Short name T557
Test name
Test status
Simulation time 3608892458 ps
CPU time 45.18 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 559680 kb
Host smart-39d2aac6-38dc-4a1c-8a0a-bcdee2f956f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474038721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.474038721
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3125800880
Short name T801
Test name
Test status
Simulation time 94322571 ps
CPU time 0.9 seconds
Started Mar 21 01:18:33 PM PDT 24
Finished Mar 21 01:18:36 PM PDT 24
Peak memory 202596 kb
Host smart-9f666253-1959-463d-a837-a5cf0b4606a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125800880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3125800880
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2257200588
Short name T481
Test name
Test status
Simulation time 494033657 ps
CPU time 4.08 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 224228 kb
Host smart-69cb3179-6c96-4b95-95c7-5a11dd64ee77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257200588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2257200588
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.171916495
Short name T366
Test name
Test status
Simulation time 7894056630 ps
CPU time 108.46 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 1120648 kb
Host smart-7c2c52b5-687b-4a2a-a3f5-c7f53d1c72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171916495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.171916495
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_override.832202572
Short name T496
Test name
Test status
Simulation time 17644635 ps
CPU time 0.67 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:18:37 PM PDT 24
Peak memory 202568 kb
Host smart-721ae693-1e6d-4323-b16f-7f9eac75ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832202572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.832202572
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3618565279
Short name T38
Test name
Test status
Simulation time 5486216031 ps
CPU time 26 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:19:12 PM PDT 24
Peak memory 219540 kb
Host smart-cc6156bc-72b2-483f-949f-66178569ccf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618565279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3618565279
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.92188335
Short name T819
Test name
Test status
Simulation time 1522301106 ps
CPU time 36.68 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:19:13 PM PDT 24
Peak memory 270212 kb
Host smart-a232005c-7c13-4c7b-bbb3-cc6ddc784039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92188335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.92188335
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1955724018
Short name T476
Test name
Test status
Simulation time 2870147401 ps
CPU time 3.59 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 203484 kb
Host smart-49a89d31-214d-40d5-b58f-337fac6d2af3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955724018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1955724018
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2250669027
Short name T983
Test name
Test status
Simulation time 10243000115 ps
CPU time 13.79 seconds
Started Mar 21 01:18:41 PM PDT 24
Finished Mar 21 01:18:56 PM PDT 24
Peak memory 284064 kb
Host smart-6306b9dd-dfdb-40ad-9f20-ced855433165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250669027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2250669027
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2983264120
Short name T694
Test name
Test status
Simulation time 10093492934 ps
CPU time 93.76 seconds
Started Mar 21 01:18:38 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 747708 kb
Host smart-b08a05a4-d373-4d0d-a21b-8e0444d9e5c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983264120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2983264120
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.807969391
Short name T986
Test name
Test status
Simulation time 772834757 ps
CPU time 2.37 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:18:39 PM PDT 24
Peak memory 203328 kb
Host smart-3b81dcd4-e7ff-423b-b292-ac96322dad69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807969391 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.807969391
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1055073424
Short name T1078
Test name
Test status
Simulation time 2440154180 ps
CPU time 3.52 seconds
Started Mar 21 01:18:37 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 203352 kb
Host smart-cda1316e-b4f5-4b20-89f9-2fc51d14eb38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055073424 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1055073424
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3582273166
Short name T351
Test name
Test status
Simulation time 630063457 ps
CPU time 7.82 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 01:18:51 PM PDT 24
Peak memory 203400 kb
Host smart-1b1375e8-4e48-477c-b0a1-a31be13a415e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582273166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3582273166
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1393580246
Short name T4
Test name
Test status
Simulation time 679095555 ps
CPU time 28.5 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 203432 kb
Host smart-b8eb98b9-3f34-4dbf-a341-99dd4159a491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393580246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1393580246
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2593860762
Short name T673
Test name
Test status
Simulation time 43002105258 ps
CPU time 3122.92 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 02:10:46 PM PDT 24
Peak memory 4770108 kb
Host smart-9cf67425-cb34-4935-ab17-a2fb644d8a01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593860762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2593860762
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1818220160
Short name T544
Test name
Test status
Simulation time 11831543594 ps
CPU time 7.18 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 219696 kb
Host smart-0681d68f-65bc-48d7-9b13-eb5f286c0277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818220160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1818220160
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.845028173
Short name T615
Test name
Test status
Simulation time 24747721 ps
CPU time 0.6 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 202972 kb
Host smart-1fde0345-5ed7-4010-b784-0e4ce6085460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845028173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.845028173
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.4046951047
Short name T1083
Test name
Test status
Simulation time 86888909 ps
CPU time 1.33 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 214932 kb
Host smart-900444c3-96d0-400e-9dc4-21617d4ef2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046951047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.4046951047
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2907845744
Short name T353
Test name
Test status
Simulation time 486920980 ps
CPU time 12.79 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:56 PM PDT 24
Peak memory 250412 kb
Host smart-c7e75771-92b0-49be-9c12-646f0c4c5809
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907845744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2907845744
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.32158993
Short name T315
Test name
Test status
Simulation time 21731264176 ps
CPU time 87.26 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:20:04 PM PDT 24
Peak memory 773892 kb
Host smart-4f0e8c06-f3d0-48e2-aa62-423212736968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32158993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.32158993
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2082748064
Short name T949
Test name
Test status
Simulation time 2437837594 ps
CPU time 78.97 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 01:20:01 PM PDT 24
Peak memory 472812 kb
Host smart-f45d42e5-0d3f-463b-8c95-20f9851cbd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082748064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2082748064
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1978158599
Short name T394
Test name
Test status
Simulation time 393261313 ps
CPU time 1.02 seconds
Started Mar 21 01:18:42 PM PDT 24
Finished Mar 21 01:18:44 PM PDT 24
Peak memory 203408 kb
Host smart-e4bc25a0-c7a6-403d-ae16-c6d0864dccd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978158599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1978158599
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3856393443
Short name T451
Test name
Test status
Simulation time 138896469 ps
CPU time 3.97 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:18:41 PM PDT 24
Peak memory 226092 kb
Host smart-e0678804-ff03-405e-a161-957a1b48c484
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856393443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3856393443
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3784198798
Short name T612
Test name
Test status
Simulation time 4295313774 ps
CPU time 130.19 seconds
Started Mar 21 01:18:35 PM PDT 24
Finished Mar 21 01:20:47 PM PDT 24
Peak memory 1229152 kb
Host smart-5b9caaa4-4b30-403c-9133-e612889bc62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784198798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3784198798
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.931408673
Short name T831
Test name
Test status
Simulation time 15347584 ps
CPU time 0.65 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:18:45 PM PDT 24
Peak memory 202432 kb
Host smart-e617d935-4484-4890-9558-ddb1263b3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931408673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.931408673
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2896983408
Short name T912
Test name
Test status
Simulation time 7106807688 ps
CPU time 942.36 seconds
Started Mar 21 01:18:36 PM PDT 24
Finished Mar 21 01:34:19 PM PDT 24
Peak memory 880140 kb
Host smart-71c4ba82-a2ee-4111-8743-3a3fa9fdae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896983408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2896983408
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.222207905
Short name T820
Test name
Test status
Simulation time 4272096721 ps
CPU time 56.69 seconds
Started Mar 21 01:18:43 PM PDT 24
Finished Mar 21 01:19:41 PM PDT 24
Peak memory 332060 kb
Host smart-c94bcd15-bd52-4877-940e-805c10daef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222207905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.222207905
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3251964477
Short name T720
Test name
Test status
Simulation time 722739997 ps
CPU time 3.12 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 203344 kb
Host smart-dd0b428d-2577-4c82-9f23-5662ac21379d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251964477 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3251964477
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2330405964
Short name T539
Test name
Test status
Simulation time 10025980087 ps
CPU time 99.45 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 641024 kb
Host smart-4299038f-7b9c-408b-a4cb-dc8d3308c346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330405964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2330405964
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3760600414
Short name T692
Test name
Test status
Simulation time 10586117704 ps
CPU time 6.47 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:54 PM PDT 24
Peak memory 255816 kb
Host smart-cfada05c-09c1-42b5-83a7-3ee7cd3dd542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760600414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3760600414
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.642350428
Short name T984
Test name
Test status
Simulation time 794039276 ps
CPU time 2.36 seconds
Started Mar 21 01:18:49 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 203420 kb
Host smart-f7514f87-fe99-4756-9957-d319975bfd41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642350428 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.642350428
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1131856546
Short name T987
Test name
Test status
Simulation time 1061648602 ps
CPU time 5.33 seconds
Started Mar 21 01:18:46 PM PDT 24
Finished Mar 21 01:18:53 PM PDT 24
Peak memory 208456 kb
Host smart-81324645-a89a-47e4-993a-800c60abc5cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131856546 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1131856546
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2557996145
Short name T886
Test name
Test status
Simulation time 10698297937 ps
CPU time 11.13 seconds
Started Mar 21 01:18:34 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 203388 kb
Host smart-f94df4bf-5a24-4187-91a1-fb865e129ebf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557996145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2557996145
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.1293567387
Short name T312
Test name
Test status
Simulation time 1084780031 ps
CPU time 4.02 seconds
Started Mar 21 01:18:44 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 203460 kb
Host smart-622274a6-aa83-4247-8791-cc8d9e00063a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293567387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.1293567387
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.651222264
Short name T1065
Test name
Test status
Simulation time 2151184052 ps
CPU time 6.33 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:18:54 PM PDT 24
Peak memory 203360 kb
Host smart-28f62796-10b6-426f-b07e-0ffa9701412c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651222264 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.651222264
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.877462871
Short name T462
Test name
Test status
Simulation time 51308012 ps
CPU time 0.6 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 203052 kb
Host smart-ed00c7a9-9d0d-4e0e-9935-0ba6432f3bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877462871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.877462871
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1721252688
Short name T515
Test name
Test status
Simulation time 38204463 ps
CPU time 1.72 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 211484 kb
Host smart-8155a6fb-9518-44b5-87c2-1542493cc9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721252688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1721252688
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2340912023
Short name T676
Test name
Test status
Simulation time 866641046 ps
CPU time 8.27 seconds
Started Mar 21 01:18:49 PM PDT 24
Finished Mar 21 01:18:58 PM PDT 24
Peak memory 299496 kb
Host smart-f491776c-485d-4728-aa0d-76b52ea61971
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340912023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.2340912023
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4100960778
Short name T494
Test name
Test status
Simulation time 15079915603 ps
CPU time 90.23 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:20:18 PM PDT 24
Peak memory 419728 kb
Host smart-1d9e30d3-cad7-4daa-a2dd-079323131166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100960778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4100960778
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2318628568
Short name T254
Test name
Test status
Simulation time 3460590842 ps
CPU time 54.12 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:19:41 PM PDT 24
Peak memory 599352 kb
Host smart-307f1ef9-f0a6-49e2-8860-d8ec48572a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318628568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2318628568
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4047628815
Short name T449
Test name
Test status
Simulation time 449739015 ps
CPU time 0.99 seconds
Started Mar 21 01:18:49 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 203036 kb
Host smart-1544ea0b-1f56-4aab-bdb8-c408a43ab769
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047628815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4047628815
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.302271499
Short name T1072
Test name
Test status
Simulation time 562815256 ps
CPU time 7.72 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:18:54 PM PDT 24
Peak memory 203300 kb
Host smart-e5297747-b307-4c2e-b36b-d2853e92ca20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302271499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
302271499
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2238249778
Short name T1033
Test name
Test status
Simulation time 3768291974 ps
CPU time 91.02 seconds
Started Mar 21 01:18:50 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 1130508 kb
Host smart-ce2a76b1-a58a-4937-ad77-47c8c6f9e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238249778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2238249778
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_override.65361155
Short name T174
Test name
Test status
Simulation time 44783083 ps
CPU time 0.73 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 202528 kb
Host smart-cc040bf9-3a1f-4230-9b2c-1d78caf88bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65361155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.65361155
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1859792799
Short name T546
Test name
Test status
Simulation time 948287782 ps
CPU time 64.39 seconds
Started Mar 21 01:18:50 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 250804 kb
Host smart-7ed53093-3d29-40f1-8636-8f24a23b3ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859792799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1859792799
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3182589402
Short name T285
Test name
Test status
Simulation time 3040187121 ps
CPU time 3.13 seconds
Started Mar 21 01:18:45 PM PDT 24
Finished Mar 21 01:18:48 PM PDT 24
Peak memory 203512 kb
Host smart-125e70f9-38a3-4e53-bb08-a6135d915498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182589402 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3182589402
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3378947151
Short name T714
Test name
Test status
Simulation time 10088957424 ps
CPU time 69.41 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 613968 kb
Host smart-356c9a3f-8b9e-4c27-8004-7cce90031abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378947151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3378947151
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2446351619
Short name T822
Test name
Test status
Simulation time 10072661599 ps
CPU time 85.2 seconds
Started Mar 21 01:18:46 PM PDT 24
Finished Mar 21 01:20:12 PM PDT 24
Peak memory 693272 kb
Host smart-9a60baa7-7467-4488-a0b7-ba9cb6e2a671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446351619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2446351619
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.339619863
Short name T885
Test name
Test status
Simulation time 1511107599 ps
CPU time 2.18 seconds
Started Mar 21 01:18:50 PM PDT 24
Finished Mar 21 01:18:53 PM PDT 24
Peak memory 203396 kb
Host smart-ab094a79-5ce1-4f86-89e7-bdbed81836d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339619863 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.339619863
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.107284853
Short name T378
Test name
Test status
Simulation time 1166100314 ps
CPU time 5.08 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 211608 kb
Host smart-035f19e9-52e9-430a-9cfb-5bafc7a15a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107284853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.107284853
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.4048514605
Short name T1081
Test name
Test status
Simulation time 21631097881 ps
CPU time 43.29 seconds
Started Mar 21 01:18:49 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203384 kb
Host smart-1e0f1c39-d339-4574-8bc1-cebd1ef3e113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048514605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.4048514605
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2644867203
Short name T1069
Test name
Test status
Simulation time 1814575024 ps
CPU time 5.57 seconds
Started Mar 21 01:18:46 PM PDT 24
Finished Mar 21 01:18:53 PM PDT 24
Peak memory 203308 kb
Host smart-dc3b1f99-0f03-4019-9cb3-cd04504dc3c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644867203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2644867203
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.4142113528
Short name T654
Test name
Test status
Simulation time 10513860005 ps
CPU time 144.76 seconds
Started Mar 21 01:18:44 PM PDT 24
Finished Mar 21 01:21:09 PM PDT 24
Peak memory 717228 kb
Host smart-270e784e-878b-4eed-8cb8-36b8ea6cb711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142113528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.4142113528
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3503632264
Short name T867
Test name
Test status
Simulation time 1443671904 ps
CPU time 6.11 seconds
Started Mar 21 01:18:47 PM PDT 24
Finished Mar 21 01:18:54 PM PDT 24
Peak memory 210364 kb
Host smart-ef3e212d-70e3-4158-b18f-180d00eefa4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503632264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3503632264
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1233702953
Short name T839
Test name
Test status
Simulation time 83755178 ps
CPU time 1.49 seconds
Started Mar 21 01:17:29 PM PDT 24
Finished Mar 21 01:17:30 PM PDT 24
Peak memory 213296 kb
Host smart-0dcd598f-5e40-4187-b51f-ee150eb8bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233702953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1233702953
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1542289098
Short name T669
Test name
Test status
Simulation time 472626197 ps
CPU time 26.04 seconds
Started Mar 21 01:17:31 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 310444 kb
Host smart-048207d0-a259-4f44-ada2-732e0cc73158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542289098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1542289098
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4036080694
Short name T547
Test name
Test status
Simulation time 4107793834 ps
CPU time 62.29 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:18:40 PM PDT 24
Peak memory 547396 kb
Host smart-351815f3-0d85-4767-b384-a7a929f23635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036080694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4036080694
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1389775433
Short name T967
Test name
Test status
Simulation time 10112428073 ps
CPU time 80.51 seconds
Started Mar 21 01:17:29 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 726544 kb
Host smart-29bfea85-d75e-4bea-9651-665d1a82b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389775433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1389775433
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1446745502
Short name T253
Test name
Test status
Simulation time 166422443 ps
CPU time 1.14 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 202748 kb
Host smart-3778b5ff-c2f6-4ab3-b870-5f07c21fce30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446745502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1446745502
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2433185953
Short name T67
Test name
Test status
Simulation time 604264478 ps
CPU time 9 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:17:44 PM PDT 24
Peak memory 203280 kb
Host smart-a971e70f-e888-4557-82c4-55f8d68c1cda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433185953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2433185953
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3812554764
Short name T826
Test name
Test status
Simulation time 11348414633 ps
CPU time 196.73 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:20:52 PM PDT 24
Peak memory 881704 kb
Host smart-b9716abf-5170-470e-abfb-a15b65d9fbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812554764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3812554764
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_perf.4169721420
Short name T12
Test name
Test status
Simulation time 4975049956 ps
CPU time 562.24 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:27:00 PM PDT 24
Peak memory 726240 kb
Host smart-c689d4b1-c423-4759-a142-04a42c115208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169721420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.4169721420
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2361475761
Short name T624
Test name
Test status
Simulation time 1260107035 ps
CPU time 102.27 seconds
Started Mar 21 01:17:32 PM PDT 24
Finished Mar 21 01:19:14 PM PDT 24
Peak memory 294820 kb
Host smart-b2d266ef-8d41-4b7b-9dbf-b7f692a4cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361475761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2361475761
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.898517713
Short name T102
Test name
Test status
Simulation time 15603405070 ps
CPU time 809.99 seconds
Started Mar 21 01:17:26 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 2013392 kb
Host smart-7c825273-8610-46dc-8dfa-0c85b55519cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898517713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.898517713
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1410547146
Short name T81
Test name
Test status
Simulation time 255719273 ps
CPU time 0.91 seconds
Started Mar 21 01:17:29 PM PDT 24
Finished Mar 21 01:17:30 PM PDT 24
Peak memory 221592 kb
Host smart-e684ca55-b0ce-4b47-be3e-e52f5e659604
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410547146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1410547146
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1405994079
Short name T639
Test name
Test status
Simulation time 1102927030 ps
CPU time 4.62 seconds
Started Mar 21 01:17:34 PM PDT 24
Finished Mar 21 01:17:39 PM PDT 24
Peak memory 211656 kb
Host smart-f6fb026f-7263-4dc5-a6d5-bff18e84134c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405994079 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1405994079
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.560918001
Short name T597
Test name
Test status
Simulation time 10311899433 ps
CPU time 15.86 seconds
Started Mar 21 01:17:36 PM PDT 24
Finished Mar 21 01:17:52 PM PDT 24
Peak memory 298184 kb
Host smart-79d5ec71-aca7-4adf-b8cf-e1bc3987621a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560918001 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.560918001
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3046860617
Short name T459
Test name
Test status
Simulation time 10248021448 ps
CPU time 43.94 seconds
Started Mar 21 01:17:25 PM PDT 24
Finished Mar 21 01:18:09 PM PDT 24
Peak memory 463584 kb
Host smart-bdb1eacb-53c7-4e57-a2c0-e54a70f4e605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046860617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3046860617
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.552240032
Short name T239
Test name
Test status
Simulation time 538127885 ps
CPU time 3.22 seconds
Started Mar 21 01:17:27 PM PDT 24
Finished Mar 21 01:17:30 PM PDT 24
Peak memory 203320 kb
Host smart-0fb4ebd6-7892-441a-91da-bd5971c124eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552240032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.552240032
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.984066854
Short name T475
Test name
Test status
Simulation time 2864317439 ps
CPU time 4.05 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:17:43 PM PDT 24
Peak memory 203404 kb
Host smart-5969c183-c4ca-4614-8aff-efcc4844598b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984066854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.984066854
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1681181455
Short name T604
Test name
Test status
Simulation time 722503510 ps
CPU time 10.22 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:17:50 PM PDT 24
Peak memory 203276 kb
Host smart-5e60dfa7-ae86-46f1-ab01-727bc7e6ecdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681181455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1681181455
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2326296378
Short name T271
Test name
Test status
Simulation time 2415382461 ps
CPU time 20.31 seconds
Started Mar 21 01:17:31 PM PDT 24
Finished Mar 21 01:17:52 PM PDT 24
Peak memory 212820 kb
Host smart-cc3f8469-4602-41fb-904e-e2e4ac5bbf1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326296378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2326296378
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.172946970
Short name T163
Test name
Test status
Simulation time 15778957035 ps
CPU time 31.02 seconds
Started Mar 21 01:17:27 PM PDT 24
Finished Mar 21 01:17:58 PM PDT 24
Peak memory 203368 kb
Host smart-53b5ecdc-562f-482a-a72b-9c37a6e6a0ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172946970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.172946970
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.161313342
Short name T788
Test name
Test status
Simulation time 1091188603 ps
CPU time 6.07 seconds
Started Mar 21 01:17:33 PM PDT 24
Finished Mar 21 01:17:39 PM PDT 24
Peak memory 219476 kb
Host smart-5b9fb2c1-8026-4a62-aada-c65c79f1d457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161313342 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.161313342
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1826331413
Short name T160
Test name
Test status
Simulation time 42262239 ps
CPU time 0.58 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:18:57 PM PDT 24
Peak memory 203020 kb
Host smart-3d172bf0-83bf-4916-8f2d-9a619a3655b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826331413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1826331413
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.858789413
Short name T964
Test name
Test status
Simulation time 40440227 ps
CPU time 1.3 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:18:59 PM PDT 24
Peak memory 211464 kb
Host smart-31a830fa-9300-4d6e-befe-d4502fbf7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858789413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.858789413
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2632907347
Short name T965
Test name
Test status
Simulation time 357458307 ps
CPU time 6.46 seconds
Started Mar 21 01:18:56 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 260424 kb
Host smart-94055b55-00ff-4483-9276-fb85e2e6d822
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632907347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2632907347
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4190198843
Short name T403
Test name
Test status
Simulation time 5057123982 ps
CPU time 78.49 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:20:16 PM PDT 24
Peak memory 473076 kb
Host smart-dc3844c7-8943-4266-a733-cd5c85bf1d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190198843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4190198843
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3571253660
Short name T970
Test name
Test status
Simulation time 5307167293 ps
CPU time 38.54 seconds
Started Mar 21 01:18:46 PM PDT 24
Finished Mar 21 01:19:26 PM PDT 24
Peak memory 520564 kb
Host smart-a7a0c787-6696-4815-bcea-b67b30d01670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571253660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3571253660
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3342117508
Short name T976
Test name
Test status
Simulation time 549480807 ps
CPU time 0.92 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:00 PM PDT 24
Peak memory 203100 kb
Host smart-21ad64cf-88ff-4869-9d3e-87ef033b4887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342117508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3342117508
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1568372973
Short name T302
Test name
Test status
Simulation time 147662724 ps
CPU time 4.02 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 228052 kb
Host smart-e765eb6c-3d12-435a-b126-df93beab00f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568372973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1568372973
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3231040619
Short name T566
Test name
Test status
Simulation time 5512129606 ps
CPU time 189.22 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:21:58 PM PDT 24
Peak memory 875472 kb
Host smart-bbcd796a-97b6-44d2-9155-939e654eae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231040619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3231040619
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_override.3340315001
Short name T266
Test name
Test status
Simulation time 18366785 ps
CPU time 0.64 seconds
Started Mar 21 01:18:48 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 202480 kb
Host smart-ad43ad32-b2f1-4d97-9f66-fd6accab0749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340315001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3340315001
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2001508331
Short name T35
Test name
Test status
Simulation time 6449854318 ps
CPU time 76.34 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 384064 kb
Host smart-043b36c5-a926-4e27-80eb-10b20b8c9909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001508331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2001508331
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1600936127
Short name T610
Test name
Test status
Simulation time 1433698702 ps
CPU time 50.27 seconds
Started Mar 21 01:18:46 PM PDT 24
Finished Mar 21 01:19:36 PM PDT 24
Peak memory 341436 kb
Host smart-ba76a669-13b0-494b-98ec-74461429325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600936127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1600936127
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.560735017
Short name T921
Test name
Test status
Simulation time 1074376200 ps
CPU time 3.73 seconds
Started Mar 21 01:19:00 PM PDT 24
Finished Mar 21 01:19:04 PM PDT 24
Peak memory 211628 kb
Host smart-3ce3737f-9613-42e3-a746-4c0ee02b172f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560735017 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.560735017
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.4044591356
Short name T1063
Test name
Test status
Simulation time 10298354149 ps
CPU time 22.66 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:23 PM PDT 24
Peak memory 359356 kb
Host smart-0c86b0b5-9be6-4abc-b7f2-1ddb534db1f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044591356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.4044591356
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2319402956
Short name T190
Test name
Test status
Simulation time 10108056644 ps
CPU time 86.27 seconds
Started Mar 21 01:19:02 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 704960 kb
Host smart-35b6906c-a93c-422f-8107-faa3cf715c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319402956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2319402956
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3414242128
Short name T974
Test name
Test status
Simulation time 672483368 ps
CPU time 2.13 seconds
Started Mar 21 01:19:00 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 203448 kb
Host smart-d8e2ebd4-312f-4802-a914-efdd9c123811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414242128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3414242128
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2972964248
Short name T361
Test name
Test status
Simulation time 822732400 ps
CPU time 4.26 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 203328 kb
Host smart-91096b76-1b6e-41b9-b00a-898bbdfc75e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972964248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2972964248
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.945933820
Short name T573
Test name
Test status
Simulation time 6428195056 ps
CPU time 7.46 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 203444 kb
Host smart-005f3ba7-cf94-488c-a002-8444d21b737a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945933820 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.945933820
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4080065244
Short name T508
Test name
Test status
Simulation time 3556113934 ps
CPU time 33.79 seconds
Started Mar 21 01:18:55 PM PDT 24
Finished Mar 21 01:19:29 PM PDT 24
Peak memory 203348 kb
Host smart-83738f92-fb4f-49e9-950c-89516b16b7a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080065244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4080065244
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1449030989
Short name T437
Test name
Test status
Simulation time 1059494392 ps
CPU time 30.89 seconds
Started Mar 21 01:19:00 PM PDT 24
Finished Mar 21 01:19:31 PM PDT 24
Peak memory 203432 kb
Host smart-1d9fc49f-e573-48d3-88e0-b8cda73e937e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449030989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1449030989
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2401386201
Short name T678
Test name
Test status
Simulation time 26467307752 ps
CPU time 526.14 seconds
Started Mar 21 01:18:56 PM PDT 24
Finished Mar 21 01:27:42 PM PDT 24
Peak memory 1528068 kb
Host smart-f4a16800-e59f-4fcd-a9c0-df53bb881485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401386201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2401386201
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.775596609
Short name T769
Test name
Test status
Simulation time 6290544621 ps
CPU time 7.08 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:06 PM PDT 24
Peak memory 211536 kb
Host smart-fccb2da5-20d4-4be6-a678-bb31874fbf25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775596609 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.775596609
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.504834544
Short name T644
Test name
Test status
Simulation time 3117087776 ps
CPU time 5.66 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 203484 kb
Host smart-e7bfa8ff-6d4a-406a-95a5-1c6aec6e49d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504834544 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_unexp_stop.504834544
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3549483811
Short name T994
Test name
Test status
Simulation time 19126078 ps
CPU time 0.65 seconds
Started Mar 21 01:19:04 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 203080 kb
Host smart-666ba8c3-8d87-43ac-8056-d0878bad5921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549483811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3549483811
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2205827380
Short name T637
Test name
Test status
Simulation time 109584877 ps
CPU time 1.21 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:00 PM PDT 24
Peak memory 211440 kb
Host smart-cdef92f3-a680-4ab4-820d-3f0bbf231965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205827380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2205827380
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2726093946
Short name T260
Test name
Test status
Simulation time 1033147117 ps
CPU time 12.24 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:11 PM PDT 24
Peak memory 250816 kb
Host smart-0ddb86b7-485c-41db-b7ac-ac9dca60a1a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726093946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2726093946
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.675159531
Short name T718
Test name
Test status
Simulation time 1363320409 ps
CPU time 45.41 seconds
Started Mar 21 01:18:56 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 506404 kb
Host smart-862857d0-dc25-4a34-b924-355cbdea11b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675159531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.675159531
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3151130903
Short name T832
Test name
Test status
Simulation time 1220934544 ps
CPU time 73.47 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:20:11 PM PDT 24
Peak memory 358520 kb
Host smart-94de7c53-f23b-4b4d-bab5-1ed36d846b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151130903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3151130903
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.737812340
Short name T595
Test name
Test status
Simulation time 693191913 ps
CPU time 0.91 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:00 PM PDT 24
Peak memory 203156 kb
Host smart-de4e0bfe-ad0d-4c66-93d7-4d9b04905837
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737812340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.737812340
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1833878226
Short name T264
Test name
Test status
Simulation time 170528699 ps
CPU time 3.84 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:19:02 PM PDT 24
Peak memory 203240 kb
Host smart-41306648-3d29-4544-8e52-ca39030ce0ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833878226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1833878226
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3449435285
Short name T142
Test name
Test status
Simulation time 9112782940 ps
CPU time 44.75 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 744324 kb
Host smart-e9f93b2d-190e-46d5-80a1-41ec5f14e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449435285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3449435285
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_override.1387155673
Short name T907
Test name
Test status
Simulation time 16429201 ps
CPU time 0.67 seconds
Started Mar 21 01:19:00 PM PDT 24
Finished Mar 21 01:19:00 PM PDT 24
Peak memory 202432 kb
Host smart-4f5abfa3-9540-4641-95c8-8c15e75615f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387155673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1387155673
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1617578341
Short name T715
Test name
Test status
Simulation time 1398003263 ps
CPU time 47.07 seconds
Started Mar 21 01:18:56 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 321448 kb
Host smart-b82e7b97-a5ea-49df-920b-19ccc6819ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617578341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1617578341
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.27505508
Short name T959
Test name
Test status
Simulation time 10773071226 ps
CPU time 334.55 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 1520296 kb
Host smart-928d3073-40d2-48c6-b24b-b453a4ed95e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27505508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.27505508
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3841026127
Short name T775
Test name
Test status
Simulation time 3320734232 ps
CPU time 3.38 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:19:01 PM PDT 24
Peak memory 211644 kb
Host smart-73c1bc2a-0dee-404d-8780-4e7949578c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841026127 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3841026127
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3316628425
Short name T944
Test name
Test status
Simulation time 10151150954 ps
CPU time 30.24 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:19:29 PM PDT 24
Peak memory 367428 kb
Host smart-c613d24f-728d-4776-83c9-178287b71a85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316628425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3316628425
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3135495936
Short name T625
Test name
Test status
Simulation time 10128045503 ps
CPU time 34.68 seconds
Started Mar 21 01:18:57 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 450488 kb
Host smart-7f3993cf-0414-4381-9062-973f4d360deb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135495936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3135495936
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3671167791
Short name T43
Test name
Test status
Simulation time 534084630 ps
CPU time 2.97 seconds
Started Mar 21 01:19:05 PM PDT 24
Finished Mar 21 01:19:08 PM PDT 24
Peak memory 203308 kb
Host smart-e02c37f3-eacb-4606-89ca-c20402d89066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671167791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3671167791
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.703200224
Short name T1016
Test name
Test status
Simulation time 1099989242 ps
CPU time 4.99 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:06 PM PDT 24
Peak memory 203376 kb
Host smart-86aed2c4-6902-4dff-b0a7-306974d50d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703200224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.703200224
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.4235571178
Short name T292
Test name
Test status
Simulation time 3944060005 ps
CPU time 39.47 seconds
Started Mar 21 01:19:04 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 203428 kb
Host smart-ca792bf0-62a8-4ef0-910f-097d9cefa3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235571178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.4235571178
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.4263880323
Short name T400
Test name
Test status
Simulation time 5662844480 ps
CPU time 16.74 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:18 PM PDT 24
Peak memory 223440 kb
Host smart-05d607ee-160f-4143-8aae-f3750b50f816
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263880323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.4263880323
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3589814046
Short name T1084
Test name
Test status
Simulation time 18483298549 ps
CPU time 33.11 seconds
Started Mar 21 01:18:59 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203344 kb
Host smart-9eaaf52f-b390-41e8-8212-034ff526def6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589814046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3589814046
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3882326547
Short name T1023
Test name
Test status
Simulation time 35101368424 ps
CPU time 818.68 seconds
Started Mar 21 01:19:00 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 4067352 kb
Host smart-a6ca641f-362a-4f1e-9513-b72c4c8def79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882326547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3882326547
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2418648463
Short name T534
Test name
Test status
Simulation time 5445028986 ps
CPU time 6.68 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:19:04 PM PDT 24
Peak memory 203336 kb
Host smart-29d99f19-fada-44f8-b18e-ad7b23fa21ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418648463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2418648463
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3510286807
Short name T267
Test name
Test status
Simulation time 17123869 ps
CPU time 0.63 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 203068 kb
Host smart-a44b2d05-0beb-4492-8944-9175538f5780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510286807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3510286807
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.398254276
Short name T809
Test name
Test status
Simulation time 118258816 ps
CPU time 1.63 seconds
Started Mar 21 01:19:02 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 211488 kb
Host smart-a1632a5b-2e28-48dd-845c-1387ee25bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398254276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.398254276
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.113845465
Short name T1043
Test name
Test status
Simulation time 383332300 ps
CPU time 6.03 seconds
Started Mar 21 01:19:04 PM PDT 24
Finished Mar 21 01:19:11 PM PDT 24
Peak memory 264776 kb
Host smart-6fd519d1-13bd-4c80-946b-fd5f13798c8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113845465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.113845465
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2574502185
Short name T821
Test name
Test status
Simulation time 1975042432 ps
CPU time 162 seconds
Started Mar 21 01:19:02 PM PDT 24
Finished Mar 21 01:21:44 PM PDT 24
Peak memory 688760 kb
Host smart-7f15c640-86fc-4f81-9374-579143b1397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574502185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2574502185
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.833421511
Short name T404
Test name
Test status
Simulation time 10160956860 ps
CPU time 48.35 seconds
Started Mar 21 01:19:05 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 600508 kb
Host smart-fee347b3-4b95-4f74-9fc5-a38f73139d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833421511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.833421511
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3043285216
Short name T732
Test name
Test status
Simulation time 357306325 ps
CPU time 0.98 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:18:59 PM PDT 24
Peak memory 203232 kb
Host smart-e969e49f-b2a4-40cb-a8a6-461e92eb3f73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043285216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3043285216
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3423142529
Short name T802
Test name
Test status
Simulation time 1236088462 ps
CPU time 6.21 seconds
Started Mar 21 01:19:05 PM PDT 24
Finished Mar 21 01:19:11 PM PDT 24
Peak memory 203224 kb
Host smart-31b2cda2-e5ba-43c9-851b-2cb2d5c9b298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423142529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3423142529
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_override.2376267658
Short name T877
Test name
Test status
Simulation time 17555690 ps
CPU time 0.66 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:02 PM PDT 24
Peak memory 202516 kb
Host smart-7983bba9-d289-4b5f-af27-fe6faed9adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376267658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2376267658
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1615106714
Short name T428
Test name
Test status
Simulation time 5366661730 ps
CPU time 132.75 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:21:14 PM PDT 24
Peak memory 211576 kb
Host smart-a0269376-b717-48f3-8bc3-d5703864dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615106714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1615106714
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1335379594
Short name T661
Test name
Test status
Simulation time 2717608299 ps
CPU time 91.43 seconds
Started Mar 21 01:18:58 PM PDT 24
Finished Mar 21 01:20:29 PM PDT 24
Peak memory 246948 kb
Host smart-cc655bfe-119a-41a7-9d86-b6050ce3436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335379594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1335379594
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1333456675
Short name T709
Test name
Test status
Simulation time 1529172419 ps
CPU time 3.32 seconds
Started Mar 21 01:19:21 PM PDT 24
Finished Mar 21 01:19:24 PM PDT 24
Peak memory 203420 kb
Host smart-2ea49915-26f9-43f4-9076-768ba1da8b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333456675 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1333456675
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3769326734
Short name T323
Test name
Test status
Simulation time 10078778813 ps
CPU time 29.25 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:47 PM PDT 24
Peak memory 403420 kb
Host smart-1c69013c-58de-4f57-91b1-481361d4289d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769326734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3769326734
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.468256793
Short name T537
Test name
Test status
Simulation time 10073890489 ps
CPU time 105.22 seconds
Started Mar 21 01:19:19 PM PDT 24
Finished Mar 21 01:21:04 PM PDT 24
Peak memory 729412 kb
Host smart-20e26a50-bb5b-4c27-a45d-1f5e30263ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468256793 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.468256793
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.798812176
Short name T575
Test name
Test status
Simulation time 639740954 ps
CPU time 2.28 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 203328 kb
Host smart-7ec6332d-cd3d-4b1b-aebd-e32bbc0f79a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798812176 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.798812176
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1585533862
Short name T894
Test name
Test status
Simulation time 817271505 ps
CPU time 3.88 seconds
Started Mar 21 01:19:01 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 203276 kb
Host smart-2e7df9a4-396e-4a84-8160-e79ffb13d5e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585533862 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1585533862
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.937638809
Short name T936
Test name
Test status
Simulation time 2339599756 ps
CPU time 41.31 seconds
Started Mar 21 01:19:02 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 203124 kb
Host smart-b6b37147-210b-430f-b0ae-09ad79a977bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937638809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.937638809
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3532686358
Short name T512
Test name
Test status
Simulation time 4263652321 ps
CPU time 12.72 seconds
Started Mar 21 01:19:04 PM PDT 24
Finished Mar 21 01:19:17 PM PDT 24
Peak memory 207052 kb
Host smart-515eee11-10f8-4e87-9061-3dd26310a91b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532686358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3532686358
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1746932763
Short name T1080
Test name
Test status
Simulation time 22888274898 ps
CPU time 1704.76 seconds
Started Mar 21 01:19:02 PM PDT 24
Finished Mar 21 01:47:27 PM PDT 24
Peak memory 5677820 kb
Host smart-d6781bf1-3f5c-4982-a92c-7019bf83551d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746932763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1746932763
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2963310284
Short name T8
Test name
Test status
Simulation time 6056825007 ps
CPU time 7.2 seconds
Started Mar 21 01:19:20 PM PDT 24
Finished Mar 21 01:19:27 PM PDT 24
Peak memory 219592 kb
Host smart-0c4504b4-9142-4651-b6d4-9b258c41dbba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963310284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2963310284
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3842738776
Short name T417
Test name
Test status
Simulation time 24952255 ps
CPU time 0.62 seconds
Started Mar 21 01:19:19 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 203112 kb
Host smart-eb555bad-179e-45f8-a1ae-5e7bdfdc6bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842738776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3842738776
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2375043935
Short name T830
Test name
Test status
Simulation time 146987531 ps
CPU time 1.29 seconds
Started Mar 21 01:19:20 PM PDT 24
Finished Mar 21 01:19:21 PM PDT 24
Peak memory 211480 kb
Host smart-e39d2108-085c-477e-a451-74775e0d5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375043935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2375043935
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2278359684
Short name T105
Test name
Test status
Simulation time 454239824 ps
CPU time 5.91 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:23 PM PDT 24
Peak memory 221296 kb
Host smart-1c58aef0-f8ca-43b1-9c4d-006d10a2fec4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278359684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2278359684
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1669327390
Short name T447
Test name
Test status
Simulation time 3842758540 ps
CPU time 39 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:56 PM PDT 24
Peak memory 262532 kb
Host smart-ee17aefb-8d59-4e62-97d5-c9a22acc3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669327390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1669327390
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.974439461
Short name T783
Test name
Test status
Simulation time 4270883513 ps
CPU time 75.5 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:20:34 PM PDT 24
Peak memory 480328 kb
Host smart-666694ee-f734-487e-ba51-bc685af258eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974439461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.974439461
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.824711251
Short name T878
Test name
Test status
Simulation time 351219823 ps
CPU time 1.2 seconds
Started Mar 21 01:19:16 PM PDT 24
Finished Mar 21 01:19:17 PM PDT 24
Peak memory 203372 kb
Host smart-c26d771f-09d9-435f-b344-944b54ab0c44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824711251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.824711251
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.525361618
Short name T617
Test name
Test status
Simulation time 650813881 ps
CPU time 3.63 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:21 PM PDT 24
Peak memory 221484 kb
Host smart-9c0859ea-59e0-4d45-b3ae-6f7d8b89c88e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525361618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
525361618
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3607353273
Short name T649
Test name
Test status
Simulation time 2890540260 ps
CPU time 71.14 seconds
Started Mar 21 01:19:21 PM PDT 24
Finished Mar 21 01:20:32 PM PDT 24
Peak memory 811064 kb
Host smart-ff5bfec6-51e0-45cb-8816-1e12c0eceeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607353273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3607353273
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_override.365525119
Short name T934
Test name
Test status
Simulation time 27720717 ps
CPU time 0.64 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 202472 kb
Host smart-565ef933-cbe9-482f-bfc2-8b37989e648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365525119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.365525119
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2946487237
Short name T937
Test name
Test status
Simulation time 6979832095 ps
CPU time 798.42 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:32:37 PM PDT 24
Peak memory 837588 kb
Host smart-8b1689af-7644-4831-8e64-692396bf50be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946487237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2946487237
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.865659537
Short name T359
Test name
Test status
Simulation time 3715829193 ps
CPU time 26.92 seconds
Started Mar 21 01:19:15 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 280272 kb
Host smart-84b27161-b8ea-4428-98ee-ede51b18b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865659537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.865659537
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.949681309
Short name T601
Test name
Test status
Simulation time 2176444768 ps
CPU time 3 seconds
Started Mar 21 01:19:17 PM PDT 24
Finished Mar 21 01:19:20 PM PDT 24
Peak memory 203392 kb
Host smart-661ec20b-2206-4809-af8a-7cc530964a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949681309 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.949681309
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3266146988
Short name T847
Test name
Test status
Simulation time 10101480871 ps
CPU time 96.42 seconds
Started Mar 21 01:19:16 PM PDT 24
Finished Mar 21 01:20:52 PM PDT 24
Peak memory 629644 kb
Host smart-45689bd5-15e6-437e-8e7b-d29b916614c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266146988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3266146988
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3036828259
Short name T655
Test name
Test status
Simulation time 10668167082 ps
CPU time 4.03 seconds
Started Mar 21 01:19:21 PM PDT 24
Finished Mar 21 01:19:25 PM PDT 24
Peak memory 227892 kb
Host smart-7424ac3c-6f6a-4d89-a031-2224b4d76abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036828259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3036828259
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3288803150
Short name T747
Test name
Test status
Simulation time 415109063 ps
CPU time 2.63 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:19:21 PM PDT 24
Peak memory 203324 kb
Host smart-b75466d9-b77c-41d8-b572-9ea6525d0c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288803150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3288803150
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.4037402515
Short name T1038
Test name
Test status
Simulation time 1479583958 ps
CPU time 3.99 seconds
Started Mar 21 01:19:18 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 206316 kb
Host smart-1f73d904-1e16-4040-a37a-05fd728cdcb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037402515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.4037402515
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2118399008
Short name T954
Test name
Test status
Simulation time 3803731364 ps
CPU time 10.86 seconds
Started Mar 21 01:19:15 PM PDT 24
Finished Mar 21 01:19:26 PM PDT 24
Peak memory 203440 kb
Host smart-38406d8c-e0a3-4ddf-bf28-d4b72ac0c710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118399008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2118399008
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2578661255
Short name T408
Test name
Test status
Simulation time 566493727 ps
CPU time 10.66 seconds
Started Mar 21 01:19:20 PM PDT 24
Finished Mar 21 01:19:31 PM PDT 24
Peak memory 206616 kb
Host smart-3a4837c7-6f49-4809-ac48-3653f06391a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578661255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2578661255
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2958140740
Short name T379
Test name
Test status
Simulation time 35901066036 ps
CPU time 117.53 seconds
Started Mar 21 01:19:16 PM PDT 24
Finished Mar 21 01:21:14 PM PDT 24
Peak memory 1031080 kb
Host smart-4958c208-a173-4b4b-af0b-5921dd54d8ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958140740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2958140740
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.592844265
Short name T611
Test name
Test status
Simulation time 3716187951 ps
CPU time 6.12 seconds
Started Mar 21 01:19:20 PM PDT 24
Finished Mar 21 01:19:26 PM PDT 24
Peak memory 203480 kb
Host smart-1a381468-a5af-4e9e-a4b0-8ca910da0077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592844265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.592844265
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1792126122
Short name T789
Test name
Test status
Simulation time 18151514 ps
CPU time 0.62 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203032 kb
Host smart-eb432c74-c8a4-493e-abaa-192cea282944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792126122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1792126122
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.396803384
Short name T767
Test name
Test status
Simulation time 351063313 ps
CPU time 1.25 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:28 PM PDT 24
Peak memory 214676 kb
Host smart-145047f1-a9b4-4ade-a48b-7308590858b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396803384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.396803384
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.424856930
Short name T352
Test name
Test status
Simulation time 431497824 ps
CPU time 4.36 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:35 PM PDT 24
Peak memory 212628 kb
Host smart-53b80612-1420-4f76-a431-4a40e5eac009
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424856930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.424856930
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.401172808
Short name T15
Test name
Test status
Simulation time 6402710403 ps
CPU time 31.76 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:59 PM PDT 24
Peak memory 352772 kb
Host smart-c523bbf7-dfb3-470b-92c5-72326951bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401172808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.401172808
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.332034406
Short name T777
Test name
Test status
Simulation time 5964717824 ps
CPU time 103.55 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:21:13 PM PDT 24
Peak memory 560024 kb
Host smart-4ccfc40e-c5f9-4389-a185-f00609d03c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332034406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.332034406
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3504640664
Short name T112
Test name
Test status
Simulation time 129220622 ps
CPU time 1 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:28 PM PDT 24
Peak memory 202996 kb
Host smart-46935ec2-0de4-40cf-9764-2710037825db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504640664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3504640664
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2914449404
Short name T367
Test name
Test status
Simulation time 267860613 ps
CPU time 3.59 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 203192 kb
Host smart-54cb1036-fd8a-4949-ad90-a7b9f5f8c948
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914449404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2914449404
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1956578663
Short name T881
Test name
Test status
Simulation time 3828308378 ps
CPU time 307.28 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 1155196 kb
Host smart-f8de903f-5fd4-4cd9-bdd7-56cb3468067b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956578663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1956578663
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_override.409653078
Short name T275
Test name
Test status
Simulation time 57400847 ps
CPU time 0.62 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:19:30 PM PDT 24
Peak memory 202424 kb
Host smart-0d64a330-873b-4670-9082-51ac1c3e4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409653078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.409653078
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1313185549
Short name T854
Test name
Test status
Simulation time 169756142 ps
CPU time 3.96 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:36 PM PDT 24
Peak memory 220768 kb
Host smart-12c5ab69-cc96-4beb-a40c-e87ac83db662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313185549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1313185549
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3490617673
Short name T365
Test name
Test status
Simulation time 5087845468 ps
CPU time 47.68 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:20:19 PM PDT 24
Peak memory 298648 kb
Host smart-f8f51cf0-1713-4784-92a1-940a84a75949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490617673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3490617673
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3004033755
Short name T338
Test name
Test status
Simulation time 435242531 ps
CPU time 2.38 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203340 kb
Host smart-4fbf788e-cb6a-469d-aeac-55e3c7e0bf0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004033755 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3004033755
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1312937559
Short name T179
Test name
Test status
Simulation time 10174469936 ps
CPU time 30.53 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:57 PM PDT 24
Peak memory 357812 kb
Host smart-be27ff51-25ac-4d13-91a2-8bc77e177473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312937559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1312937559
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1108931093
Short name T491
Test name
Test status
Simulation time 10050515286 ps
CPU time 103.84 seconds
Started Mar 21 01:19:25 PM PDT 24
Finished Mar 21 01:21:09 PM PDT 24
Peak memory 749316 kb
Host smart-d6cd6f65-1431-4add-8670-a2b0f7d322e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108931093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1108931093
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.117871235
Short name T859
Test name
Test status
Simulation time 1200167214 ps
CPU time 1.77 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 203360 kb
Host smart-205eab9d-8c7d-4f37-a7bc-c4b583470797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117871235 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.117871235
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1866187536
Short name T101
Test name
Test status
Simulation time 757855714 ps
CPU time 3.41 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 203412 kb
Host smart-0d927c93-8e55-476c-a2b5-15cd534c079b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866187536 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1866187536
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.812285558
Short name T620
Test name
Test status
Simulation time 3091176727 ps
CPU time 11.05 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:19:39 PM PDT 24
Peak memory 203464 kb
Host smart-4e5e7919-da8e-4021-a607-357570667c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812285558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.812285558
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.61412372
Short name T1068
Test name
Test status
Simulation time 2019360568 ps
CPU time 7.65 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 207044 kb
Host smart-cdf6c559-8229-48bd-b0c6-1b39384a16a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61412372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stress_rd.61412372
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2263022989
Short name T699
Test name
Test status
Simulation time 5325678255 ps
CPU time 7.17 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:19:36 PM PDT 24
Peak memory 209652 kb
Host smart-ee733e57-6637-4914-803f-350a12a930a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263022989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2263022989
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2734780039
Short name T742
Test name
Test status
Simulation time 16588680 ps
CPU time 0.58 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203028 kb
Host smart-d457e7fb-1dfa-43e3-958c-03901bf889a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734780039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2734780039
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.767494987
Short name T880
Test name
Test status
Simulation time 36006705 ps
CPU time 1.07 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:31 PM PDT 24
Peak memory 211492 kb
Host smart-a155bc94-7fc3-44ee-bbdf-8462b4ea2260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767494987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.767494987
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2765435265
Short name T1013
Test name
Test status
Simulation time 262829583 ps
CPU time 5.25 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 251528 kb
Host smart-23187e67-7e20-4c5a-9870-cd9f2c23a010
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765435265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2765435265
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.904199523
Short name T540
Test name
Test status
Simulation time 5675221194 ps
CPU time 46.22 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:20:16 PM PDT 24
Peak memory 556992 kb
Host smart-96508f1b-7b4a-4895-b454-fbc19572daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904199523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.904199523
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4108220295
Short name T1003
Test name
Test status
Simulation time 3729763365 ps
CPU time 134.14 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:21:42 PM PDT 24
Peak memory 649140 kb
Host smart-292cff09-6195-4b54-8535-53cc103efcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108220295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4108220295
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3571188629
Short name T460
Test name
Test status
Simulation time 163450628 ps
CPU time 1.12 seconds
Started Mar 21 01:19:33 PM PDT 24
Finished Mar 21 01:19:35 PM PDT 24
Peak memory 203212 kb
Host smart-3a1b7103-81cb-4177-9005-dc28a89a8c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571188629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3571188629
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1284735612
Short name T990
Test name
Test status
Simulation time 868834576 ps
CPU time 9.61 seconds
Started Mar 21 01:19:34 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 233460 kb
Host smart-6611c839-4fb6-4a60-b724-5b6ca09ef549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284735612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1284735612
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_override.684607434
Short name T781
Test name
Test status
Simulation time 62517353 ps
CPU time 0.64 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 202412 kb
Host smart-7a8101ae-cfb1-42eb-a32e-6f1b9d40b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684607434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.684607434
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1115949566
Short name T985
Test name
Test status
Simulation time 18353206466 ps
CPU time 1186.61 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:39:14 PM PDT 24
Peak memory 530412 kb
Host smart-236f0396-b409-431d-a53a-962049c61cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115949566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1115949566
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3112038517
Short name T310
Test name
Test status
Simulation time 2312284122 ps
CPU time 34.56 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:20:02 PM PDT 24
Peak memory 292304 kb
Host smart-cb91e40c-c3f9-4e04-bfc6-9282e040ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112038517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3112038517
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.595620637
Short name T679
Test name
Test status
Simulation time 3900389168 ps
CPU time 4.81 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:37 PM PDT 24
Peak memory 203420 kb
Host smart-3f22c8fc-c722-4896-9a65-25b8bdf5ffc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595620637 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.595620637
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4201507241
Short name T514
Test name
Test status
Simulation time 10096361739 ps
CPU time 35.74 seconds
Started Mar 21 01:19:36 PM PDT 24
Finished Mar 21 01:20:12 PM PDT 24
Peak memory 427864 kb
Host smart-03bcc113-cabe-40c7-a51d-ba1591baa3c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201507241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4201507241
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1859009794
Short name T456
Test name
Test status
Simulation time 10363683388 ps
CPU time 15.38 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:45 PM PDT 24
Peak memory 347184 kb
Host smart-2d8a04bc-938e-460d-bf99-f70b85a466ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859009794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1859009794
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1901417125
Short name T538
Test name
Test status
Simulation time 987309259 ps
CPU time 2.23 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 203288 kb
Host smart-15d87492-99e8-40fc-b3fb-b4c1bf514e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901417125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1901417125
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.19930151
Short name T477
Test name
Test status
Simulation time 4214302861 ps
CPU time 4.88 seconds
Started Mar 21 01:19:26 PM PDT 24
Finished Mar 21 01:19:31 PM PDT 24
Peak memory 211536 kb
Host smart-0d540c4b-4c98-4f41-a03f-b87e7376e4e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930151 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.19930151
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.379026205
Short name T280
Test name
Test status
Simulation time 14802728939 ps
CPU time 61.24 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:20:33 PM PDT 24
Peak memory 203420 kb
Host smart-5a7d10e7-788f-4e39-a801-67f5caff80da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379026205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.379026205
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.4171257639
Short name T988
Test name
Test status
Simulation time 3878491539 ps
CPU time 16.53 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:19:46 PM PDT 24
Peak memory 219804 kb
Host smart-257a46d0-c13e-4083-9e62-bf77a8713efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171257639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.4171257639
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.812882030
Short name T327
Test name
Test status
Simulation time 6261040022 ps
CPU time 231.75 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 1012492 kb
Host smart-bf695980-cb1c-4f78-ae30-444565f7170c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812882030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.812882030
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2211832713
Short name T829
Test name
Test status
Simulation time 2632691390 ps
CPU time 6.46 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:19:36 PM PDT 24
Peak memory 219628 kb
Host smart-1577b269-44f6-45e3-b7a2-0ca67764dbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211832713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2211832713
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1694987024
Short name T362
Test name
Test status
Simulation time 15888368 ps
CPU time 0.62 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203032 kb
Host smart-debe86b7-ed9e-40eb-ab32-98367d0ffba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694987024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1694987024
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.673883665
Short name T484
Test name
Test status
Simulation time 213966418 ps
CPU time 1.57 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:33 PM PDT 24
Peak memory 219732 kb
Host smart-f50a689a-4c16-4b9b-822f-a92f4c02fa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673883665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.673883665
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1201366871
Short name T70
Test name
Test status
Simulation time 447838604 ps
CPU time 5.18 seconds
Started Mar 21 01:19:33 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 242620 kb
Host smart-ab070090-0c9f-4658-ae5a-c39de0ac00ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201366871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1201366871
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1522580485
Short name T890
Test name
Test status
Simulation time 4551821232 ps
CPU time 144.85 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:21:57 PM PDT 24
Peak memory 636828 kb
Host smart-1ce9cb4e-2d34-4e48-a5cf-645a9e6b6d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522580485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1522580485
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3275810219
Short name T556
Test name
Test status
Simulation time 3485485095 ps
CPU time 127.36 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 610744 kb
Host smart-19cc4e1e-1a13-4561-a335-be25df20c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275810219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3275810219
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2561984771
Short name T966
Test name
Test status
Simulation time 301954244 ps
CPU time 1.02 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:33 PM PDT 24
Peak memory 203136 kb
Host smart-baad5e44-babb-40c0-86f9-de2ce643b8a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561984771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2561984771
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3513836789
Short name T706
Test name
Test status
Simulation time 312444600 ps
CPU time 3.92 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203296 kb
Host smart-7a1a6215-15a4-4534-b34d-e2b1052bf951
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513836789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3513836789
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.740614897
Short name T813
Test name
Test status
Simulation time 4602128503 ps
CPU time 143.35 seconds
Started Mar 21 01:19:33 PM PDT 24
Finished Mar 21 01:21:56 PM PDT 24
Peak memory 1290840 kb
Host smart-a03d6996-2de7-40a3-afe4-a88429024685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740614897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.740614897
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_override.3135042309
Short name T946
Test name
Test status
Simulation time 51404554 ps
CPU time 0.62 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:33 PM PDT 24
Peak memory 202428 kb
Host smart-3781e91d-6b80-41ed-a30e-a9c46c9ab813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135042309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3135042309
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1281889834
Short name T645
Test name
Test status
Simulation time 7459857178 ps
CPU time 144.66 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:21:56 PM PDT 24
Peak memory 322184 kb
Host smart-bec70ad4-4c50-485f-91ac-d378d9a24537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281889834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1281889834
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.4110532592
Short name T642
Test name
Test status
Simulation time 1503370064 ps
CPU time 54.91 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:20:23 PM PDT 24
Peak memory 325040 kb
Host smart-36f28a42-aec5-4631-a659-365489cef37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110532592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.4110532592
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2175616614
Short name T1027
Test name
Test status
Simulation time 990023733 ps
CPU time 4.35 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 211500 kb
Host smart-c14d1099-5774-4cb0-be2f-12f75c8ccddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175616614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2175616614
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3595879501
Short name T647
Test name
Test status
Simulation time 10460794181 ps
CPU time 14.04 seconds
Started Mar 21 01:19:35 PM PDT 24
Finished Mar 21 01:19:49 PM PDT 24
Peak memory 292688 kb
Host smart-67ef8f8e-f54e-49df-94b2-e8eb61388aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595879501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3595879501
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3465342419
Short name T932
Test name
Test status
Simulation time 10333820875 ps
CPU time 16.6 seconds
Started Mar 21 01:19:35 PM PDT 24
Finished Mar 21 01:19:52 PM PDT 24
Peak memory 334512 kb
Host smart-b6175a59-3a49-4d46-a230-1ae8fceb0b18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465342419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3465342419
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1898562979
Short name T910
Test name
Test status
Simulation time 581296611 ps
CPU time 2.72 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:33 PM PDT 24
Peak memory 203300 kb
Host smart-20ca3fca-933d-4b1a-b1b1-d93c83520cec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898562979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1898562979
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3871061264
Short name T528
Test name
Test status
Simulation time 928164955 ps
CPU time 4.93 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:35 PM PDT 24
Peak memory 211532 kb
Host smart-c6df756c-1b91-4cef-a1d5-99a1fffe1af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871061264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3871061264
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2320683857
Short name T507
Test name
Test status
Simulation time 836666409 ps
CPU time 32.82 seconds
Started Mar 21 01:19:35 PM PDT 24
Finished Mar 21 01:20:08 PM PDT 24
Peak memory 203320 kb
Host smart-6ad288ac-0429-4174-b2c6-87a735ede940
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320683857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2320683857
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2674397227
Short name T580
Test name
Test status
Simulation time 13412175389 ps
CPU time 41.34 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:20:14 PM PDT 24
Peak memory 206264 kb
Host smart-621a153d-1d2e-4e06-833a-e36141f14b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674397227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2674397227
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3489560187
Short name T521
Test name
Test status
Simulation time 16771112265 ps
CPU time 78.43 seconds
Started Mar 21 01:19:35 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 873184 kb
Host smart-55916f20-4906-4d81-afe6-5a16c9266c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489560187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3489560187
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3308723760
Short name T470
Test name
Test status
Simulation time 1682308352 ps
CPU time 7.74 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 216424 kb
Host smart-da5ccfce-7e33-4c79-9557-35a402ebb807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308723760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3308723760
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3781776069
Short name T1012
Test name
Test status
Simulation time 29523474 ps
CPU time 0.61 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 203168 kb
Host smart-a0bdc306-0957-4f28-8bec-616dca3ae39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781776069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3781776069
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3427798544
Short name T1004
Test name
Test status
Simulation time 41262781 ps
CPU time 1.19 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 211528 kb
Host smart-7b9e99de-8548-4837-a13c-22e594adbbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427798544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3427798544
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3903477577
Short name T672
Test name
Test status
Simulation time 816015709 ps
CPU time 22.32 seconds
Started Mar 21 01:19:27 PM PDT 24
Finished Mar 21 01:19:49 PM PDT 24
Peak memory 290640 kb
Host smart-99faf3be-2b3e-44d9-8e35-be7d04de61eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903477577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3903477577
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.977403577
Short name T1050
Test name
Test status
Simulation time 28951276294 ps
CPU time 185.08 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:22:34 PM PDT 24
Peak memory 781052 kb
Host smart-90d91c84-fe9c-48b2-8ed0-c1c5c932d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977403577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.977403577
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2901927774
Short name T461
Test name
Test status
Simulation time 8206962997 ps
CPU time 53.2 seconds
Started Mar 21 01:19:35 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 591868 kb
Host smart-4cc95047-639a-4b43-a5fb-447ba7dd07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901927774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2901927774
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2270391532
Short name T598
Test name
Test status
Simulation time 415615674 ps
CPU time 1.06 seconds
Started Mar 21 01:19:30 PM PDT 24
Finished Mar 21 01:19:31 PM PDT 24
Peak memory 203364 kb
Host smart-a583e466-c071-4b9d-8798-0d4ef2acb908
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270391532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2270391532
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3994508693
Short name T354
Test name
Test status
Simulation time 613778700 ps
CPU time 3.9 seconds
Started Mar 21 01:19:28 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 203236 kb
Host smart-5a84d4c5-b902-439a-94cd-788ca7248b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994508693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3994508693
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3857194982
Short name T436
Test name
Test status
Simulation time 10614414129 ps
CPU time 217 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:23:07 PM PDT 24
Peak memory 916920 kb
Host smart-1b76f569-7149-449e-981c-df82a26fbca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857194982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3857194982
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_override.50042478
Short name T295
Test name
Test status
Simulation time 28203129 ps
CPU time 0.61 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:19:30 PM PDT 24
Peak memory 202460 kb
Host smart-b2a3bd5d-6a15-4ed7-9aeb-4e2f3d13532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50042478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.50042478
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.983689113
Short name T509
Test name
Test status
Simulation time 3160016844 ps
CPU time 1182.52 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:39:14 PM PDT 24
Peak memory 608460 kb
Host smart-50dfb6ba-65ec-46ec-8597-53f1a4f97ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983689113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.983689113
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1989333605
Short name T405
Test name
Test status
Simulation time 1696569126 ps
CPU time 130.43 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:21:42 PM PDT 24
Peak memory 282696 kb
Host smart-88480057-a3a6-4e95-99b7-febbb8630abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989333605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1989333605
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.187795061
Short name T196
Test name
Test status
Simulation time 46440386597 ps
CPU time 2499.31 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 2690884 kb
Host smart-1dfd6fcb-d7b8-4046-9021-768861dca7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187795061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.187795061
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.135682081
Short name T467
Test name
Test status
Simulation time 1278564527 ps
CPU time 4.77 seconds
Started Mar 21 01:19:33 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 203304 kb
Host smart-892e2ad9-381e-4ab0-a643-f26c3ec83f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135682081 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.135682081
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2198172689
Short name T903
Test name
Test status
Simulation time 10035235692 ps
CPU time 75.99 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:20:47 PM PDT 24
Peak memory 593032 kb
Host smart-f370d013-9022-48e7-8c17-bdcfe235be8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198172689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2198172689
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2665091760
Short name T256
Test name
Test status
Simulation time 10214006585 ps
CPU time 16.14 seconds
Started Mar 21 01:19:33 PM PDT 24
Finished Mar 21 01:19:49 PM PDT 24
Peak memory 327864 kb
Host smart-f10fdf2e-eb8f-4fd0-b41c-3bbb528eee21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665091760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2665091760
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1175341698
Short name T872
Test name
Test status
Simulation time 4248707643 ps
CPU time 2.64 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:19:50 PM PDT 24
Peak memory 203464 kb
Host smart-e653cc95-9644-41c7-a067-355e23bd3568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175341698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1175341698
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3756925482
Short name T454
Test name
Test status
Simulation time 3128448206 ps
CPU time 4.16 seconds
Started Mar 21 01:19:31 PM PDT 24
Finished Mar 21 01:19:36 PM PDT 24
Peak memory 203876 kb
Host smart-cf5a8baf-02d7-4730-b66f-98932ff63f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756925482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3756925482
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.647913805
Short name T603
Test name
Test status
Simulation time 856446451 ps
CPU time 14.19 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:47 PM PDT 24
Peak memory 203312 kb
Host smart-9651b25f-a92e-415c-a7b7-52f7ae2008bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647913805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.647913805
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3295137099
Short name T933
Test name
Test status
Simulation time 1980506559 ps
CPU time 53.16 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 205072 kb
Host smart-70b6b870-2bc7-409c-81dc-1e4f7fbac55c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295137099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3295137099
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2708253475
Short name T1067
Test name
Test status
Simulation time 19504516430 ps
CPU time 816.12 seconds
Started Mar 21 01:19:29 PM PDT 24
Finished Mar 21 01:33:06 PM PDT 24
Peak memory 4006352 kb
Host smart-cbe4d5a6-c593-4dd1-b195-dcac8a1f7e3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708253475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2708253475
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1417487008
Short name T276
Test name
Test status
Simulation time 9115869720 ps
CPU time 6.1 seconds
Started Mar 21 01:19:32 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 203352 kb
Host smart-393f755c-b183-47b7-a5a8-bdc8c0261d1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417487008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1417487008
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.667844867
Short name T89
Test name
Test status
Simulation time 42698499 ps
CPU time 0.62 seconds
Started Mar 21 01:19:39 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 203096 kb
Host smart-e0e438b1-25b1-40fd-9cb8-038025b8d879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667844867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.667844867
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.96100146
Short name T887
Test name
Test status
Simulation time 57842532 ps
CPU time 1.54 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 211540 kb
Host smart-69b5dc86-93bb-42e8-ac38-e7428de827d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96100146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.96100146
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.418780852
Short name T1008
Test name
Test status
Simulation time 487063283 ps
CPU time 5.37 seconds
Started Mar 21 01:19:37 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 248900 kb
Host smart-5e59fe34-dc70-42ba-9b6a-760645d343c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418780852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.418780852
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.795874779
Short name T550
Test name
Test status
Simulation time 2634599539 ps
CPU time 34.09 seconds
Started Mar 21 01:19:47 PM PDT 24
Finished Mar 21 01:20:22 PM PDT 24
Peak memory 318748 kb
Host smart-e2a3a32f-b64a-420d-bf42-8de75ad7a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795874779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.795874779
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2502543015
Short name T524
Test name
Test status
Simulation time 4316228026 ps
CPU time 76.28 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:21:07 PM PDT 24
Peak memory 719720 kb
Host smart-5b04342e-eb68-41ba-9ff4-5c1b14d1e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502543015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2502543015
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3325318641
Short name T741
Test name
Test status
Simulation time 153010130 ps
CPU time 1.11 seconds
Started Mar 21 01:19:41 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 203240 kb
Host smart-32285cfa-40ad-4851-bab6-5ce0c0363756
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325318641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3325318641
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.26271
Short name T71
Test name
Test status
Simulation time 174271652 ps
CPU time 8.93 seconds
Started Mar 21 01:19:44 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 203240 kb
Host smart-be25cbca-f3fe-4048-be74-9593a799d4c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.26271
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_override.3276203990
Short name T1000
Test name
Test status
Simulation time 18247636 ps
CPU time 0.64 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:19:48 PM PDT 24
Peak memory 202440 kb
Host smart-6c37d812-1eea-4e94-87fc-bf2eb9185af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276203990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3276203990
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.434444751
Short name T181
Test name
Test status
Simulation time 300643120 ps
CPU time 2.61 seconds
Started Mar 21 01:19:40 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 227684 kb
Host smart-01e54ac1-d88f-49ba-8bdd-3a81bc08241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434444751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.434444751
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1411586986
Short name T652
Test name
Test status
Simulation time 22631058805 ps
CPU time 69 seconds
Started Mar 21 01:19:39 PM PDT 24
Finished Mar 21 01:20:48 PM PDT 24
Peak memory 342284 kb
Host smart-9a67b5bf-366a-4ad7-80c2-27570a796077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411586986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1411586986
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2145932051
Short name T377
Test name
Test status
Simulation time 702701488 ps
CPU time 3.52 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 203436 kb
Host smart-dcae2f74-9554-42dd-abe7-dac57f84ff77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145932051 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2145932051
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2628064271
Short name T457
Test name
Test status
Simulation time 10081195346 ps
CPU time 32.79 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:20:11 PM PDT 24
Peak memory 373568 kb
Host smart-e07c123e-5d73-491f-bd63-3ef68ca5f9cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628064271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2628064271
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.283116559
Short name T286
Test name
Test status
Simulation time 10034155577 ps
CPU time 96.35 seconds
Started Mar 21 01:19:43 PM PDT 24
Finished Mar 21 01:21:19 PM PDT 24
Peak memory 737856 kb
Host smart-7b8fb70d-109d-45b0-9237-37515a4c0cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283116559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.283116559
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1311346533
Short name T731
Test name
Test status
Simulation time 2573236640 ps
CPU time 2.36 seconds
Started Mar 21 01:19:42 PM PDT 24
Finished Mar 21 01:19:45 PM PDT 24
Peak memory 203400 kb
Host smart-59b0abbf-d576-4e4f-9bd1-6888742c5d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311346533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1311346533
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2780789815
Short name T431
Test name
Test status
Simulation time 937728419 ps
CPU time 5.38 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:19:59 PM PDT 24
Peak memory 213252 kb
Host smart-e5a7714d-dac2-4f06-aa7c-14b15ea01e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780789815 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2780789815
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3745910168
Short name T914
Test name
Test status
Simulation time 948293588 ps
CPU time 13.14 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:20:03 PM PDT 24
Peak memory 203164 kb
Host smart-a4513127-3db3-4ea2-b058-ef14b5c588e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745910168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3745910168
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.684337093
Short name T1060
Test name
Test status
Simulation time 10415329344 ps
CPU time 23.7 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:17 PM PDT 24
Peak memory 219360 kb
Host smart-9c3cb27d-b52f-4e21-b446-5cd93d9437e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684337093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.684337093
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.726322163
Short name T670
Test name
Test status
Simulation time 8387586999 ps
CPU time 30.31 seconds
Started Mar 21 01:19:36 PM PDT 24
Finished Mar 21 01:20:07 PM PDT 24
Peak memory 222448 kb
Host smart-aed6bc0f-bbec-4d01-9afd-bfcf99e4f8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726322163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.726322163
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.523019508
Short name T785
Test name
Test status
Simulation time 34361888576 ps
CPU time 2312.35 seconds
Started Mar 21 01:19:40 PM PDT 24
Finished Mar 21 01:58:14 PM PDT 24
Peak memory 7722528 kb
Host smart-0f590f82-c431-400a-9bf0-41526c210b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523019508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.523019508
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1400588488
Short name T308
Test name
Test status
Simulation time 4910632185 ps
CPU time 6.28 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:00 PM PDT 24
Peak memory 203168 kb
Host smart-31bf02f1-4b77-44f1-82a9-232ce5779c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400588488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1400588488
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2050985277
Short name T317
Test name
Test status
Simulation time 21911568 ps
CPU time 0.6 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:19:47 PM PDT 24
Peak memory 203124 kb
Host smart-b7efcea5-139f-4b9c-89a5-7afbefcc5111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050985277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2050985277
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1990231340
Short name T904
Test name
Test status
Simulation time 104176958 ps
CPU time 1.64 seconds
Started Mar 21 01:19:39 PM PDT 24
Finished Mar 21 01:19:41 PM PDT 24
Peak memory 211476 kb
Host smart-893b9e7f-ca27-4c09-bc9d-7181d51da259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990231340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1990231340
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2088781454
Short name T782
Test name
Test status
Simulation time 3336664288 ps
CPU time 16.24 seconds
Started Mar 21 01:19:42 PM PDT 24
Finished Mar 21 01:19:59 PM PDT 24
Peak memory 269420 kb
Host smart-48f46d92-8445-4e37-b6d1-bd121d8e1e66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088781454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2088781454
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.568703936
Short name T148
Test name
Test status
Simulation time 2012416720 ps
CPU time 144.77 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 683052 kb
Host smart-87632e1f-8226-40d2-bc13-849b63572bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568703936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.568703936
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.717969425
Short name T336
Test name
Test status
Simulation time 4076159764 ps
CPU time 61.12 seconds
Started Mar 21 01:19:41 PM PDT 24
Finished Mar 21 01:20:43 PM PDT 24
Peak memory 680908 kb
Host smart-3f8e0e5a-8f93-40af-8333-ae4ef1b4c2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717969425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.717969425
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3089787493
Short name T466
Test name
Test status
Simulation time 53152168 ps
CPU time 0.86 seconds
Started Mar 21 01:19:42 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 203108 kb
Host smart-48b87e74-c460-4f05-8c4f-a7ec94c4d6e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089787493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3089787493
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.4119089530
Short name T784
Test name
Test status
Simulation time 889004985 ps
CPU time 3.64 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 222464 kb
Host smart-36a5312f-e3fd-4058-815e-54ddf08013fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119089530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.4119089530
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2262582676
Short name T1014
Test name
Test status
Simulation time 2386467895 ps
CPU time 58.05 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 777696 kb
Host smart-16944886-1891-4a63-8a74-0634c2bace62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262582676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2262582676
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_override.706000820
Short name T18
Test name
Test status
Simulation time 44251495 ps
CPU time 0.67 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:19:39 PM PDT 24
Peak memory 202608 kb
Host smart-89b2be1f-5cd3-4cae-bf84-522c852efaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706000820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.706000820
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.272588089
Short name T738
Test name
Test status
Simulation time 17577628287 ps
CPU time 321.22 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 211472 kb
Host smart-ea0848e1-2e2c-4211-a9e0-cf15cb75c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272588089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.272588089
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3824346708
Short name T808
Test name
Test status
Simulation time 2396168707 ps
CPU time 73.24 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:21:03 PM PDT 24
Peak memory 380980 kb
Host smart-3ef543e6-f06b-4f0c-9899-209d5a9ce5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824346708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3824346708
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.668860113
Short name T519
Test name
Test status
Simulation time 1452338346 ps
CPU time 3.48 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 203312 kb
Host smart-d6098d30-bc1b-48d5-a753-598af5ada4bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668860113 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.668860113
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2060539665
Short name T68
Test name
Test status
Simulation time 10245743629 ps
CPU time 14.55 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:19:52 PM PDT 24
Peak memory 295424 kb
Host smart-5a4c7208-4f25-474e-bd1e-5e1ba459bd02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060539665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2060539665
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1785627894
Short name T613
Test name
Test status
Simulation time 10029685337 ps
CPU time 104.63 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:21:34 PM PDT 24
Peak memory 670600 kb
Host smart-6bf0dd6c-7903-4097-a625-a16c7e5bd053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785627894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1785627894
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2050767725
Short name T233
Test name
Test status
Simulation time 1366929199 ps
CPU time 1.98 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:19:51 PM PDT 24
Peak memory 203428 kb
Host smart-6149d9c9-a4a8-4e62-8cab-696b4866b879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050767725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2050767725
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.4208064946
Short name T951
Test name
Test status
Simulation time 2238987877 ps
CPU time 5.22 seconds
Started Mar 21 01:19:39 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 211600 kb
Host smart-401b5716-8277-45b3-9915-2da1c5d6fdca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208064946 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.4208064946
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1975521190
Short name T973
Test name
Test status
Simulation time 5421712366 ps
CPU time 23.45 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 203460 kb
Host smart-df3a2eea-b078-48b2-8e60-7fa2f0770b01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975521190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1975521190
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3954610241
Short name T636
Test name
Test status
Simulation time 3658014321 ps
CPU time 17.38 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:20:07 PM PDT 24
Peak memory 216172 kb
Host smart-2a493d34-f2f3-4e9c-a347-7353a0078f4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954610241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3954610241
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.4009852439
Short name T58
Test name
Test status
Simulation time 30329666234 ps
CPU time 3145.74 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 02:12:20 PM PDT 24
Peak memory 7225460 kb
Host smart-440d798d-f53e-4911-9d72-3b0d58152b6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009852439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.4009852439
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3848279796
Short name T754
Test name
Test status
Simulation time 14665676124 ps
CPU time 6.14 seconds
Started Mar 21 01:19:40 PM PDT 24
Finished Mar 21 01:19:48 PM PDT 24
Peak memory 211588 kb
Host smart-ba2dc9f1-0071-434a-9b79-6ac7409aa0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848279796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3848279796
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.1913232805
Short name T489
Test name
Test status
Simulation time 3261456582 ps
CPU time 7.16 seconds
Started Mar 21 01:19:48 PM PDT 24
Finished Mar 21 01:19:57 PM PDT 24
Peak memory 203484 kb
Host smart-baeb73c4-b6b9-4a85-a60b-b44cb2b46a1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913232805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.1913232805
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4201482327
Short name T284
Test name
Test status
Simulation time 40190151 ps
CPU time 0.62 seconds
Started Mar 21 01:17:41 PM PDT 24
Finished Mar 21 01:17:42 PM PDT 24
Peak memory 203044 kb
Host smart-0fda193f-b8a8-4d68-b611-3492c3ecfc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201482327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4201482327
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3761340730
Short name T567
Test name
Test status
Simulation time 82612345 ps
CPU time 1.6 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:41 PM PDT 24
Peak memory 211464 kb
Host smart-1835ae49-0eb9-490f-883d-3287cbd92a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761340730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3761340730
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1610204255
Short name T252
Test name
Test status
Simulation time 1191956035 ps
CPU time 4.34 seconds
Started Mar 21 01:17:29 PM PDT 24
Finished Mar 21 01:17:34 PM PDT 24
Peak memory 244588 kb
Host smart-bfb4c2d3-ecb6-4801-bd00-5eff2ea94aec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610204255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1610204255
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1051651588
Short name T14
Test name
Test status
Simulation time 5524344641 ps
CPU time 44.91 seconds
Started Mar 21 01:17:36 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 534192 kb
Host smart-348a0028-a027-42b1-887b-cc91b894cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051651588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1051651588
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2030128515
Short name T1010
Test name
Test status
Simulation time 1258854021 ps
CPU time 38.93 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:18:17 PM PDT 24
Peak memory 481768 kb
Host smart-e79e3ffd-6d7e-46f0-8594-6d18c706ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030128515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2030128515
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2276730340
Short name T619
Test name
Test status
Simulation time 319617472 ps
CPU time 1.13 seconds
Started Mar 21 01:17:30 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 202812 kb
Host smart-bb09a869-173d-46d5-b709-5141cd121294
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276730340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2276730340
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1836967378
Short name T330
Test name
Test status
Simulation time 222593894 ps
CPU time 4.89 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:17:43 PM PDT 24
Peak memory 233956 kb
Host smart-7acca231-5aab-46a8-9ad8-a8bb38d08ed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836967378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1836967378
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1460082165
Short name T874
Test name
Test status
Simulation time 14111960963 ps
CPU time 121.46 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:19:41 PM PDT 24
Peak memory 1159760 kb
Host smart-90c9a316-11f1-47d6-afa7-b46396e574ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460082165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1460082165
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_override.1891370076
Short name T173
Test name
Test status
Simulation time 46695711 ps
CPU time 0.61 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:17:39 PM PDT 24
Peak memory 202436 kb
Host smart-7a7f7ca1-95c6-4f7f-b015-5623e1a714e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891370076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1891370076
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2590519573
Short name T980
Test name
Test status
Simulation time 205530891 ps
CPU time 2.86 seconds
Started Mar 21 01:17:34 PM PDT 24
Finished Mar 21 01:17:37 PM PDT 24
Peak memory 211604 kb
Host smart-d88f0ba3-e322-4115-b295-5265ac4f5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590519573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2590519573
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1737823923
Short name T153
Test name
Test status
Simulation time 5801109625 ps
CPU time 46.83 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:18:25 PM PDT 24
Peak memory 321404 kb
Host smart-7b461be2-57ea-474a-86df-3cde7009fb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737823923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1737823923
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1172246475
Short name T104
Test name
Test status
Simulation time 135823707 ps
CPU time 0.83 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:29 PM PDT 24
Peak memory 220508 kb
Host smart-dfb81a34-73b8-4498-87dd-adfe54b53300
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172246475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1172246475
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3943458548
Short name T596
Test name
Test status
Simulation time 1297984186 ps
CPU time 3.29 seconds
Started Mar 21 01:17:28 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 203336 kb
Host smart-7bd61176-3c87-4886-8d2d-7cc65f805859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943458548 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3943458548
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1581858483
Short name T293
Test name
Test status
Simulation time 10079376917 ps
CPU time 74.83 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 619516 kb
Host smart-109c9aca-85a6-4cb6-8598-d19653423947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581858483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1581858483
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3703330557
Short name T444
Test name
Test status
Simulation time 10278139555 ps
CPU time 15.52 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:17:51 PM PDT 24
Peak memory 337220 kb
Host smart-a8bc49af-0859-4739-bc1d-844071055843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703330557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3703330557
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1466920846
Short name T299
Test name
Test status
Simulation time 684742909 ps
CPU time 3.71 seconds
Started Mar 21 01:17:34 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 203452 kb
Host smart-31158a02-01ec-4410-9de9-57c6191e7c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466920846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1466920846
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3184630467
Short name T879
Test name
Test status
Simulation time 17261919523 ps
CPU time 5.65 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:17:41 PM PDT 24
Peak memory 219304 kb
Host smart-56d6463b-cd9a-4fe1-b978-1075fcafc8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184630467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3184630467
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3565486989
Short name T806
Test name
Test status
Simulation time 5423494347 ps
CPU time 3.84 seconds
Started Mar 21 01:17:33 PM PDT 24
Finished Mar 21 01:17:37 PM PDT 24
Peak memory 203304 kb
Host smart-d3344ae6-dcd6-4aff-a099-db626658d1bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565486989 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3565486989
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2620108756
Short name T873
Test name
Test status
Simulation time 13021602378 ps
CPU time 14.61 seconds
Started Mar 21 01:17:48 PM PDT 24
Finished Mar 21 01:18:03 PM PDT 24
Peak memory 203376 kb
Host smart-dc5d1c0d-9d9b-439d-b322-0e152afedf68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620108756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2620108756
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3459995290
Short name T948
Test name
Test status
Simulation time 1064670224 ps
CPU time 4.88 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:45 PM PDT 24
Peak memory 203284 kb
Host smart-6ac90a14-0907-48a0-a49a-77b77bc765de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459995290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3459995290
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1407043368
Short name T510
Test name
Test status
Simulation time 30924184492 ps
CPU time 551.68 seconds
Started Mar 21 01:17:31 PM PDT 24
Finished Mar 21 01:26:43 PM PDT 24
Peak memory 1722212 kb
Host smart-94cd5f07-6ebb-4da4-87e4-5dcf35df1f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407043368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1407043368
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3985037762
Short name T553
Test name
Test status
Simulation time 2748474043 ps
CPU time 6.37 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:17:45 PM PDT 24
Peak memory 210020 kb
Host smart-b0dc73d4-f83d-4c34-a0ec-6b33badc4b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985037762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3985037762
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1755955039
Short name T576
Test name
Test status
Simulation time 46091961 ps
CPU time 0.64 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 203080 kb
Host smart-26a43ecb-562e-44ee-ab51-83384286a1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755955039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1755955039
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1875513421
Short name T30
Test name
Test status
Simulation time 128883274 ps
CPU time 1.43 seconds
Started Mar 21 01:19:40 PM PDT 24
Finished Mar 21 01:19:43 PM PDT 24
Peak memory 214356 kb
Host smart-d73d132e-491f-4dcc-8465-4cb7de840d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875513421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1875513421
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1497152157
Short name T177
Test name
Test status
Simulation time 221527443 ps
CPU time 11.72 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 247268 kb
Host smart-8db8e327-cb64-4369-952e-73272686b6c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497152157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1497152157
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.870013330
Short name T430
Test name
Test status
Simulation time 3926999300 ps
CPU time 52.24 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 406244 kb
Host smart-88072296-6d57-4729-8295-5e763c7d8804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870013330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.870013330
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.570469786
Short name T342
Test name
Test status
Simulation time 2633209790 ps
CPU time 30.91 seconds
Started Mar 21 01:19:42 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 439588 kb
Host smart-236eabe7-945f-41bb-880a-5ba051d97679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570469786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.570469786
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2272767377
Short name T559
Test name
Test status
Simulation time 196360268 ps
CPU time 1.01 seconds
Started Mar 21 01:19:40 PM PDT 24
Finished Mar 21 01:19:42 PM PDT 24
Peak memory 203048 kb
Host smart-d8be3a1e-8774-43c5-a898-f8ec17f2cb64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272767377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2272767377
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.602006967
Short name T800
Test name
Test status
Simulation time 686705252 ps
CPU time 5.04 seconds
Started Mar 21 01:19:47 PM PDT 24
Finished Mar 21 01:19:53 PM PDT 24
Peak memory 230888 kb
Host smart-9d55df15-65a8-4527-b289-5db2ad4baa8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602006967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
602006967
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2922339867
Short name T147
Test name
Test status
Simulation time 35023353396 ps
CPU time 71.84 seconds
Started Mar 21 01:19:54 PM PDT 24
Finished Mar 21 01:21:06 PM PDT 24
Peak memory 953324 kb
Host smart-66779b7a-5bff-4d2b-8205-60f5e735dbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922339867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2922339867
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_override.3650830
Short name T920
Test name
Test status
Simulation time 22008557 ps
CPU time 0.61 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 202400 kb
Host smart-604ff8fa-4547-4d63-98ef-02e99bed25ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3650830
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1879030729
Short name T991
Test name
Test status
Simulation time 5134464051 ps
CPU time 300.7 seconds
Started Mar 21 01:19:54 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 379972 kb
Host smart-ce74f930-5ca0-48fe-87e8-1cf94c9e1020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879030729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1879030729
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.479653785
Short name T860
Test name
Test status
Simulation time 1614554454 ps
CPU time 80.21 seconds
Started Mar 21 01:19:46 PM PDT 24
Finished Mar 21 01:21:07 PM PDT 24
Peak memory 374600 kb
Host smart-0c73bde2-bb02-4cbf-bb3b-e24af4ce9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479653785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.479653785
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2413850766
Short name T258
Test name
Test status
Simulation time 2455092297 ps
CPU time 2.75 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:19:55 PM PDT 24
Peak memory 203392 kb
Host smart-f4f2204c-0ec9-4a34-8414-cde548d74262
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413850766 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2413850766
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.242911287
Short name T675
Test name
Test status
Simulation time 10105212490 ps
CPU time 28.03 seconds
Started Mar 21 01:19:56 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 366480 kb
Host smart-444cf01b-537c-4923-a16d-c0a2d47a8a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242911287 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.242911287
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1050965540
Short name T634
Test name
Test status
Simulation time 10281621984 ps
CPU time 36.34 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:30 PM PDT 24
Peak memory 468792 kb
Host smart-76314328-52f6-4193-9f26-e3f19bc8b65c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050965540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1050965540
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2317768651
Short name T594
Test name
Test status
Simulation time 804007504 ps
CPU time 2.55 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 203240 kb
Host smart-a779ee6a-7652-46e4-b344-9706e7141470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317768651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2317768651
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2440125695
Short name T236
Test name
Test status
Simulation time 3548031825 ps
CPU time 5.07 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:19:56 PM PDT 24
Peak memory 211600 kb
Host smart-49b507a8-218a-412e-a2a4-213d4f0bcda4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440125695 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2440125695
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1406089304
Short name T393
Test name
Test status
Simulation time 5585869286 ps
CPU time 57.43 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:20:36 PM PDT 24
Peak memory 203364 kb
Host smart-ae01974f-7c32-4ccb-b6ff-17c31c5ca719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406089304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1406089304
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.648893419
Short name T499
Test name
Test status
Simulation time 2962352608 ps
CPU time 9.97 seconds
Started Mar 21 01:19:54 PM PDT 24
Finished Mar 21 01:20:04 PM PDT 24
Peak memory 208640 kb
Host smart-6701859e-ba60-4c82-b714-5156e1314c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648893419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.648893419
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1039778392
Short name T341
Test name
Test status
Simulation time 12798314317 ps
CPU time 5.15 seconds
Started Mar 21 01:19:38 PM PDT 24
Finished Mar 21 01:19:44 PM PDT 24
Peak memory 203352 kb
Host smart-3fbf7a41-6427-4479-984e-dddcc98c6743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039778392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1039778392
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2181087254
Short name T497
Test name
Test status
Simulation time 26624322570 ps
CPU time 132.47 seconds
Started Mar 21 01:19:54 PM PDT 24
Finished Mar 21 01:22:06 PM PDT 24
Peak memory 1321448 kb
Host smart-9df3cc91-ee06-4f15-94fd-7516bdfae685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181087254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2181087254
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2019730643
Short name T296
Test name
Test status
Simulation time 5280552857 ps
CPU time 6.52 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:59 PM PDT 24
Peak memory 211640 kb
Host smart-5973e44c-e697-40af-ac7a-b695b890d443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019730643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2019730643
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.3748554814
Short name T24
Test name
Test status
Simulation time 751644966 ps
CPU time 4.83 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 203384 kb
Host smart-4205a424-c93e-4970-b86f-71dc5efa58c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748554814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.3748554814
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2105309080
Short name T91
Test name
Test status
Simulation time 115167132 ps
CPU time 0.62 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 203012 kb
Host smart-264a9cf6-002b-4a93-b2f5-80b9bd43cfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105309080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2105309080
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1971728080
Short name T818
Test name
Test status
Simulation time 503899911 ps
CPU time 1.32 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 211492 kb
Host smart-ec2c8724-83ba-44a7-bac3-41b1a4f4e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971728080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1971728080
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1450554656
Short name T465
Test name
Test status
Simulation time 545705425 ps
CPU time 28 seconds
Started Mar 21 01:19:56 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 317204 kb
Host smart-124b0405-0204-430b-bcec-90bc7d784313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450554656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1450554656
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1492790378
Short name T414
Test name
Test status
Simulation time 8258031369 ps
CPU time 58.99 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 628868 kb
Host smart-13c4933e-54f5-43ac-a781-1150aed75fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492790378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1492790378
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1898258129
Short name T909
Test name
Test status
Simulation time 2505225952 ps
CPU time 35.09 seconds
Started Mar 21 01:19:55 PM PDT 24
Finished Mar 21 01:20:30 PM PDT 24
Peak memory 502500 kb
Host smart-0c8d6bc5-1244-46f7-9a6c-6a517107c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898258129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1898258129
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.112288456
Short name T989
Test name
Test status
Simulation time 733169132 ps
CPU time 0.89 seconds
Started Mar 21 01:19:49 PM PDT 24
Finished Mar 21 01:19:51 PM PDT 24
Peak memory 203064 kb
Host smart-43426a2e-f934-4020-8934-366f98eafc24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112288456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.112288456
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.4063466751
Short name T311
Test name
Test status
Simulation time 553418309 ps
CPU time 4.47 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:19:56 PM PDT 24
Peak memory 229624 kb
Host smart-80a93cb0-9fd7-49d2-a7c0-3202e82f0d22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063466751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.4063466751
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1330863719
Short name T139
Test name
Test status
Simulation time 4003575140 ps
CPU time 93.03 seconds
Started Mar 21 01:19:56 PM PDT 24
Finished Mar 21 01:21:30 PM PDT 24
Peak memory 1125756 kb
Host smart-2d558cf1-2128-4c3c-ab67-e07c682adeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330863719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1330863719
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_override.2358492732
Short name T171
Test name
Test status
Simulation time 36676158 ps
CPU time 0.64 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:19:51 PM PDT 24
Peak memory 202392 kb
Host smart-1553bbd1-9a96-42d5-92be-a5c64f8a7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358492732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2358492732
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3121548627
Short name T331
Test name
Test status
Simulation time 1151242122 ps
CPU time 33.86 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 290392 kb
Host smart-105f5425-0353-439a-81fe-3af123db4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121548627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3121548627
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2411454555
Short name T870
Test name
Test status
Simulation time 648671554 ps
CPU time 2.87 seconds
Started Mar 21 01:19:56 PM PDT 24
Finished Mar 21 01:20:00 PM PDT 24
Peak memory 203404 kb
Host smart-d7d132ce-bf93-4425-a9f9-50f5ebe7ea93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411454555 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2411454555
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1243958009
Short name T313
Test name
Test status
Simulation time 10035639513 ps
CPU time 55.37 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 474660 kb
Host smart-303676ef-170c-46e4-9ea8-1675fb4fd57f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243958009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1243958009
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2297736748
Short name T608
Test name
Test status
Simulation time 10043444104 ps
CPU time 96.33 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:21:27 PM PDT 24
Peak memory 657664 kb
Host smart-24d486b7-0702-4acd-b046-27469757f801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297736748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2297736748
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.152184481
Short name T23
Test name
Test status
Simulation time 361503491 ps
CPU time 2.13 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 203264 kb
Host smart-a48cec0a-b636-49b9-b513-051c6d8cbb54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152184481 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.152184481
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1863687413
Short name T838
Test name
Test status
Simulation time 691602404 ps
CPU time 3.94 seconds
Started Mar 21 01:19:49 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 207188 kb
Host smart-fc08b011-c4fe-4585-a633-f5a5dab82ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863687413 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1863687413
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2236449269
Short name T41
Test name
Test status
Simulation time 7253219157 ps
CPU time 17.26 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:20:10 PM PDT 24
Peak memory 216016 kb
Host smart-7a395483-25f5-4989-8f9e-e10fdd549a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236449269 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2236449269
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3658226441
Short name T1006
Test name
Test status
Simulation time 1183547221 ps
CPU time 47.46 seconds
Started Mar 21 01:19:54 PM PDT 24
Finished Mar 21 01:20:42 PM PDT 24
Peak memory 203296 kb
Host smart-0823e8f2-174d-4445-a787-767f91f15cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658226441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3658226441
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.887118635
Short name T281
Test name
Test status
Simulation time 596261938 ps
CPU time 12.69 seconds
Started Mar 21 01:19:51 PM PDT 24
Finished Mar 21 01:20:04 PM PDT 24
Peak memory 203356 kb
Host smart-88e21682-bf82-455b-bd8e-9bdd9a68cfd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887118635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.887118635
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.4278130260
Short name T237
Test name
Test status
Simulation time 8007363693 ps
CPU time 8.07 seconds
Started Mar 21 01:19:49 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 203448 kb
Host smart-255b595b-9dae-4945-a21a-438179d952ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278130260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.4278130260
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.728183141
Short name T1087
Test name
Test status
Simulation time 27968117150 ps
CPU time 227.46 seconds
Started Mar 21 01:19:49 PM PDT 24
Finished Mar 21 01:23:38 PM PDT 24
Peak memory 1824388 kb
Host smart-c0b3e362-e970-4fa1-8c34-255df5909b90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728183141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.728183141
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2437087538
Short name T853
Test name
Test status
Simulation time 1460177798 ps
CPU time 7.69 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:20:01 PM PDT 24
Peak memory 219072 kb
Host smart-ee348cd9-126a-4507-9bac-e51723406a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437087538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2437087538
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.381633500
Short name T319
Test name
Test status
Simulation time 40302214 ps
CPU time 0.63 seconds
Started Mar 21 01:20:04 PM PDT 24
Finished Mar 21 01:20:04 PM PDT 24
Peak memory 203012 kb
Host smart-ce87372d-f787-4964-87dd-744de1193e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381633500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.381633500
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2901715084
Short name T583
Test name
Test status
Simulation time 46890167 ps
CPU time 1.35 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:12 PM PDT 24
Peak memory 211560 kb
Host smart-c0f53b61-cc51-4797-b7e8-906d5ba87655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901715084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2901715084
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.426403058
Short name T240
Test name
Test status
Simulation time 562848682 ps
CPU time 5.09 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 261428 kb
Host smart-02a72ee1-f4e0-494d-bbd1-aa2d2a7f2069
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426403058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.426403058
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3925350270
Short name T422
Test name
Test status
Simulation time 5973271032 ps
CPU time 86.62 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:21:20 PM PDT 24
Peak memory 469724 kb
Host smart-f03823ab-1252-4ac9-b5f1-caf435d312e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925350270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3925350270
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.4155890045
Short name T248
Test name
Test status
Simulation time 1996022095 ps
CPU time 69.79 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:21:03 PM PDT 24
Peak memory 678520 kb
Host smart-cc1aac10-7b3e-4000-9178-e2ca9cd7ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155890045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.4155890045
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2862161815
Short name T876
Test name
Test status
Simulation time 223818201 ps
CPU time 0.95 seconds
Started Mar 21 01:19:49 PM PDT 24
Finished Mar 21 01:19:51 PM PDT 24
Peak memory 203044 kb
Host smart-9e62dc54-f653-4779-88e2-360d41a67724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862161815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2862161815
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.4014533497
Short name T744
Test name
Test status
Simulation time 146678140 ps
CPU time 7.72 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:19:58 PM PDT 24
Peak memory 227860 kb
Host smart-852de2b2-7b06-43b3-8dca-a29d6e366c69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014533497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.4014533497
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1579552664
Short name T701
Test name
Test status
Simulation time 5520227576 ps
CPU time 183.04 seconds
Started Mar 21 01:19:50 PM PDT 24
Finished Mar 21 01:22:53 PM PDT 24
Peak memory 846140 kb
Host smart-3911688b-eb75-4e4f-8e4d-9eb2fb959c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579552664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1579552664
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_override.584459360
Short name T169
Test name
Test status
Simulation time 30997988 ps
CPU time 0.7 seconds
Started Mar 21 01:19:52 PM PDT 24
Finished Mar 21 01:19:54 PM PDT 24
Peak memory 202448 kb
Host smart-e1413517-f0b8-443a-9ca5-dfe98e6c949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584459360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.584459360
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.431923393
Short name T868
Test name
Test status
Simulation time 7023355576 ps
CPU time 1306.57 seconds
Started Mar 21 01:19:53 PM PDT 24
Finished Mar 21 01:41:40 PM PDT 24
Peak memory 613940 kb
Host smart-8b20be15-79bd-4a3a-a193-dd4f288969cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431923393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.431923393
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1579358805
Short name T432
Test name
Test status
Simulation time 1429308593 ps
CPU time 47.05 seconds
Started Mar 21 01:19:56 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 300360 kb
Host smart-d26405a9-896d-4b8c-bc23-797394c9c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579358805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1579358805
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.764902888
Short name T203
Test name
Test status
Simulation time 50236424753 ps
CPU time 1739.22 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:49:21 PM PDT 24
Peak memory 2434196 kb
Host smart-89a0eb04-dd6f-42bd-8e60-ff83080cf129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764902888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.764902888
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.381863096
Short name T753
Test name
Test status
Simulation time 1279368651 ps
CPU time 2.26 seconds
Started Mar 21 01:20:03 PM PDT 24
Finished Mar 21 01:20:05 PM PDT 24
Peak memory 203316 kb
Host smart-b3cbfdb9-31a7-4d07-9697-db572f739467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381863096 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.381863096
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1189404875
Short name T1030
Test name
Test status
Simulation time 10232929335 ps
CPU time 15.31 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:26 PM PDT 24
Peak memory 316864 kb
Host smart-ad3fe2a4-791c-4627-be04-02b3f607c839
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189404875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1189404875
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2533441179
Short name T1049
Test name
Test status
Simulation time 10055004076 ps
CPU time 98.88 seconds
Started Mar 21 01:20:00 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 715544 kb
Host smart-5754926c-57c6-43aa-862d-c47994bd764a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533441179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2533441179
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.1775075977
Short name T1045
Test name
Test status
Simulation time 572003178 ps
CPU time 1.97 seconds
Started Mar 21 01:20:03 PM PDT 24
Finished Mar 21 01:20:05 PM PDT 24
Peak memory 203372 kb
Host smart-133b0202-70c7-4eb1-99c6-ffff8dcdc983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775075977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.1775075977
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1124025741
Short name T607
Test name
Test status
Simulation time 923697689 ps
CPU time 4.31 seconds
Started Mar 21 01:19:58 PM PDT 24
Finished Mar 21 01:20:03 PM PDT 24
Peak memory 205476 kb
Host smart-7297e584-a483-41d4-a7a4-caf45ed547d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124025741 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1124025741
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1813796793
Short name T997
Test name
Test status
Simulation time 587669284 ps
CPU time 7.14 seconds
Started Mar 21 01:20:12 PM PDT 24
Finished Mar 21 01:20:19 PM PDT 24
Peak memory 203424 kb
Host smart-d708f060-e017-4053-a2f1-ec874c5029c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813796793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1813796793
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1976468569
Short name T261
Test name
Test status
Simulation time 2175540776 ps
CPU time 13.4 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:24 PM PDT 24
Peak memory 213188 kb
Host smart-8b1fd6a8-4651-4934-9cff-68a7b206a7ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976468569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1976468569
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1209219082
Short name T572
Test name
Test status
Simulation time 5881644011 ps
CPU time 7.64 seconds
Started Mar 21 01:20:00 PM PDT 24
Finished Mar 21 01:20:07 PM PDT 24
Peak memory 216508 kb
Host smart-3b17a0e6-6084-477d-a194-6e6ee736a0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209219082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1209219082
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3149828126
Short name T294
Test name
Test status
Simulation time 23768950 ps
CPU time 0.65 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:10 PM PDT 24
Peak memory 203024 kb
Host smart-064cf912-2a3a-47d1-900a-cf36bbb1b484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149828126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3149828126
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1947207691
Short name T968
Test name
Test status
Simulation time 3330813729 ps
CPU time 10.85 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:20:26 PM PDT 24
Peak memory 310688 kb
Host smart-b3db015c-4ef2-40ff-bed0-b26a7459646b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947207691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1947207691
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1526971849
Short name T627
Test name
Test status
Simulation time 8425531138 ps
CPU time 68.04 seconds
Started Mar 21 01:20:07 PM PDT 24
Finished Mar 21 01:21:15 PM PDT 24
Peak memory 687360 kb
Host smart-60fcb457-6820-4cf3-90b1-acacb66bf68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526971849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1526971849
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3847921598
Short name T529
Test name
Test status
Simulation time 5045567676 ps
CPU time 93.51 seconds
Started Mar 21 01:20:05 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 517816 kb
Host smart-020fe4e4-1c62-460c-b6df-72a8c4a70361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847921598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3847921598
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1852898571
Short name T192
Test name
Test status
Simulation time 100881282 ps
CPU time 0.96 seconds
Started Mar 21 01:20:00 PM PDT 24
Finished Mar 21 01:20:02 PM PDT 24
Peak memory 203044 kb
Host smart-2e70353c-cf0c-49a8-bc6f-e02b29e90d88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852898571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1852898571
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2816506569
Short name T474
Test name
Test status
Simulation time 186831168 ps
CPU time 9.46 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:20:24 PM PDT 24
Peak memory 203236 kb
Host smart-d23b5064-c63f-4893-80f3-636c7f74e260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816506569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2816506569
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_override.117913508
Short name T433
Test name
Test status
Simulation time 180644273 ps
CPU time 0.66 seconds
Started Mar 21 01:20:02 PM PDT 24
Finished Mar 21 01:20:03 PM PDT 24
Peak memory 202436 kb
Host smart-05e30e4b-5ec2-4090-a6a4-c40ed4d9085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117913508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.117913508
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3286170326
Short name T589
Test name
Test status
Simulation time 1317039322 ps
CPU time 28.49 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 236740 kb
Host smart-d7348b34-5ec0-4265-a558-9266bb81bcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286170326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3286170326
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3270228081
Short name T957
Test name
Test status
Simulation time 2365923666 ps
CPU time 37.12 seconds
Started Mar 21 01:20:07 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 268108 kb
Host smart-eb62a274-38e6-4e35-82e0-8887593c1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270228081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3270228081
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.840774999
Short name T332
Test name
Test status
Simulation time 640088619 ps
CPU time 3.42 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 211644 kb
Host smart-677b902a-d679-46ec-9944-11f01ec867b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840774999 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.840774999
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2762877037
Short name T758
Test name
Test status
Simulation time 10102739242 ps
CPU time 74.66 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:21:29 PM PDT 24
Peak memory 589528 kb
Host smart-24fe0b80-eab8-435c-b945-d2e1ec73b98a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762877037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2762877037
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.489766595
Short name T1009
Test name
Test status
Simulation time 10072767705 ps
CPU time 37.39 seconds
Started Mar 21 01:20:11 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 434188 kb
Host smart-69b956ca-6dfd-4d54-aaa5-8bfa99afd2a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489766595 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.489766595
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3362138349
Short name T548
Test name
Test status
Simulation time 322529478 ps
CPU time 2.41 seconds
Started Mar 21 01:20:07 PM PDT 24
Finished Mar 21 01:20:10 PM PDT 24
Peak memory 203436 kb
Host smart-f6f40c85-baf0-4d5e-88af-5c19c138e63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362138349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3362138349
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2660262042
Short name T429
Test name
Test status
Simulation time 1720943585 ps
CPU time 3.23 seconds
Started Mar 21 01:20:01 PM PDT 24
Finished Mar 21 01:20:04 PM PDT 24
Peak memory 203664 kb
Host smart-39c847f5-b5c7-47e2-acb0-e8baad0af0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660262042 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2660262042
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.611517847
Short name T975
Test name
Test status
Simulation time 777323778 ps
CPU time 31.65 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 203288 kb
Host smart-8602a3d0-9207-44a3-b645-76e063c864eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611517847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.611517847
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1878153320
Short name T395
Test name
Test status
Simulation time 1240258139 ps
CPU time 24.33 seconds
Started Mar 21 01:20:04 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 203164 kb
Host smart-1807fcdb-d41b-4dd2-b095-081f6726c643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878153320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1878153320
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.528641247
Short name T277
Test name
Test status
Simulation time 26614183976 ps
CPU time 29.12 seconds
Started Mar 21 01:20:04 PM PDT 24
Finished Mar 21 01:20:33 PM PDT 24
Peak memory 414332 kb
Host smart-318fe4bc-3602-401e-ad48-52b1a812dc61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528641247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.528641247
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3468392578
Short name T337
Test name
Test status
Simulation time 1349513143 ps
CPU time 6.7 seconds
Started Mar 21 01:20:08 PM PDT 24
Finished Mar 21 01:20:15 PM PDT 24
Peak memory 211444 kb
Host smart-3de79002-d1ba-48ff-9212-b89199c84754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468392578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3468392578
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.864989841
Short name T358
Test name
Test status
Simulation time 19056275 ps
CPU time 0.59 seconds
Started Mar 21 01:20:17 PM PDT 24
Finished Mar 21 01:20:19 PM PDT 24
Peak memory 203116 kb
Host smart-e8ce6e5d-b503-4d74-9280-aff4a1db3fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864989841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.864989841
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3235818588
Short name T796
Test name
Test status
Simulation time 70875761 ps
CPU time 1.25 seconds
Started Mar 21 01:20:11 PM PDT 24
Finished Mar 21 01:20:12 PM PDT 24
Peak memory 211460 kb
Host smart-e86c217a-9865-4e59-b37d-9d40dc327b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235818588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3235818588
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.504908139
Short name T797
Test name
Test status
Simulation time 442054405 ps
CPU time 7.23 seconds
Started Mar 21 01:20:15 PM PDT 24
Finished Mar 21 01:20:23 PM PDT 24
Peak memory 275720 kb
Host smart-fe8bafb5-33fa-4a57-96ec-a28f20a79dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504908139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.504908139
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3114720983
Short name T500
Test name
Test status
Simulation time 1968663444 ps
CPU time 51.06 seconds
Started Mar 21 01:20:16 PM PDT 24
Finished Mar 21 01:21:07 PM PDT 24
Peak memory 493192 kb
Host smart-bcc30842-7570-49d9-8abe-c4f7dbc85224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114720983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3114720983
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1124581520
Short name T842
Test name
Test status
Simulation time 1519554849 ps
CPU time 37.98 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:48 PM PDT 24
Peak memory 496760 kb
Host smart-0f7f9da6-4910-48a5-9742-29ceaf629669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124581520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1124581520
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3245705869
Short name T898
Test name
Test status
Simulation time 872803124 ps
CPU time 1.04 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:11 PM PDT 24
Peak memory 203040 kb
Host smart-2f7b9a8a-bf9b-493c-bb60-1dc268ff25f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245705869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3245705869
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2895764276
Short name T899
Test name
Test status
Simulation time 168022183 ps
CPU time 3.88 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:20:18 PM PDT 24
Peak memory 224156 kb
Host smart-71e67798-6108-4d4e-97c4-78fdff65492e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895764276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2895764276
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2281292316
Short name T343
Test name
Test status
Simulation time 6110984846 ps
CPU time 72.58 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 799572 kb
Host smart-6750df88-c8b8-4779-ae2a-5fe85f1cbd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281292316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2281292316
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_override.380421612
Short name T501
Test name
Test status
Simulation time 61114512 ps
CPU time 0.64 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:11 PM PDT 24
Peak memory 202536 kb
Host smart-4b9908ba-7580-46b9-8495-af771e7d4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380421612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.380421612
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2704672118
Short name T960
Test name
Test status
Simulation time 480747056 ps
CPU time 2.36 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:12 PM PDT 24
Peak memory 211524 kb
Host smart-b049794c-fc80-4b6e-92cc-f6a72c8b698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704672118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2704672118
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.4041374045
Short name T289
Test name
Test status
Simulation time 906110366 ps
CPU time 33.11 seconds
Started Mar 21 01:20:12 PM PDT 24
Finished Mar 21 01:20:45 PM PDT 24
Peak memory 277828 kb
Host smart-a7310ee6-1ef9-41c3-9bcf-ad60550673e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041374045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.4041374045
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3716523405
Short name T21
Test name
Test status
Simulation time 4014370754 ps
CPU time 4.48 seconds
Started Mar 21 01:20:16 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 211552 kb
Host smart-dddeb0a2-762d-4c95-97b1-fedd97f1e72a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716523405 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3716523405
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2556671674
Short name T1001
Test name
Test status
Simulation time 10349308069 ps
CPU time 13.61 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:24 PM PDT 24
Peak memory 286352 kb
Host smart-0c5cf31e-489f-4d99-8f43-5f67449b53ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556671674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2556671674
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2227541384
Short name T703
Test name
Test status
Simulation time 10059452168 ps
CPU time 81.56 seconds
Started Mar 21 01:20:12 PM PDT 24
Finished Mar 21 01:21:34 PM PDT 24
Peak memory 702556 kb
Host smart-99a99253-8045-4d36-b61a-4984c2a6d345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227541384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2227541384
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3097436276
Short name T862
Test name
Test status
Simulation time 347859597 ps
CPU time 2.01 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:11 PM PDT 24
Peak memory 203340 kb
Host smart-183fa014-c5a6-479b-9951-9023b682c205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097436276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3097436276
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.231137373
Short name T549
Test name
Test status
Simulation time 24368554488 ps
CPU time 7.85 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:20:17 PM PDT 24
Peak memory 218872 kb
Host smart-5e636be1-c20a-49fc-835a-d52f8289d4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231137373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.231137373
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1791077239
Short name T162
Test name
Test status
Simulation time 1775203086 ps
CPU time 13.63 seconds
Started Mar 21 01:20:10 PM PDT 24
Finished Mar 21 01:20:24 PM PDT 24
Peak memory 203304 kb
Host smart-213dc0bb-1581-4572-af37-5b2e93a9e4c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791077239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1791077239
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1073179432
Short name T503
Test name
Test status
Simulation time 744413976 ps
CPU time 15.48 seconds
Started Mar 21 01:20:15 PM PDT 24
Finished Mar 21 01:20:31 PM PDT 24
Peak memory 203412 kb
Host smart-dbdaced6-bc22-4051-b0f0-fe34368de783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073179432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1073179432
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1081311941
Short name T871
Test name
Test status
Simulation time 1439838021 ps
CPU time 7.25 seconds
Started Mar 21 01:20:15 PM PDT 24
Finished Mar 21 01:20:22 PM PDT 24
Peak memory 203316 kb
Host smart-aafe72f6-578e-456d-976f-f7a693d8d78d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081311941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1081311941
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2643833692
Short name T100
Test name
Test status
Simulation time 18947584 ps
CPU time 0.62 seconds
Started Mar 21 01:20:25 PM PDT 24
Finished Mar 21 01:20:26 PM PDT 24
Peak memory 203096 kb
Host smart-667ecda0-ba11-4f44-a2d9-3578f9930c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643833692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2643833692
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3029410198
Short name T47
Test name
Test status
Simulation time 51217999 ps
CPU time 1.38 seconds
Started Mar 21 01:20:30 PM PDT 24
Finished Mar 21 01:20:31 PM PDT 24
Peak memory 219612 kb
Host smart-2e26c8b5-3eae-4dd5-8cf5-5975699fb837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029410198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3029410198
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3340533280
Short name T273
Test name
Test status
Simulation time 647949208 ps
CPU time 6.51 seconds
Started Mar 21 01:20:15 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 277344 kb
Host smart-05af7a1b-9e69-4dd8-bf3f-2751a3f9d355
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340533280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3340533280
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2225219289
Short name T339
Test name
Test status
Simulation time 1998677417 ps
CPU time 139.87 seconds
Started Mar 21 01:20:19 PM PDT 24
Finished Mar 21 01:22:40 PM PDT 24
Peak memory 680088 kb
Host smart-80223d3c-ee94-4a8a-8b91-6a7621cf02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225219289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2225219289
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.666224675
Short name T908
Test name
Test status
Simulation time 8785501817 ps
CPU time 79.96 seconds
Started Mar 21 01:20:09 PM PDT 24
Finished Mar 21 01:21:30 PM PDT 24
Peak memory 729612 kb
Host smart-b6d0d94d-94c3-4f92-a73f-7ca120c1e0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666224675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.666224675
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4208539597
Short name T941
Test name
Test status
Simulation time 128240411 ps
CPU time 0.78 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:20:22 PM PDT 24
Peak memory 202484 kb
Host smart-7b24f7ce-790d-49c3-953b-71aebe01f025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208539597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4208539597
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2951885644
Short name T728
Test name
Test status
Simulation time 606067794 ps
CPU time 5.62 seconds
Started Mar 21 01:20:11 PM PDT 24
Finished Mar 21 01:20:17 PM PDT 24
Peak memory 240300 kb
Host smart-410610a1-4fbc-4848-bdec-ce67cf09b4b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951885644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2951885644
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.802245093
Short name T786
Test name
Test status
Simulation time 3191200828 ps
CPU time 212.11 seconds
Started Mar 21 01:20:14 PM PDT 24
Finished Mar 21 01:23:46 PM PDT 24
Peak memory 905100 kb
Host smart-bb3160b7-d4f4-42ed-8a8f-79b0cc2389d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802245093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.802245093
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_override.2573837799
Short name T321
Test name
Test status
Simulation time 16030698 ps
CPU time 0.67 seconds
Started Mar 21 01:20:12 PM PDT 24
Finished Mar 21 01:20:13 PM PDT 24
Peak memory 202444 kb
Host smart-d3c5a793-c256-4984-abfe-d39a37a707ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573837799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2573837799
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.134618995
Short name T696
Test name
Test status
Simulation time 54297163567 ps
CPU time 1240.59 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:41:01 PM PDT 24
Peak memory 1062528 kb
Host smart-b835a52a-09f0-49fd-9425-6c8764716e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134618995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.134618995
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1525735536
Short name T320
Test name
Test status
Simulation time 3478824085 ps
CPU time 3.08 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:26 PM PDT 24
Peak memory 203456 kb
Host smart-3a275de6-1570-4aab-9e5f-79a59ce9c001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525735536 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1525735536
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1640267971
Short name T993
Test name
Test status
Simulation time 10091977677 ps
CPU time 32.07 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:20:58 PM PDT 24
Peak memory 360700 kb
Host smart-b7487d84-d84a-4493-a513-6c323e8a4dbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640267971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1640267971
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.59865895
Short name T963
Test name
Test status
Simulation time 10054584005 ps
CPU time 96.52 seconds
Started Mar 21 01:20:25 PM PDT 24
Finished Mar 21 01:22:01 PM PDT 24
Peak memory 695112 kb
Host smart-2360a9cb-5b24-42b2-b665-1019c1b7fc95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59865895 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_fifo_reset_tx.59865895
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.747294007
Short name T199
Test name
Test status
Simulation time 339634947 ps
CPU time 2.15 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 203384 kb
Host smart-f7661666-9412-47a6-b88e-f2f27d309cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747294007 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.747294007
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3119188608
Short name T1031
Test name
Test status
Simulation time 4317956765 ps
CPU time 5.91 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:29 PM PDT 24
Peak memory 219572 kb
Host smart-93c04912-aaae-4043-a0a5-c398287d01e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119188608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3119188608
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3858956409
Short name T471
Test name
Test status
Simulation time 4639718011 ps
CPU time 5.87 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 203324 kb
Host smart-7532f9b1-47dc-4cab-95d7-759005bff11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858956409 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3858956409
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3221959852
Short name T609
Test name
Test status
Simulation time 1084398359 ps
CPU time 13.31 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 203292 kb
Host smart-bf15f3da-9d85-4fae-b09e-aa3aa3929576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221959852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3221959852
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3135215317
Short name T929
Test name
Test status
Simulation time 4046481156 ps
CPU time 19.72 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 230316 kb
Host smart-998392d8-04da-45f2-9858-0890fcd62482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135215317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3135215317
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2244209425
Short name T257
Test name
Test status
Simulation time 14807781740 ps
CPU time 35.95 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:21:00 PM PDT 24
Peak memory 586064 kb
Host smart-027a9925-334a-49cf-9516-b6b5b0051eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244209425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2244209425
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.81542798
Short name T770
Test name
Test status
Simulation time 1239355252 ps
CPU time 6.8 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:30 PM PDT 24
Peak memory 216136 kb
Host smart-2d0e35e5-d523-45ab-ae61-1f1711cdc6ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81542798 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_timeout.81542798
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1631213802
Short name T792
Test name
Test status
Simulation time 68813848 ps
CPU time 0.65 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:22 PM PDT 24
Peak memory 203028 kb
Host smart-dd444e40-eff6-41ff-b8ad-395a9469bb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631213802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1631213802
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1271833641
Short name T915
Test name
Test status
Simulation time 157367072 ps
CPU time 1.36 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 211568 kb
Host smart-c3327383-45eb-4f90-9be2-fb1b5208d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271833641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1271833641
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.4229959701
Short name T1055
Test name
Test status
Simulation time 1410019738 ps
CPU time 17.93 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:42 PM PDT 24
Peak memory 271592 kb
Host smart-09cd8ce1-4415-43ef-9332-1f2920c8ba59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229959701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.4229959701
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.341356853
Short name T309
Test name
Test status
Simulation time 1593013670 ps
CPU time 46.1 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:21:10 PM PDT 24
Peak memory 562344 kb
Host smart-2b888738-1800-4218-bc70-4462e6ab42d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341356853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.341356853
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3449423144
Short name T590
Test name
Test status
Simulation time 8195992092 ps
CPU time 64.59 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:21:27 PM PDT 24
Peak memory 653040 kb
Host smart-0d287264-d026-4403-9eff-7e924dc75b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449423144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3449423144
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.839348786
Short name T660
Test name
Test status
Simulation time 396665830 ps
CPU time 0.95 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 202672 kb
Host smart-80b1c05c-22e4-4d28-b55f-4090711956b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839348786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.839348786
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2549023299
Short name T664
Test name
Test status
Simulation time 122780634 ps
CPU time 2.86 seconds
Started Mar 21 01:20:27 PM PDT 24
Finished Mar 21 01:20:30 PM PDT 24
Peak memory 203320 kb
Host smart-a43e6397-d208-46aa-b433-a99fa9ac599d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549023299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2549023299
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_override.4027541109
Short name T16
Test name
Test status
Simulation time 20596910 ps
CPU time 0.68 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 202488 kb
Host smart-5730e33f-961e-41b1-b6a5-f812742d1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027541109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.4027541109
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3528712063
Short name T355
Test name
Test status
Simulation time 2396857414 ps
CPU time 29.05 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:52 PM PDT 24
Peak memory 222672 kb
Host smart-41d8ce0f-e214-400d-9208-807b7a894c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528712063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3528712063
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.4162849984
Short name T211
Test name
Test status
Simulation time 1152805174 ps
CPU time 86.89 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:21:49 PM PDT 24
Peak memory 284428 kb
Host smart-8b63d215-d806-4906-90c3-4930c88e0617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162849984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4162849984
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2567886446
Short name T743
Test name
Test status
Simulation time 10295342670 ps
CPU time 13.52 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:37 PM PDT 24
Peak memory 283156 kb
Host smart-71116234-c411-488f-a507-70c22edf7e29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567886446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2567886446
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3237147917
Short name T458
Test name
Test status
Simulation time 10244540158 ps
CPU time 17.93 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:40 PM PDT 24
Peak memory 324792 kb
Host smart-6842cbb1-eec1-40c9-af81-7d1e61c5e4c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237147917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3237147917
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.146879369
Short name T554
Test name
Test status
Simulation time 336479594 ps
CPU time 2.56 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:26 PM PDT 24
Peak memory 203412 kb
Host smart-8eaeca4d-a4ce-4909-b703-568511e1a41d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146879369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.146879369
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3827124225
Short name T238
Test name
Test status
Simulation time 2882870617 ps
CPU time 3.74 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:20:30 PM PDT 24
Peak memory 203484 kb
Host smart-d28ae086-705b-4947-a716-33d6771780f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827124225 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3827124225
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.464085159
Short name T938
Test name
Test status
Simulation time 1155967458 ps
CPU time 29.99 seconds
Started Mar 21 01:20:30 PM PDT 24
Finished Mar 21 01:21:00 PM PDT 24
Peak memory 203316 kb
Host smart-88086587-33d6-4cb7-98d6-eb28073d36b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464085159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.464085159
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.667904138
Short name T209
Test name
Test status
Simulation time 6112018204 ps
CPU time 23.03 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:20:47 PM PDT 24
Peak memory 226976 kb
Host smart-6aa54258-caa3-41b0-82dc-8ddbe3c0d306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667904138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.667904138
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2020064483
Short name T265
Test name
Test status
Simulation time 23304072852 ps
CPU time 1561.63 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:46:22 PM PDT 24
Peak memory 5711512 kb
Host smart-c6e9c652-e575-4f71-8505-e50dadf04b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020064483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2020064483
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2723159519
Short name T740
Test name
Test status
Simulation time 1240445221 ps
CPU time 6.55 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 219568 kb
Host smart-7d499550-70a8-405f-bbfb-0f41de5240fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723159519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2723159519
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.2723083568
Short name T766
Test name
Test status
Simulation time 1811100043 ps
CPU time 5.11 seconds
Started Mar 21 01:20:19 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 205320 kb
Host smart-5803e9cd-6870-4ce4-9a88-079f90aca80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723083568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.2723083568
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2744298039
Short name T917
Test name
Test status
Simulation time 42373743 ps
CPU time 0.64 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:32 PM PDT 24
Peak memory 203016 kb
Host smart-314eea17-7879-4a1e-8d5f-396e355c5774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744298039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2744298039
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3389955835
Short name T705
Test name
Test status
Simulation time 73991085 ps
CPU time 1.13 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 211624 kb
Host smart-a09ce6d4-bd32-45f6-873b-ec6e4f534a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389955835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3389955835
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1797944917
Short name T410
Test name
Test status
Simulation time 995687625 ps
CPU time 14.44 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:20:39 PM PDT 24
Peak memory 255956 kb
Host smart-9e245da3-3ffe-4df9-94ae-7d6bebf96c6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797944917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1797944917
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.803510494
Short name T298
Test name
Test status
Simulation time 1099227953 ps
CPU time 62.36 seconds
Started Mar 21 01:20:20 PM PDT 24
Finished Mar 21 01:21:23 PM PDT 24
Peak memory 356144 kb
Host smart-bb439169-dc9f-4076-82a7-52a56c47cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803510494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.803510494
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2175231374
Short name T511
Test name
Test status
Simulation time 2007286120 ps
CPU time 48.27 seconds
Started Mar 21 01:20:21 PM PDT 24
Finished Mar 21 01:21:11 PM PDT 24
Peak memory 570948 kb
Host smart-68ef922d-2673-4e3d-8ce6-1ce04f11c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175231374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2175231374
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1562957012
Short name T883
Test name
Test status
Simulation time 176010388 ps
CPU time 1.05 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 203212 kb
Host smart-b334a9b8-84e3-45a3-bf9f-af39c206b1be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562957012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1562957012
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.136178391
Short name T187
Test name
Test status
Simulation time 433550088 ps
CPU time 5.57 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:29 PM PDT 24
Peak memory 203264 kb
Host smart-4cee9b7a-100e-44f6-8764-4d318d91f87a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136178391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
136178391
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1535588472
Short name T697
Test name
Test status
Simulation time 12828473137 ps
CPU time 204.4 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:23:49 PM PDT 24
Peak memory 912572 kb
Host smart-dc2b28dd-646e-4bb0-8f1c-b154c3e90fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535588472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1535588472
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_override.2350559806
Short name T1011
Test name
Test status
Simulation time 97739095 ps
CPU time 0.65 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:25 PM PDT 24
Peak memory 202484 kb
Host smart-2944199b-cc91-4f5b-acb4-5876f75f0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350559806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2350559806
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.118350424
Short name T446
Test name
Test status
Simulation time 13075823914 ps
CPU time 586.3 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 659672 kb
Host smart-83929c01-3ce1-4ecc-ab76-46fd3f2eb54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118350424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.118350424
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1040115502
Short name T586
Test name
Test status
Simulation time 1571995828 ps
CPU time 45.49 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:21:09 PM PDT 24
Peak memory 303060 kb
Host smart-4b06158a-7618-4a09-8963-047c6d9f6532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040115502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1040115502
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2644447519
Short name T242
Test name
Test status
Simulation time 703575283 ps
CPU time 3.59 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:35 PM PDT 24
Peak memory 203312 kb
Host smart-a846509a-0946-4f68-8d4c-9f6e9d15760b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644447519 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2644447519
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3239138250
Short name T495
Test name
Test status
Simulation time 10206944164 ps
CPU time 12.55 seconds
Started Mar 21 01:20:33 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 280432 kb
Host smart-27477728-0722-43dc-893c-4fa993e61724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239138250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3239138250
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3335556100
Short name T347
Test name
Test status
Simulation time 10389191780 ps
CPU time 13.54 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 308892 kb
Host smart-77878fc6-7220-4126-8fcc-e2857b6727e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335556100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3335556100
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3716203721
Short name T893
Test name
Test status
Simulation time 1103674204 ps
CPU time 2.05 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:35 PM PDT 24
Peak memory 203348 kb
Host smart-3c25696c-663d-4335-b30c-e387e6fb4544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716203721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3716203721
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2681682264
Short name T982
Test name
Test status
Simulation time 560576601 ps
CPU time 3.29 seconds
Started Mar 21 01:20:24 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 203288 kb
Host smart-680e953c-d846-4a0b-bf8e-4518fbf941eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681682264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2681682264
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2608193851
Short name T901
Test name
Test status
Simulation time 7342860441 ps
CPU time 5.28 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 203304 kb
Host smart-f3354451-6c29-42cc-96e6-bb6a48fdb63c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608193851 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2608193851
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2815972898
Short name T1035
Test name
Test status
Simulation time 516810242 ps
CPU time 7.48 seconds
Started Mar 21 01:20:22 PM PDT 24
Finished Mar 21 01:20:31 PM PDT 24
Peak memory 203420 kb
Host smart-ed77d8d3-afcd-4174-8270-5a6a477f3290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815972898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2815972898
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.50866525
Short name T1026
Test name
Test status
Simulation time 1185412625 ps
CPU time 18.12 seconds
Started Mar 21 01:20:27 PM PDT 24
Finished Mar 21 01:20:45 PM PDT 24
Peak memory 220928 kb
Host smart-94effb86-277f-4f0c-a836-52eaf1a9b101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50866525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_rd.50866525
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.588874427
Short name T418
Test name
Test status
Simulation time 30611928483 ps
CPU time 4.6 seconds
Started Mar 21 01:20:23 PM PDT 24
Finished Mar 21 01:20:28 PM PDT 24
Peak memory 203384 kb
Host smart-983edc6a-c179-47df-92f3-0777f2ebb8f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588874427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.588874427
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.614924181
Short name T614
Test name
Test status
Simulation time 17737677428 ps
CPU time 530.55 seconds
Started Mar 21 01:20:26 PM PDT 24
Finished Mar 21 01:29:17 PM PDT 24
Peak memory 1512540 kb
Host smart-4eb594d9-9f74-4b0a-b26f-7f1e6c5c32bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614924181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.614924181
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3307842856
Short name T158
Test name
Test status
Simulation time 3261630665 ps
CPU time 7.82 seconds
Started Mar 21 01:20:35 PM PDT 24
Finished Mar 21 01:20:43 PM PDT 24
Peak memory 219724 kb
Host smart-acf6226d-2e1d-4583-abab-0dccec9dd590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307842856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3307842856
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2074549729
Short name T564
Test name
Test status
Simulation time 50180420 ps
CPU time 0.67 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:20:41 PM PDT 24
Peak memory 203024 kb
Host smart-ebc15b29-79f7-4c97-adbd-c7cad42cab33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074549729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2074549729
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2231723637
Short name T325
Test name
Test status
Simulation time 30124153 ps
CPU time 1.17 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:34 PM PDT 24
Peak memory 211444 kb
Host smart-4dc97d7a-270a-458f-8518-39f05dd89141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231723637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2231723637
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3633649092
Short name T468
Test name
Test status
Simulation time 541592145 ps
CPU time 13.73 seconds
Started Mar 21 01:20:34 PM PDT 24
Finished Mar 21 01:20:47 PM PDT 24
Peak memory 256940 kb
Host smart-2cb94c9f-2a19-4956-ac53-a8f5289f2ddb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633649092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3633649092
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1031761503
Short name T220
Test name
Test status
Simulation time 4713606190 ps
CPU time 151.42 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:23:08 PM PDT 24
Peak memory 651956 kb
Host smart-3c69ab05-8361-4d86-9aeb-3b28f6e0ccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031761503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1031761503
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2562287247
Short name T109
Test name
Test status
Simulation time 4441888297 ps
CPU time 74.32 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:21:47 PM PDT 24
Peak memory 768472 kb
Host smart-6de26096-6bd8-4c11-a1cf-541d92cdc5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562287247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2562287247
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.474676461
Short name T329
Test name
Test status
Simulation time 83218434 ps
CPU time 0.92 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:32 PM PDT 24
Peak memory 203008 kb
Host smart-53de051b-e36e-4dee-b8a4-d71bac6f7dba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474676461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.474676461
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4051412551
Short name T807
Test name
Test status
Simulation time 332605476 ps
CPU time 4.31 seconds
Started Mar 21 01:20:33 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 233460 kb
Host smart-24462a73-58f9-4098-837b-e68ac3d3282d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051412551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4051412551
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.4108278464
Short name T530
Test name
Test status
Simulation time 6238992868 ps
CPU time 90.85 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:22:02 PM PDT 24
Peak memory 956812 kb
Host smart-7cb1c5f2-3de7-47ad-b8c1-64fe4828122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108278464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.4108278464
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_override.1245098082
Short name T172
Test name
Test status
Simulation time 22384329 ps
CPU time 0.66 seconds
Started Mar 21 01:20:30 PM PDT 24
Finished Mar 21 01:20:31 PM PDT 24
Peak memory 202440 kb
Host smart-a1f1a931-5835-4582-97b0-445bc60b6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245098082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1245098082
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.106347382
Short name T1044
Test name
Test status
Simulation time 4054673204 ps
CPU time 32.38 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:21:08 PM PDT 24
Peak memory 276880 kb
Host smart-c5f2b7af-57b4-4f85-a9b5-562fe15f6ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106347382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.106347382
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.195697078
Short name T326
Test name
Test status
Simulation time 3934101493 ps
CPU time 3.69 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:36 PM PDT 24
Peak memory 203464 kb
Host smart-a52097a7-44ce-4494-af0a-14c3521e0304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195697078 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.195697078
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3390867668
Short name T1019
Test name
Test status
Simulation time 10185766569 ps
CPU time 13.14 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 280880 kb
Host smart-ab5a6212-5776-4dba-90d2-5701e2a466df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390867668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3390867668
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.4237437313
Short name T425
Test name
Test status
Simulation time 10167660708 ps
CPU time 4.83 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:36 PM PDT 24
Peak memory 237040 kb
Host smart-14ea6d5f-a803-4e9c-94f9-cdf12fbc10e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237437313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.4237437313
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1812472390
Short name T653
Test name
Test status
Simulation time 1358618915 ps
CPU time 1.83 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 203396 kb
Host smart-58e0102f-6120-4d12-a38b-4da796997384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812472390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1812472390
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2499715657
Short name T600
Test name
Test status
Simulation time 1476740425 ps
CPU time 6.58 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 203300 kb
Host smart-fe5d8f01-1d32-437f-bd12-dc8f717efb08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499715657 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2499715657
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3865258012
Short name T243
Test name
Test status
Simulation time 1555051660 ps
CPU time 5.93 seconds
Started Mar 21 01:20:33 PM PDT 24
Finished Mar 21 01:20:39 PM PDT 24
Peak memory 203304 kb
Host smart-dcefef40-561a-45e6-be03-e5013403830d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865258012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3865258012
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1777210179
Short name T480
Test name
Test status
Simulation time 6382115917 ps
CPU time 49.68 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 204180 kb
Host smart-8517ec02-8c3b-4dc3-b081-90f9b17fe80a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777210179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1777210179
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3821352075
Short name T525
Test name
Test status
Simulation time 27673567273 ps
CPU time 512.17 seconds
Started Mar 21 01:20:34 PM PDT 24
Finished Mar 21 01:29:07 PM PDT 24
Peak memory 1510764 kb
Host smart-18297044-4076-400f-be62-487e7f868d6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821352075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3821352075
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1791500147
Short name T845
Test name
Test status
Simulation time 1009829817 ps
CPU time 5.97 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:39 PM PDT 24
Peak memory 203288 kb
Host smart-588e545c-2c7c-4d69-9f98-8735e9485fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791500147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1791500147
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3201919317
Short name T301
Test name
Test status
Simulation time 16870076 ps
CPU time 0.61 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:20:41 PM PDT 24
Peak memory 203132 kb
Host smart-65c0dfd5-b379-4f29-a77f-448486415056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201919317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3201919317
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2822084080
Short name T46
Test name
Test status
Simulation time 37206735 ps
CPU time 1.13 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:32 PM PDT 24
Peak memory 211580 kb
Host smart-3c740544-458a-401a-b213-c9ae601521b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822084080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2822084080
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1524409011
Short name T371
Test name
Test status
Simulation time 480869691 ps
CPU time 8.98 seconds
Started Mar 21 01:20:34 PM PDT 24
Finished Mar 21 01:20:43 PM PDT 24
Peak memory 306636 kb
Host smart-c27373ab-5ec5-4b43-a9c1-86c118e9d889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524409011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1524409011
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2502102219
Short name T219
Test name
Test status
Simulation time 8277782284 ps
CPU time 72.19 seconds
Started Mar 21 01:20:37 PM PDT 24
Finished Mar 21 01:21:50 PM PDT 24
Peak memory 632892 kb
Host smart-e154e706-b1fb-4525-8640-19aee0cfd852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502102219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2502102219
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1634384486
Short name T485
Test name
Test status
Simulation time 12001464708 ps
CPU time 47.71 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:21:19 PM PDT 24
Peak memory 562292 kb
Host smart-839cc483-1d7e-45a9-ba15-bc2246bb5b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634384486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1634384486
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3997930044
Short name T1053
Test name
Test status
Simulation time 572312023 ps
CPU time 1.18 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:33 PM PDT 24
Peak memory 203224 kb
Host smart-fbc30bc2-6aca-4613-9944-cef2b18244fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997930044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3997930044
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1596382302
Short name T798
Test name
Test status
Simulation time 188616002 ps
CPU time 5.37 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:37 PM PDT 24
Peak memory 236764 kb
Host smart-e4375e60-5a16-4db8-ae88-3b903cabac8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596382302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1596382302
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3984391912
Short name T138
Test name
Test status
Simulation time 26500442479 ps
CPU time 72.01 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:21:48 PM PDT 24
Peak memory 877704 kb
Host smart-3c1c7358-78f1-449a-9612-d3d3b3349e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984391912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3984391912
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_override.3977495413
Short name T168
Test name
Test status
Simulation time 20710170 ps
CPU time 0.66 seconds
Started Mar 21 01:20:32 PM PDT 24
Finished Mar 21 01:20:33 PM PDT 24
Peak memory 202444 kb
Host smart-ad93182a-296d-4cfb-b6d1-15048d72678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977495413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3977495413
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.4258814947
Short name T570
Test name
Test status
Simulation time 7423291872 ps
CPU time 2179.27 seconds
Started Mar 21 01:20:35 PM PDT 24
Finished Mar 21 01:56:54 PM PDT 24
Peak memory 1292396 kb
Host smart-e5528c99-410d-4034-bc14-aeedc3e1ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258814947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4258814947
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.4161464195
Short name T690
Test name
Test status
Simulation time 6244072432 ps
CPU time 98.66 seconds
Started Mar 21 01:20:34 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 404536 kb
Host smart-5400cd14-637a-4d66-a1ff-7318096c2932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161464195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.4161464195
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3376648340
Short name T19
Test name
Test status
Simulation time 3995263765 ps
CPU time 4.1 seconds
Started Mar 21 01:20:31 PM PDT 24
Finished Mar 21 01:20:36 PM PDT 24
Peak memory 211884 kb
Host smart-9ad6962e-fcf8-4c0f-a25b-544ea217d3e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376648340 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3376648340
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4109971688
Short name T1073
Test name
Test status
Simulation time 10181399780 ps
CPU time 13.04 seconds
Started Mar 21 01:20:34 PM PDT 24
Finished Mar 21 01:20:47 PM PDT 24
Peak memory 292656 kb
Host smart-f2c4affb-3e8a-4c45-a1df-081f3fc5f104
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109971688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.4109971688
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1041071563
Short name T176
Test name
Test status
Simulation time 10555674358 ps
CPU time 10.14 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 300628 kb
Host smart-54afc1fa-d4f3-4b97-8a41-e6b1da7fe8df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041071563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1041071563
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.418077253
Short name T1041
Test name
Test status
Simulation time 744121485 ps
CPU time 2.15 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 203352 kb
Host smart-e6614393-857f-4272-96e9-5bf5de568d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418077253 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_hrst.418077253
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2174796072
Short name T1022
Test name
Test status
Simulation time 10518008161 ps
CPU time 3.78 seconds
Started Mar 21 01:20:36 PM PDT 24
Finished Mar 21 01:20:40 PM PDT 24
Peak memory 203436 kb
Host smart-974a3032-9e02-4c82-854a-5f39a0c91e8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174796072 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2174796072
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.793504691
Short name T445
Test name
Test status
Simulation time 4871678761 ps
CPU time 10.6 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:20:50 PM PDT 24
Peak memory 203328 kb
Host smart-3ba7c8f7-ae09-4530-9711-8848bb91c1fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793504691 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.793504691
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2314810584
Short name T426
Test name
Test status
Simulation time 650987115 ps
CPU time 25.9 seconds
Started Mar 21 01:20:35 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 203272 kb
Host smart-2703ae5c-d49f-4d94-9d01-a5366ecd739e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314810584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2314810584
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3662198193
Short name T442
Test name
Test status
Simulation time 2668601820 ps
CPU time 45.6 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 204604 kb
Host smart-a2cabd6a-3a9e-4af3-a830-356049057200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662198193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3662198193
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.153680722
Short name T762
Test name
Test status
Simulation time 9293263327 ps
CPU time 129.55 seconds
Started Mar 21 01:20:35 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 708324 kb
Host smart-f1eeaec2-55ae-440c-9aeb-a6c5e55a7b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153680722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.153680722
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1577403485
Short name T774
Test name
Test status
Simulation time 5807058683 ps
CPU time 7.16 seconds
Started Mar 21 01:20:33 PM PDT 24
Finished Mar 21 01:20:41 PM PDT 24
Peak memory 203404 kb
Host smart-c7550efe-8b37-4501-b6ec-1a80e2b11461
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577403485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1577403485
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3974867048
Short name T657
Test name
Test status
Simulation time 19617331 ps
CPU time 0.6 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 203052 kb
Host smart-98e9192d-77c1-47cb-958f-89b7667e1435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974867048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3974867048
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2239425038
Short name T542
Test name
Test status
Simulation time 75467397 ps
CPU time 1.3 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:17:39 PM PDT 24
Peak memory 211604 kb
Host smart-3651200c-34f8-419a-b999-a0c3dcb73c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239425038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2239425038
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3105921726
Short name T1021
Test name
Test status
Simulation time 1030288641 ps
CPU time 6.15 seconds
Started Mar 21 01:17:42 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 249456 kb
Host smart-ff4c141b-9433-44f9-9e65-85f3ee55e2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105921726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3105921726
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.100272151
Short name T364
Test name
Test status
Simulation time 25825395307 ps
CPU time 74.51 seconds
Started Mar 21 01:17:43 PM PDT 24
Finished Mar 21 01:18:58 PM PDT 24
Peak memory 654592 kb
Host smart-0ac360c2-ac17-4166-9863-92a8f5743448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100272151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.100272151
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1017598838
Short name T110
Test name
Test status
Simulation time 6539410471 ps
CPU time 55.09 seconds
Started Mar 21 01:17:47 PM PDT 24
Finished Mar 21 01:18:42 PM PDT 24
Peak memory 565144 kb
Host smart-b0c95a19-e83a-49f6-bd66-9386b7133865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017598838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1017598838
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1097949856
Short name T776
Test name
Test status
Simulation time 647459563 ps
CPU time 0.99 seconds
Started Mar 21 01:17:41 PM PDT 24
Finished Mar 21 01:17:42 PM PDT 24
Peak memory 203144 kb
Host smart-0c695a0c-65f8-429d-aebd-cef8479f3f3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097949856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1097949856
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3051922384
Short name T919
Test name
Test status
Simulation time 154781592 ps
CPU time 9.64 seconds
Started Mar 21 01:17:45 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 231420 kb
Host smart-5c714111-b0c6-4179-9033-856fe1c5b5ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051922384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3051922384
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2109652683
Short name T452
Test name
Test status
Simulation time 3030906783 ps
CPU time 87.44 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:19:07 PM PDT 24
Peak memory 930860 kb
Host smart-cf0b96fc-af2d-42d4-9720-23425f0f62f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109652683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2109652683
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_override.3478632352
Short name T401
Test name
Test status
Simulation time 81781999 ps
CPU time 0.63 seconds
Started Mar 21 01:17:35 PM PDT 24
Finished Mar 21 01:17:36 PM PDT 24
Peak memory 202536 kb
Host smart-9b21e0f0-cc06-4631-9f7d-59444bae9747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478632352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3478632352
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1760743296
Short name T39
Test name
Test status
Simulation time 2684496048 ps
CPU time 28.37 seconds
Started Mar 21 01:17:42 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 203408 kb
Host smart-4e24f4e3-6713-423a-94c3-b35601def142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760743296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1760743296
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3256446459
Short name T415
Test name
Test status
Simulation time 5334492550 ps
CPU time 79.1 seconds
Started Mar 21 01:17:27 PM PDT 24
Finished Mar 21 01:18:46 PM PDT 24
Peak memory 244220 kb
Host smart-146c3358-1cbf-48ea-816e-fb2019233099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256446459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3256446459
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2889176508
Short name T103
Test name
Test status
Simulation time 39014172 ps
CPU time 0.84 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 220220 kb
Host smart-3132f3b8-c83f-4e04-a214-7735cb5b51a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889176508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2889176508
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3441355031
Short name T413
Test name
Test status
Simulation time 11122479198 ps
CPU time 4.07 seconds
Started Mar 21 01:17:42 PM PDT 24
Finished Mar 21 01:17:46 PM PDT 24
Peak memory 203376 kb
Host smart-187580fb-8764-44c3-b193-9fef8602a44c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441355031 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3441355031
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2724568783
Short name T3
Test name
Test status
Simulation time 10326473941 ps
CPU time 15.75 seconds
Started Mar 21 01:17:36 PM PDT 24
Finished Mar 21 01:17:52 PM PDT 24
Peak memory 301428 kb
Host smart-73705643-f951-42ca-9501-b19ea5069d35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724568783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2724568783
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1384588784
Short name T864
Test name
Test status
Simulation time 10055948953 ps
CPU time 92.28 seconds
Started Mar 21 01:17:36 PM PDT 24
Finished Mar 21 01:19:09 PM PDT 24
Peak memory 735752 kb
Host smart-27a38cbd-042a-4bd1-9713-0a52839e412a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384588784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1384588784
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2291975450
Short name T569
Test name
Test status
Simulation time 1181146626 ps
CPU time 2.57 seconds
Started Mar 21 01:17:45 PM PDT 24
Finished Mar 21 01:17:47 PM PDT 24
Peak memory 203412 kb
Host smart-554a39b0-b7ac-403e-bbc3-d39e16b8639e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291975450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2291975450
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2000535684
Short name T232
Test name
Test status
Simulation time 16689354821 ps
CPU time 7.49 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 223452 kb
Host smart-fd0e7767-b6a9-4b13-b3e3-5915e4470201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000535684 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2000535684
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3726346179
Short name T900
Test name
Test status
Simulation time 513506415 ps
CPU time 18.23 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:17:56 PM PDT 24
Peak memory 203276 kb
Host smart-b11a2e6e-be51-4e70-9615-173df9dbda27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726346179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3726346179
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.870256243
Short name T59
Test name
Test status
Simulation time 4116975234 ps
CPU time 14.69 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 212824 kb
Host smart-f5bc47f5-8566-440e-b4a0-25fac0daa852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870256243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.870256243
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2793785223
Short name T923
Test name
Test status
Simulation time 6996731384 ps
CPU time 85.73 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 953788 kb
Host smart-45f50226-5917-43a4-9614-a3d42df56a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793785223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2793785223
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1437445052
Short name T803
Test name
Test status
Simulation time 5407405322 ps
CPU time 6.88 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:17:44 PM PDT 24
Peak memory 219640 kb
Host smart-a5379f72-f424-4176-84a0-bbb5291e0642
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437445052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1437445052
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1726848957
Short name T599
Test name
Test status
Simulation time 32030799 ps
CPU time 0.63 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:45 PM PDT 24
Peak memory 202868 kb
Host smart-c85502a0-1a55-4a0d-9507-e76f8b83b403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726848957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1726848957
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2733454863
Short name T591
Test name
Test status
Simulation time 81031313 ps
CPU time 1.29 seconds
Started Mar 21 01:20:39 PM PDT 24
Finished Mar 21 01:20:41 PM PDT 24
Peak memory 211412 kb
Host smart-65f59f97-31fb-42cf-b499-07ddea745488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733454863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2733454863
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3220191914
Short name T402
Test name
Test status
Simulation time 942608796 ps
CPU time 13.33 seconds
Started Mar 21 01:20:43 PM PDT 24
Finished Mar 21 01:20:56 PM PDT 24
Peak memory 257516 kb
Host smart-624e53dc-9e88-4153-90f9-cbcddc347448
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220191914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3220191914
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1168397520
Short name T388
Test name
Test status
Simulation time 1756922111 ps
CPU time 121.13 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 599540 kb
Host smart-bdf5acbf-c73e-4e58-8e06-d37f444b1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168397520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1168397520
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2361656760
Short name T760
Test name
Test status
Simulation time 4879516601 ps
CPU time 43.34 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 531740 kb
Host smart-6ba6027a-5710-49e0-8103-198fc0534636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361656760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2361656760
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.4014693965
Short name T194
Test name
Test status
Simulation time 97332311 ps
CPU time 0.9 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:20:42 PM PDT 24
Peak memory 203016 kb
Host smart-30d213b1-6361-4984-b692-66b1cdb01dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014693965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.4014693965
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.4263379111
Short name T593
Test name
Test status
Simulation time 261583894 ps
CPU time 7.31 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 203372 kb
Host smart-8695e038-edab-4b82-9c27-77aec910aefc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263379111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.4263379111
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.4147205599
Short name T146
Test name
Test status
Simulation time 2901683393 ps
CPU time 69.41 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:21:51 PM PDT 24
Peak memory 916608 kb
Host smart-6de7323f-5f6b-48e2-adcb-66d2a0abf420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147205599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4147205599
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_override.3072559075
Short name T779
Test name
Test status
Simulation time 79895544 ps
CPU time 0.63 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:20:40 PM PDT 24
Peak memory 202436 kb
Host smart-a0d60639-2bbc-4811-b2e5-b4f4e06ffe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072559075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3072559075
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2412922086
Short name T283
Test name
Test status
Simulation time 405197662 ps
CPU time 9.13 seconds
Started Mar 21 01:20:43 PM PDT 24
Finished Mar 21 01:20:52 PM PDT 24
Peak memory 248656 kb
Host smart-bc17a119-f63e-4480-9eed-2fe0603d889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412922086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2412922086
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1902916281
Short name T1071
Test name
Test status
Simulation time 5022060845 ps
CPU time 58.21 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 250720 kb
Host smart-ad5d1076-1532-436e-bedb-161a73614b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902916281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1902916281
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.4029061313
Short name T197
Test name
Test status
Simulation time 21278621589 ps
CPU time 1055.83 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:38:21 PM PDT 24
Peak memory 3375764 kb
Host smart-123255a3-cc0c-44d1-88af-5f5b48aa079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029061313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.4029061313
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1954034131
Short name T640
Test name
Test status
Simulation time 765323793 ps
CPU time 3.41 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 203336 kb
Host smart-e45be608-5747-479e-98fb-f2cac3466027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954034131 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1954034131
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2911591730
Short name T977
Test name
Test status
Simulation time 10175756646 ps
CPU time 32.4 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:21:12 PM PDT 24
Peak memory 401212 kb
Host smart-6fee756d-b6e4-4397-aaa9-769e47b66537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911591730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2911591730
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1645680325
Short name T691
Test name
Test status
Simulation time 10129371226 ps
CPU time 93.67 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 676024 kb
Host smart-f6dadcf8-9be2-4390-b07c-b0e0b38a7aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645680325 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1645680325
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.742778010
Short name T207
Test name
Test status
Simulation time 1644973449 ps
CPU time 1.8 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 203304 kb
Host smart-2209f894-11b1-4412-8b57-05530bf60091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742778010 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.742778010
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3661840760
Short name T650
Test name
Test status
Simulation time 1252959486 ps
CPU time 5.34 seconds
Started Mar 21 01:20:44 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 203284 kb
Host smart-aad516bd-104c-4558-9765-352e5d5d1634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661840760 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3661840760
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3320534000
Short name T255
Test name
Test status
Simulation time 5212417168 ps
CPU time 3.29 seconds
Started Mar 21 01:20:44 PM PDT 24
Finished Mar 21 01:20:48 PM PDT 24
Peak memory 203264 kb
Host smart-528ca822-520b-4600-b474-3542c24b7ff2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320534000 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3320534000
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.528800442
Short name T721
Test name
Test status
Simulation time 5765143448 ps
CPU time 15.15 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:57 PM PDT 24
Peak memory 203276 kb
Host smart-f183b949-b24c-49da-8e07-3b8cab3b296e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528800442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.528800442
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.4278124950
Short name T486
Test name
Test status
Simulation time 978363299 ps
CPU time 3.97 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 203336 kb
Host smart-5b153314-f87a-4870-a508-64db2c1337bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278124950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.4278124950
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1570102165
Short name T9
Test name
Test status
Simulation time 5341224352 ps
CPU time 5.89 seconds
Started Mar 21 01:20:44 PM PDT 24
Finished Mar 21 01:20:50 PM PDT 24
Peak memory 219236 kb
Host smart-e8295f1b-670e-4140-a940-074c6aeb43ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570102165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1570102165
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1755093453
Short name T522
Test name
Test status
Simulation time 14171335 ps
CPU time 0.58 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:51 PM PDT 24
Peak memory 203060 kb
Host smart-4732842d-f2ee-4818-914d-ad6a33ec98e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755093453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1755093453
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3587185966
Short name T996
Test name
Test status
Simulation time 216754494 ps
CPU time 1.55 seconds
Started Mar 21 01:20:43 PM PDT 24
Finished Mar 21 01:20:44 PM PDT 24
Peak memory 211504 kb
Host smart-af41e211-0e50-4b0b-bc2d-d7ed1e21f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587185966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3587185966
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.398027200
Short name T659
Test name
Test status
Simulation time 251649391 ps
CPU time 13.22 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:55 PM PDT 24
Peak memory 255320 kb
Host smart-73be0df6-2b5b-4084-b01d-2aed7cddf039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398027200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.398027200
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.12278428
Short name T216
Test name
Test status
Simulation time 8957703623 ps
CPU time 170.03 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:23:32 PM PDT 24
Peak memory 732344 kb
Host smart-087bcb27-a509-440f-b22e-1aee6df71063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12278428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.12278428
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.632330397
Short name T246
Test name
Test status
Simulation time 8717562370 ps
CPU time 57.72 seconds
Started Mar 21 01:20:41 PM PDT 24
Finished Mar 21 01:21:38 PM PDT 24
Peak memory 642636 kb
Host smart-154f62f3-7202-4464-b152-e86e8c6a6de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632330397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.632330397
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4056330866
Short name T684
Test name
Test status
Simulation time 427282116 ps
CPU time 2.51 seconds
Started Mar 21 01:20:40 PM PDT 24
Finished Mar 21 01:20:42 PM PDT 24
Peak memory 203356 kb
Host smart-d7956e01-ce6e-4a51-b01c-4495d29511bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056330866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4056330866
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2103907781
Short name T925
Test name
Test status
Simulation time 31863992264 ps
CPU time 316.51 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:25:59 PM PDT 24
Peak memory 1206396 kb
Host smart-5d529292-1a0e-4cdf-8dab-7235c123412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103907781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2103907781
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_override.4107531667
Short name T316
Test name
Test status
Simulation time 18366575 ps
CPU time 0.62 seconds
Started Mar 21 01:20:46 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 202448 kb
Host smart-7209dc8b-9b68-478a-b76a-a58259b0b1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107531667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.4107531667
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.310089517
Short name T2
Test name
Test status
Simulation time 4965055935 ps
CPU time 42.79 seconds
Started Mar 21 01:20:38 PM PDT 24
Finished Mar 21 01:21:21 PM PDT 24
Peak memory 283804 kb
Host smart-ed7d8161-90c5-4fb1-949d-dc6374bf4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310089517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.310089517
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3273146677
Short name T183
Test name
Test status
Simulation time 57279589435 ps
CPU time 3336.36 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 02:16:22 PM PDT 24
Peak memory 1380636 kb
Host smart-191d9e95-00a7-4de7-a1fa-b63ddedafef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273146677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3273146677
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.27823773
Short name T999
Test name
Test status
Simulation time 1466843559 ps
CPU time 4.78 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:50 PM PDT 24
Peak memory 203336 kb
Host smart-d63e3313-1054-487a-ad97-c47fac7bb622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823773 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_bad_addr.27823773
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3470664825
Short name T278
Test name
Test status
Simulation time 10081627849 ps
CPU time 31.74 seconds
Started Mar 21 01:20:46 PM PDT 24
Finished Mar 21 01:21:18 PM PDT 24
Peak memory 414560 kb
Host smart-72d4d07c-f568-4d9d-adcc-0c919b8a6d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470664825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3470664825
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1913783085
Short name T621
Test name
Test status
Simulation time 10036674702 ps
CPU time 117.67 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:22:39 PM PDT 24
Peak memory 742392 kb
Host smart-8e1cac19-6ba1-4293-83bc-bf0f0c543b58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913783085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1913783085
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3930329362
Short name T42
Test name
Test status
Simulation time 1025692556 ps
CPU time 2.19 seconds
Started Mar 21 01:20:43 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 203284 kb
Host smart-9b66e15b-4998-47ce-8ff6-a915bda06da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930329362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3930329362
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.774795344
Short name T592
Test name
Test status
Simulation time 1211188332 ps
CPU time 5.6 seconds
Started Mar 21 01:20:42 PM PDT 24
Finished Mar 21 01:20:48 PM PDT 24
Peak memory 219856 kb
Host smart-ff0ddffe-cd4c-44a2-ae4b-09848a56ef12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774795344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.774795344
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1812891088
Short name T545
Test name
Test status
Simulation time 792659922 ps
CPU time 10.54 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:56 PM PDT 24
Peak memory 203332 kb
Host smart-ac813425-5037-4358-975d-dbc4cb6911ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812891088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1812891088
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3155979659
Short name T1047
Test name
Test status
Simulation time 1859995822 ps
CPU time 7.35 seconds
Started Mar 21 01:20:46 PM PDT 24
Finished Mar 21 01:20:54 PM PDT 24
Peak memory 203296 kb
Host smart-a83caa0f-99ce-4344-b869-e9fcef71c58e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155979659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3155979659
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.4097735833
Short name T419
Test name
Test status
Simulation time 1215281578 ps
CPU time 5.55 seconds
Started Mar 21 01:20:47 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 203276 kb
Host smart-8cf4cc87-84ce-401b-96ff-c9b4843e31f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097735833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.4097735833
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.797232311
Short name T896
Test name
Test status
Simulation time 1706231679 ps
CPU time 4.61 seconds
Started Mar 21 01:20:47 PM PDT 24
Finished Mar 21 01:20:51 PM PDT 24
Peak memory 203872 kb
Host smart-076f0509-0bef-47a3-a98c-ab6bf0748e75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797232311 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_unexp_stop.797232311
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2878362538
Short name T1040
Test name
Test status
Simulation time 96720865 ps
CPU time 0.58 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 203140 kb
Host smart-f869e171-1b66-493d-8a9e-dd9b0acf91cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878362538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2878362538
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1324759962
Short name T51
Test name
Test status
Simulation time 143163234 ps
CPU time 1.71 seconds
Started Mar 21 01:20:53 PM PDT 24
Finished Mar 21 01:20:55 PM PDT 24
Peak memory 203416 kb
Host smart-41bf425b-2c23-4c73-93b9-ee16b30fd807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324759962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1324759962
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.659450075
Short name T981
Test name
Test status
Simulation time 506308343 ps
CPU time 20.79 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:21:12 PM PDT 24
Peak memory 251072 kb
Host smart-ec6ca0e8-af7e-48ad-80f2-e41740ff27ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659450075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.659450075
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3677127977
Short name T578
Test name
Test status
Simulation time 12129939870 ps
CPU time 30.62 seconds
Started Mar 21 01:20:50 PM PDT 24
Finished Mar 21 01:21:21 PM PDT 24
Peak memory 296536 kb
Host smart-9f462fed-bdae-43d8-b81f-7f222ae87914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677127977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3677127977
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3764024228
Short name T1002
Test name
Test status
Simulation time 1609534900 ps
CPU time 25.88 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:21:11 PM PDT 24
Peak memory 414348 kb
Host smart-92fe6dd1-bfc7-454a-98fe-80434b9fbc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764024228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3764024228
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2838383030
Short name T492
Test name
Test status
Simulation time 206689261 ps
CPU time 1.03 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:46 PM PDT 24
Peak memory 202800 kb
Host smart-e669996f-3621-482d-ac09-be813c204cc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838383030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2838383030
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3667450835
Short name T1062
Test name
Test status
Simulation time 250314994 ps
CPU time 3.89 seconds
Started Mar 21 01:20:50 PM PDT 24
Finished Mar 21 01:20:54 PM PDT 24
Peak memory 224912 kb
Host smart-7b26789d-1994-4129-b9db-32224f7f4e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667450835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3667450835
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3603253257
Short name T143
Test name
Test status
Simulation time 3769851554 ps
CPU time 94.21 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 1140724 kb
Host smart-59fc4952-eb8b-4afc-8b8e-96f992bf4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603253257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3603253257
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_override.2680946231
Short name T755
Test name
Test status
Simulation time 17950642 ps
CPU time 0.64 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:20:45 PM PDT 24
Peak memory 202532 kb
Host smart-db097597-4ff1-43d3-9ede-d67255254122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680946231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2680946231
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1914159841
Short name T737
Test name
Test status
Simulation time 3162236989 ps
CPU time 37.39 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 227752 kb
Host smart-f9e1b728-d06a-4508-aaee-ff0b21c9207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914159841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1914159841
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3804289358
Short name T961
Test name
Test status
Simulation time 6528757856 ps
CPU time 57.94 seconds
Started Mar 21 01:20:45 PM PDT 24
Finished Mar 21 01:21:43 PM PDT 24
Peak memory 306116 kb
Host smart-401f14dd-1bf9-4b3e-a324-f5658474babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804289358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3804289358
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1734030286
Short name T297
Test name
Test status
Simulation time 3290039872 ps
CPU time 3.88 seconds
Started Mar 21 01:20:52 PM PDT 24
Finished Mar 21 01:20:56 PM PDT 24
Peak memory 203396 kb
Host smart-bc899145-aa82-4f41-8d55-e7e345e12d72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734030286 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1734030286
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.713513520
Short name T889
Test name
Test status
Simulation time 10144910973 ps
CPU time 40.9 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:21:32 PM PDT 24
Peak memory 395896 kb
Host smart-c997b59e-b8b6-4860-9b3f-6c473378ed31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713513520 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.713513520
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1871993581
Short name T1032
Test name
Test status
Simulation time 10447405415 ps
CPU time 18.93 seconds
Started Mar 21 01:20:54 PM PDT 24
Finished Mar 21 01:21:13 PM PDT 24
Peak memory 349772 kb
Host smart-92b7513a-e5ee-4e71-a11f-ade1d308764c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871993581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1871993581
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2733973711
Short name T1077
Test name
Test status
Simulation time 2907873327 ps
CPU time 2.06 seconds
Started Mar 21 01:20:55 PM PDT 24
Finished Mar 21 01:20:57 PM PDT 24
Peak memory 203348 kb
Host smart-e8a81aba-3422-4bed-92ad-d7229c055089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733973711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2733973711
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1266146059
Short name T1029
Test name
Test status
Simulation time 2717505531 ps
CPU time 4.59 seconds
Started Mar 21 01:20:49 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 211568 kb
Host smart-6348feae-89d3-4b10-8c24-5338cd6ce95c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266146059 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1266146059
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.888428281
Short name T852
Test name
Test status
Simulation time 1326465140 ps
CPU time 17.58 seconds
Started Mar 21 01:20:49 PM PDT 24
Finished Mar 21 01:21:07 PM PDT 24
Peak memory 203408 kb
Host smart-4f55bad4-1e3b-4843-985f-185c88461bc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888428281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.888428281
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.895972057
Short name T1059
Test name
Test status
Simulation time 2682757490 ps
CPU time 11.39 seconds
Started Mar 21 01:20:50 PM PDT 24
Finished Mar 21 01:21:02 PM PDT 24
Peak memory 208492 kb
Host smart-a6942c32-d391-4912-a588-5f730d74dad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895972057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.895972057
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.129415994
Short name T780
Test name
Test status
Simulation time 24341071284 ps
CPU time 60.6 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:21:52 PM PDT 24
Peak memory 643804 kb
Host smart-4fdfbdd2-efd0-4e56-aec8-fc63c83f391b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129415994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.129415994
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2191153295
Short name T971
Test name
Test status
Simulation time 1215751890 ps
CPU time 6.38 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:20:57 PM PDT 24
Peak memory 211604 kb
Host smart-030d8845-f9ad-4f3e-9b3e-978c2cd09d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191153295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2191153295
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1826377716
Short name T551
Test name
Test status
Simulation time 14717003 ps
CPU time 0.63 seconds
Started Mar 21 01:20:56 PM PDT 24
Finished Mar 21 01:20:56 PM PDT 24
Peak memory 203032 kb
Host smart-5c337a4b-76b1-4f1b-961d-86ef26d09e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826377716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1826377716
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4219290001
Short name T1082
Test name
Test status
Simulation time 44886745 ps
CPU time 1.41 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 211432 kb
Host smart-182a5c38-5cd1-4275-bf06-4f032cb17062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219290001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4219290001
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.4091197584
Short name T622
Test name
Test status
Simulation time 310912079 ps
CPU time 15.29 seconds
Started Mar 21 01:20:50 PM PDT 24
Finished Mar 21 01:21:05 PM PDT 24
Peak memory 252420 kb
Host smart-97781e42-443f-4d42-a648-06355c76555b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091197584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.4091197584
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1909555653
Short name T995
Test name
Test status
Simulation time 10487979634 ps
CPU time 149.94 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 700256 kb
Host smart-0732e5f1-c298-4a50-8256-91c80e32caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909555653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1909555653
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.616685364
Short name T584
Test name
Test status
Simulation time 6841164172 ps
CPU time 128.87 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:23:00 PM PDT 24
Peak memory 629264 kb
Host smart-2632c5d8-0678-43ef-9d3d-147f0d1acc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616685364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.616685364
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.961748599
Short name T191
Test name
Test status
Simulation time 94512855 ps
CPU time 0.79 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:20:52 PM PDT 24
Peak memory 202968 kb
Host smart-427e02c0-a71a-471f-99ac-99be799bb93e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961748599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.961748599
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2967011947
Short name T1056
Test name
Test status
Simulation time 294312585 ps
CPU time 3.58 seconds
Started Mar 21 01:20:54 PM PDT 24
Finished Mar 21 01:20:58 PM PDT 24
Peak memory 203228 kb
Host smart-d0597b1c-849b-4eee-87d8-8da98281d38a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967011947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2967011947
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2313978481
Short name T164
Test name
Test status
Simulation time 2682627434 ps
CPU time 53.17 seconds
Started Mar 21 01:20:49 PM PDT 24
Finished Mar 21 01:21:42 PM PDT 24
Peak memory 697128 kb
Host smart-38ef3a47-09c6-4b3a-ad10-df235959a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313978481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2313978481
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_override.2561929448
Short name T733
Test name
Test status
Simulation time 35639839 ps
CPU time 0.63 seconds
Started Mar 21 01:20:50 PM PDT 24
Finished Mar 21 01:20:50 PM PDT 24
Peak memory 202560 kb
Host smart-e76d8153-9dc2-4a90-b16a-4095e1c1275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561929448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2561929448
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1315515011
Short name T13
Test name
Test status
Simulation time 51758950606 ps
CPU time 877.29 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:35:26 PM PDT 24
Peak memory 285020 kb
Host smart-8099154c-93ca-43d2-9311-192e0bd0835a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315515011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1315515011
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.389294879
Short name T748
Test name
Test status
Simulation time 1694617013 ps
CPU time 79.53 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 396376 kb
Host smart-6221a727-7b67-4b7f-b1c2-73a1416edcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389294879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.389294879
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1105659988
Short name T582
Test name
Test status
Simulation time 3577412581 ps
CPU time 2.98 seconds
Started Mar 21 01:21:00 PM PDT 24
Finished Mar 21 01:21:03 PM PDT 24
Peak memory 203416 kb
Host smart-972de784-2895-424f-a09d-afc4e60ae50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105659988 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1105659988
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4228378189
Short name T69
Test name
Test status
Simulation time 10050138251 ps
CPU time 32.89 seconds
Started Mar 21 01:20:55 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 397656 kb
Host smart-32072958-6823-46c0-9c2b-17c74bba83c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228378189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4228378189
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1418844136
Short name T823
Test name
Test status
Simulation time 10070131036 ps
CPU time 104.81 seconds
Started Mar 21 01:20:56 PM PDT 24
Finished Mar 21 01:22:41 PM PDT 24
Peak memory 722528 kb
Host smart-e969fb19-2852-4318-b690-e11cc4ecf368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418844136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1418844136
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1085633626
Short name T662
Test name
Test status
Simulation time 1361287508 ps
CPU time 2.09 seconds
Started Mar 21 01:21:03 PM PDT 24
Finished Mar 21 01:21:06 PM PDT 24
Peak memory 203344 kb
Host smart-d8a391e6-ab9c-4d55-a322-4e4bbdf97da9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085633626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1085633626
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2729563715
Short name T962
Test name
Test status
Simulation time 15027961693 ps
CPU time 5.67 seconds
Started Mar 21 01:20:55 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 211580 kb
Host smart-a4939376-8ed1-4990-9cd1-ded8e8472c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729563715 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2729563715
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3336342288
Short name T5
Test name
Test status
Simulation time 8808633553 ps
CPU time 12.55 seconds
Started Mar 21 01:20:48 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 203332 kb
Host smart-1a52bdef-fcfd-48f1-b9fe-c1c7be4dc721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336342288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3336342288
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3381591073
Short name T814
Test name
Test status
Simulation time 1170471327 ps
CPU time 26.55 seconds
Started Mar 21 01:20:51 PM PDT 24
Finished Mar 21 01:21:18 PM PDT 24
Peak memory 203424 kb
Host smart-554fbed8-9a9b-4f58-9180-9380ad1d4916
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381591073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3381591073
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.400354865
Short name T268
Test name
Test status
Simulation time 10647474080 ps
CPU time 104.69 seconds
Started Mar 21 01:20:57 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 1613572 kb
Host smart-a545b074-c957-4fdc-9172-a7591d68d9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400354865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.400354865
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1499813836
Short name T682
Test name
Test status
Simulation time 2609156092 ps
CPU time 6.82 seconds
Started Mar 21 01:20:59 PM PDT 24
Finished Mar 21 01:21:06 PM PDT 24
Peak memory 209400 kb
Host smart-5094c5e2-c890-4422-a624-7c3b02161998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499813836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1499813836
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2724273512
Short name T771
Test name
Test status
Simulation time 16041322 ps
CPU time 0.63 seconds
Started Mar 21 01:21:06 PM PDT 24
Finished Mar 21 01:21:07 PM PDT 24
Peak memory 203028 kb
Host smart-685626a4-908e-446d-9c76-e7f26fc489d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724273512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2724273512
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1189750095
Short name T827
Test name
Test status
Simulation time 159858393 ps
CPU time 1.46 seconds
Started Mar 21 01:21:06 PM PDT 24
Finished Mar 21 01:21:08 PM PDT 24
Peak memory 211444 kb
Host smart-2ee80fde-2830-4c3e-a76a-c5fddabd8286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189750095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1189750095
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2921537659
Short name T304
Test name
Test status
Simulation time 940860551 ps
CPU time 11.02 seconds
Started Mar 21 01:21:03 PM PDT 24
Finished Mar 21 01:21:15 PM PDT 24
Peak memory 245808 kb
Host smart-1801dee2-7b7b-41d1-8b46-cb6ad71800d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921537659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2921537659
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2854529176
Short name T350
Test name
Test status
Simulation time 2028469116 ps
CPU time 145.87 seconds
Started Mar 21 01:21:00 PM PDT 24
Finished Mar 21 01:23:26 PM PDT 24
Peak memory 701892 kb
Host smart-30f6f733-92f0-47d4-ae64-e8a55f2440d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854529176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2854529176
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3440924910
Short name T698
Test name
Test status
Simulation time 7041446992 ps
CPU time 128.13 seconds
Started Mar 21 01:20:57 PM PDT 24
Finished Mar 21 01:23:06 PM PDT 24
Peak memory 614596 kb
Host smart-013fab98-629f-407e-bfeb-d22b672b5bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440924910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3440924910
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2232129327
Short name T882
Test name
Test status
Simulation time 148659184 ps
CPU time 0.89 seconds
Started Mar 21 01:20:59 PM PDT 24
Finished Mar 21 01:21:00 PM PDT 24
Peak memory 202500 kb
Host smart-e1d647da-681b-455e-8af1-61a188a46b12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232129327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2232129327
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.90424256
Short name T453
Test name
Test status
Simulation time 184164882 ps
CPU time 2.27 seconds
Started Mar 21 01:20:58 PM PDT 24
Finished Mar 21 01:21:00 PM PDT 24
Peak memory 203348 kb
Host smart-1cf0b712-3c10-419c-9b82-6f30bf3dc83e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90424256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.90424256
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_override.886066096
Short name T1075
Test name
Test status
Simulation time 17419778 ps
CPU time 0.65 seconds
Started Mar 21 01:21:01 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 202576 kb
Host smart-45b95e3a-de5b-43d8-bb16-b770cd09c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886066096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.886066096
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2106757428
Short name T778
Test name
Test status
Simulation time 4642416611 ps
CPU time 28.48 seconds
Started Mar 21 01:20:57 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 255160 kb
Host smart-4f6ab579-f1d0-4941-a64c-5be34ed8b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106757428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2106757428
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.18864694
Short name T397
Test name
Test status
Simulation time 1207105151 ps
CPU time 41.28 seconds
Started Mar 21 01:21:04 PM PDT 24
Finished Mar 21 01:21:45 PM PDT 24
Peak memory 301576 kb
Host smart-39d043f7-19f1-4bb0-8348-dad5e7cd0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18864694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.18864694
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2741296108
Short name T244
Test name
Test status
Simulation time 468945433 ps
CPU time 2.31 seconds
Started Mar 21 01:20:59 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 203400 kb
Host smart-fa09ee8f-3783-4dfd-82e1-386002e6ba58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741296108 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2741296108
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3512625683
Short name T685
Test name
Test status
Simulation time 10080383094 ps
CPU time 71.55 seconds
Started Mar 21 01:21:32 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 567652 kb
Host smart-7c20ff07-b8e6-4e03-8a94-4225ec26e3da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512625683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3512625683
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.221891167
Short name T322
Test name
Test status
Simulation time 10144651436 ps
CPU time 34.2 seconds
Started Mar 21 01:21:01 PM PDT 24
Finished Mar 21 01:21:35 PM PDT 24
Peak memory 456200 kb
Host smart-1e6d4dce-97c7-4eb0-8abd-f16bd42f9fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221891167 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.221891167
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1030856868
Short name T730
Test name
Test status
Simulation time 521377491 ps
CPU time 2.93 seconds
Started Mar 21 01:20:58 PM PDT 24
Finished Mar 21 01:21:01 PM PDT 24
Peak memory 203364 kb
Host smart-569f45cf-0743-4c7b-a62f-847ad4501f39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030856868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1030856868
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3862451775
Short name T892
Test name
Test status
Simulation time 1037138786 ps
CPU time 3.38 seconds
Started Mar 21 01:21:10 PM PDT 24
Finished Mar 21 01:21:14 PM PDT 24
Peak memory 203280 kb
Host smart-78bc066f-bf0a-46e3-a5c6-44250b46c4da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862451775 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3862451775
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3076323069
Short name T571
Test name
Test status
Simulation time 2220722752 ps
CPU time 18.6 seconds
Started Mar 21 01:21:02 PM PDT 24
Finished Mar 21 01:21:20 PM PDT 24
Peak memory 203424 kb
Host smart-ba28a3f5-5ae7-47fc-8920-fd4ca95bbde0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076323069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3076323069
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.233571930
Short name T626
Test name
Test status
Simulation time 6213757888 ps
CPU time 29.09 seconds
Started Mar 21 01:20:59 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 219816 kb
Host smart-826e3953-1775-4069-8e2a-c4c24ffbf9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233571930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.233571930
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3492774703
Short name T863
Test name
Test status
Simulation time 688902882 ps
CPU time 9.81 seconds
Started Mar 21 01:21:05 PM PDT 24
Finished Mar 21 01:21:15 PM PDT 24
Peak memory 203780 kb
Host smart-0b7494a4-093e-4439-8013-2bc9bced15ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492774703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3492774703
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.790212904
Short name T729
Test name
Test status
Simulation time 1424752143 ps
CPU time 6.87 seconds
Started Mar 21 01:20:56 PM PDT 24
Finished Mar 21 01:21:03 PM PDT 24
Peak memory 203316 kb
Host smart-cfd715c0-5843-4900-ad2f-88f6c4ce0fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790212904 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.790212904
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3049870526
Short name T811
Test name
Test status
Simulation time 33544695 ps
CPU time 0.61 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:19 PM PDT 24
Peak memory 203116 kb
Host smart-35fbbe3a-9c13-46e5-8cc8-e11e47cd66ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049870526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3049870526
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1317831538
Short name T200
Test name
Test status
Simulation time 58653762 ps
CPU time 1.7 seconds
Started Mar 21 01:21:17 PM PDT 24
Finished Mar 21 01:21:19 PM PDT 24
Peak memory 214980 kb
Host smart-fdde6428-e924-40b2-99cf-21b0fa3ec1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317831538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1317831538
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.689657186
Short name T577
Test name
Test status
Simulation time 490848389 ps
CPU time 5.78 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:27 PM PDT 24
Peak memory 246592 kb
Host smart-28be6ec7-e6af-4661-b338-fee79a0c0fec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689657186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.689657186
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.446700037
Short name T472
Test name
Test status
Simulation time 1358377719 ps
CPU time 67.93 seconds
Started Mar 21 01:21:28 PM PDT 24
Finished Mar 21 01:22:36 PM PDT 24
Peak memory 285212 kb
Host smart-14267125-07f2-45c9-8f3f-e57c872c3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446700037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.446700037
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2869238693
Short name T27
Test name
Test status
Simulation time 2235200449 ps
CPU time 33.15 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:56 PM PDT 24
Peak memory 469200 kb
Host smart-ef2a0d7c-e1af-4785-a09d-51b5edeb6d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869238693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2869238693
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3149845601
Short name T152
Test name
Test status
Simulation time 117282045 ps
CPU time 0.85 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:23 PM PDT 24
Peak memory 202628 kb
Host smart-e7f37ad3-1bec-431f-9c42-d1d8500ffccc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149845601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3149845601
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2348374910
Short name T1039
Test name
Test status
Simulation time 368877567 ps
CPU time 2.75 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:24 PM PDT 24
Peak memory 215556 kb
Host smart-ec201895-0714-4ec1-850c-5bf48983330a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348374910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2348374910
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1715428392
Short name T145
Test name
Test status
Simulation time 15282632640 ps
CPU time 115.14 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:23:14 PM PDT 24
Peak memory 1231188 kb
Host smart-1b3a9fc3-86e4-4576-88ec-d594bf374e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715428392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1715428392
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_override.931889212
Short name T178
Test name
Test status
Simulation time 26164509 ps
CPU time 0.61 seconds
Started Mar 21 01:21:17 PM PDT 24
Finished Mar 21 01:21:18 PM PDT 24
Peak memory 202552 kb
Host smart-8fc61e08-f9b1-4b05-ba56-5c043f8bca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931889212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.931889212
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1246144682
Short name T891
Test name
Test status
Simulation time 1329646492 ps
CPU time 48 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 329652 kb
Host smart-4cb86b62-b255-4c45-8f1c-cef46c613efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246144682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1246144682
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3457900606
Short name T65
Test name
Test status
Simulation time 55194977376 ps
CPU time 216.88 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 843688 kb
Host smart-e679de25-e1e6-4623-bf9d-a4070703110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457900606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3457900606
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1238041780
Short name T835
Test name
Test status
Simulation time 1778786734 ps
CPU time 4.11 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 203392 kb
Host smart-f70b2759-a9ca-48ea-a01d-387ba960a2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238041780 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1238041780
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1318433680
Short name T1046
Test name
Test status
Simulation time 10077655794 ps
CPU time 33.29 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:54 PM PDT 24
Peak memory 373064 kb
Host smart-1bbfe100-86ca-4155-8b5c-f00cb65bf881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318433680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1318433680
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.4032940947
Short name T958
Test name
Test status
Simulation time 10885007643 ps
CPU time 11.11 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:33 PM PDT 24
Peak memory 304156 kb
Host smart-303da291-0431-4448-a70b-58e4cf0dc21b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032940947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.4032940947
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1276346804
Short name T1057
Test name
Test status
Simulation time 600859924 ps
CPU time 2.79 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:21 PM PDT 24
Peak memory 203436 kb
Host smart-184e14e6-6d0b-4dd8-b852-656658de8582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276346804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1276346804
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3790516059
Short name T837
Test name
Test status
Simulation time 901042594 ps
CPU time 4.66 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 206968 kb
Host smart-972b28bf-ff12-42d9-98e4-2486bdbdd755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790516059 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3790516059
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1477316541
Short name T328
Test name
Test status
Simulation time 9503138561 ps
CPU time 44.18 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:22:06 PM PDT 24
Peak memory 203428 kb
Host smart-010e821c-9482-4fdd-a2ee-d5ad1cea52f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477316541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1477316541
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1082166705
Short name T616
Test name
Test status
Simulation time 965897226 ps
CPU time 18.09 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:36 PM PDT 24
Peak memory 209732 kb
Host smart-c31c340a-5a84-4160-bc0d-e59fa3c7dc32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082166705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1082166705
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3078711018
Short name T1028
Test name
Test status
Simulation time 23962238621 ps
CPU time 1589.6 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:47:52 PM PDT 24
Peak memory 3024160 kb
Host smart-54cd81ac-4bf2-4f42-8178-d709f06610e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078711018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3078711018
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2908414759
Short name T516
Test name
Test status
Simulation time 14728716474 ps
CPU time 6.32 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 211588 kb
Host smart-0e7a701b-391e-475a-8895-79f447398068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908414759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2908414759
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1010976408
Short name T700
Test name
Test status
Simulation time 16604247 ps
CPU time 0.62 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 203048 kb
Host smart-b8803a56-eecf-42f7-ba15-137d8193a0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010976408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1010976408
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2490565828
Short name T969
Test name
Test status
Simulation time 93345659 ps
CPU time 1.03 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 203408 kb
Host smart-3092e662-ace1-4c2e-ab90-8ae93e47c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490565828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2490565828
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3286077643
Short name T945
Test name
Test status
Simulation time 2023219123 ps
CPU time 11.37 seconds
Started Mar 21 01:21:20 PM PDT 24
Finished Mar 21 01:21:31 PM PDT 24
Peak memory 319740 kb
Host smart-d92395a6-1047-4aa9-9b6f-a3f2990af719
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286077643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3286077643
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1882656911
Short name T763
Test name
Test status
Simulation time 1807425226 ps
CPU time 119.58 seconds
Started Mar 21 01:21:20 PM PDT 24
Finished Mar 21 01:23:20 PM PDT 24
Peak memory 633848 kb
Host smart-d3561a80-65f0-44c2-82d0-e3db4aec89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882656911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1882656911
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.4078478287
Short name T926
Test name
Test status
Simulation time 4572575286 ps
CPU time 84.07 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 750512 kb
Host smart-6f68104c-ea74-469f-93c4-1d3da56110f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078478287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.4078478287
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1963295121
Short name T324
Test name
Test status
Simulation time 242632834 ps
CPU time 6.59 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 222188 kb
Host smart-0a36a938-c056-4783-add0-bdaad39e433c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963295121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1963295121
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.732786799
Short name T734
Test name
Test status
Simulation time 23287179362 ps
CPU time 71.8 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 957232 kb
Host smart-42f5c5c8-9a20-418d-b7fb-776595b10033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732786799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.732786799
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_override.1896788584
Short name T478
Test name
Test status
Simulation time 19774932 ps
CPU time 0.65 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 202504 kb
Host smart-9bf3b476-8287-422b-811b-6da1d08cf3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896788584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1896788584
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3943769736
Short name T978
Test name
Test status
Simulation time 18118869692 ps
CPU time 1878.42 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:52:37 PM PDT 24
Peak memory 716428 kb
Host smart-f99d0859-c970-46df-be6d-47046ffd2d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943769736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3943769736
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3790403809
Short name T924
Test name
Test status
Simulation time 3374811297 ps
CPU time 86.99 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:22:49 PM PDT 24
Peak memory 284332 kb
Host smart-2702386a-ba01-4e49-b545-512182a3e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790403809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3790403809
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2261063773
Short name T858
Test name
Test status
Simulation time 965534410 ps
CPU time 4.21 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:27 PM PDT 24
Peak memory 211480 kb
Host smart-99a83d42-7775-492e-bec0-d2db01086d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261063773 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2261063773
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3077662650
Short name T1090
Test name
Test status
Simulation time 10591610861 ps
CPU time 8.28 seconds
Started Mar 21 01:21:17 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 251876 kb
Host smart-e6017eb0-d51b-41b6-b1a0-769334f987bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077662650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3077662650
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2049699007
Short name T736
Test name
Test status
Simulation time 10087585621 ps
CPU time 101.58 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:23:05 PM PDT 24
Peak memory 758040 kb
Host smart-c218d510-b977-4b34-a66a-f09080e40295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049699007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2049699007
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3859612507
Short name T897
Test name
Test status
Simulation time 1704852671 ps
CPU time 2.57 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:24 PM PDT 24
Peak memory 203300 kb
Host smart-ffe38335-680b-470b-aed7-d79fad05d530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859612507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3859612507
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2181669388
Short name T303
Test name
Test status
Simulation time 2372265282 ps
CPU time 5.57 seconds
Started Mar 21 01:21:20 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 214644 kb
Host smart-14a9b664-1d66-4325-878a-02bd9e93c694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181669388 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2181669388
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1562072095
Short name T527
Test name
Test status
Simulation time 997990756 ps
CPU time 37.34 seconds
Started Mar 21 01:21:20 PM PDT 24
Finished Mar 21 01:21:58 PM PDT 24
Peak memory 203332 kb
Host smart-31e32d00-8aa1-4393-8468-ed4457824dfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562072095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1562072095
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1999877680
Short name T506
Test name
Test status
Simulation time 2220683201 ps
CPU time 27.69 seconds
Started Mar 21 01:21:17 PM PDT 24
Finished Mar 21 01:21:45 PM PDT 24
Peak memory 227680 kb
Host smart-2fecdc00-051f-441c-8bbc-b802b61d0ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999877680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1999877680
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1465292481
Short name T671
Test name
Test status
Simulation time 18719463351 ps
CPU time 24.56 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:43 PM PDT 24
Peak memory 398916 kb
Host smart-24b147c9-d135-4902-876d-aace2ec05e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465292481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1465292481
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1324026683
Short name T952
Test name
Test status
Simulation time 5917266787 ps
CPU time 7.69 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:30 PM PDT 24
Peak memory 216780 kb
Host smart-6e036b26-7aa1-4779-9e9c-c9052b0ebcdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324026683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1324026683
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.1587773863
Short name T54
Test name
Test status
Simulation time 1402201331 ps
CPU time 4.19 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 203296 kb
Host smart-56649922-7cf5-4c63-a39e-3f75e740508b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587773863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.1587773863
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1981280379
Short name T849
Test name
Test status
Simulation time 34329641 ps
CPU time 0.62 seconds
Started Mar 21 01:21:27 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 203168 kb
Host smart-5c333a90-18a7-4a43-8a03-f7779e52fbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981280379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1981280379
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.625625557
Short name T992
Test name
Test status
Simulation time 41565294 ps
CPU time 1.32 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 211580 kb
Host smart-4d13835c-8027-4666-a12c-6650f7e1943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625625557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.625625557
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1293351268
Short name T828
Test name
Test status
Simulation time 514879377 ps
CPU time 6.05 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:21:30 PM PDT 24
Peak memory 257796 kb
Host smart-f798dbe4-051c-4c9b-8a6c-7885bf244ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293351268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1293351268
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3821808152
Short name T407
Test name
Test status
Simulation time 1344483351 ps
CPU time 45.23 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:22:06 PM PDT 24
Peak memory 526008 kb
Host smart-329696dd-8d01-44c7-b2f6-d61d55b6b758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821808152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3821808152
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2070648563
Short name T787
Test name
Test status
Simulation time 1468437364 ps
CPU time 40.75 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:22:03 PM PDT 24
Peak memory 553264 kb
Host smart-9e52f56e-7353-49e6-a2d5-55eadca54e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070648563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2070648563
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2857339691
Short name T913
Test name
Test status
Simulation time 726231883 ps
CPU time 0.92 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:23 PM PDT 24
Peak memory 203032 kb
Host smart-50c23113-4e0e-44c8-8236-81ad87a53182
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857339691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2857339691
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.611585254
Short name T851
Test name
Test status
Simulation time 130784471 ps
CPU time 7.08 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 203336 kb
Host smart-c258aa88-c697-481d-82d3-e6891401b8b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611585254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
611585254
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1443231545
Short name T717
Test name
Test status
Simulation time 3788271933 ps
CPU time 109.38 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:23:13 PM PDT 24
Peak memory 1107836 kb
Host smart-3a31a969-4f63-47b0-b59c-94d254959b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443231545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1443231545
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_override.2298092022
Short name T167
Test name
Test status
Simulation time 62946654 ps
CPU time 0.62 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:19 PM PDT 24
Peak memory 202560 kb
Host smart-49fbf527-2b34-4387-82e2-b9bdc06d6526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298092022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2298092022
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.10279635
Short name T950
Test name
Test status
Simulation time 27448278781 ps
CPU time 38.67 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:22:00 PM PDT 24
Peak memory 203344 kb
Host smart-8c4298b6-3720-4cad-a847-97d434bd747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10279635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.10279635
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.496752529
Short name T927
Test name
Test status
Simulation time 10577685621 ps
CPU time 26.2 seconds
Started Mar 21 01:21:18 PM PDT 24
Finished Mar 21 01:21:44 PM PDT 24
Peak memory 268324 kb
Host smart-1c72441f-2ced-4e55-81d8-aa4af98259fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496752529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.496752529
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.4061277640
Short name T20
Test name
Test status
Simulation time 643858719 ps
CPU time 3.21 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 203308 kb
Host smart-862a79b7-03ca-4d03-8fa7-3de0a83150f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061277640 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4061277640
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2260323687
Short name T412
Test name
Test status
Simulation time 10413774063 ps
CPU time 13.26 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:21:37 PM PDT 24
Peak memory 305768 kb
Host smart-b7e891dd-acdd-4271-9f8b-a1e36c1012cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260323687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2260323687
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.220340901
Short name T55
Test name
Test status
Simulation time 10060472324 ps
CPU time 100.94 seconds
Started Mar 21 01:21:27 PM PDT 24
Finished Mar 21 01:23:09 PM PDT 24
Peak memory 748416 kb
Host smart-944ea6d8-8338-4acb-84ca-af12b7c3174f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220340901 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.220340901
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2614982473
Short name T680
Test name
Test status
Simulation time 528157619 ps
CPU time 2.96 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:27 PM PDT 24
Peak memory 203392 kb
Host smart-5b2d0248-ad24-4cfe-a1a0-5aa599fe4906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614982473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2614982473
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1915413659
Short name T568
Test name
Test status
Simulation time 6006946749 ps
CPU time 5.31 seconds
Started Mar 21 01:21:27 PM PDT 24
Finished Mar 21 01:21:32 PM PDT 24
Peak memory 205408 kb
Host smart-aa9eb74f-9b4d-41f7-8595-ad80a8994258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915413659 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1915413659
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2363181898
Short name T840
Test name
Test status
Simulation time 3783410304 ps
CPU time 35.35 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:59 PM PDT 24
Peak memory 203312 kb
Host smart-87beb484-b535-4d69-bdcc-071e75974435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363181898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2363181898
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.1021432711
Short name T756
Test name
Test status
Simulation time 9549555937 ps
CPU time 45.07 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 230904 kb
Host smart-70f9a2c3-71e0-447d-9566-924344648c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021432711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.1021432711
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2743699720
Short name T666
Test name
Test status
Simulation time 16358525835 ps
CPU time 15.53 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 212112 kb
Host smart-22d660cd-ab5d-48b1-9fef-ad5fc1b11337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743699720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2743699720
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.312392818
Short name T318
Test name
Test status
Simulation time 22374161287 ps
CPU time 10.83 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:33 PM PDT 24
Peak memory 203472 kb
Host smart-0ff5891e-e999-4393-9689-49f85720d1b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312392818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.312392818
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.4194310533
Short name T469
Test name
Test status
Simulation time 21343700001 ps
CPU time 293.9 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:26:17 PM PDT 24
Peak memory 1163116 kb
Host smart-124986e6-e745-4b7d-9ff4-52e400304767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194310533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.4194310533
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1425708226
Short name T719
Test name
Test status
Simulation time 13524758388 ps
CPU time 7.38 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:21:34 PM PDT 24
Peak memory 203492 kb
Host smart-ec503aed-bcfd-433e-9aba-2ae50253d7dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425708226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1425708226
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.4099144470
Short name T420
Test name
Test status
Simulation time 28732717 ps
CPU time 0.65 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 203088 kb
Host smart-30fc4cd9-1415-4eae-bbb8-65b04094fbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099144470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.4099144470
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3787731411
Short name T668
Test name
Test status
Simulation time 99716574 ps
CPU time 1.12 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 211464 kb
Host smart-b2b1ba4c-43c6-4831-bdc5-9f3f72b7e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787731411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3787731411
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3830840174
Short name T487
Test name
Test status
Simulation time 237908554 ps
CPU time 4.98 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:21:32 PM PDT 24
Peak memory 251752 kb
Host smart-bf24ab40-98e1-461a-95e0-83c2fbbcbc0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830840174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3830840174
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1445689922
Short name T749
Test name
Test status
Simulation time 7607107453 ps
CPU time 128.85 seconds
Started Mar 21 01:21:27 PM PDT 24
Finished Mar 21 01:23:36 PM PDT 24
Peak memory 599856 kb
Host smart-e5c19cb3-c37e-4842-ae06-3859d20aa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445689922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1445689922
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1061350068
Short name T526
Test name
Test status
Simulation time 6862715723 ps
CPU time 136.11 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:23:41 PM PDT 24
Peak memory 631592 kb
Host smart-b42d3e54-5f2d-44d4-9934-10fb0950043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061350068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1061350068
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.918585908
Short name T32
Test name
Test status
Simulation time 256328969 ps
CPU time 1 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:22 PM PDT 24
Peak memory 202860 kb
Host smart-7c582c83-dead-4271-9f21-80dbc5c20edd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918585908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.918585908
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.4057777437
Short name T523
Test name
Test status
Simulation time 681167243 ps
CPU time 4.13 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:21:29 PM PDT 24
Peak memory 202976 kb
Host smart-a8790f52-60c2-4464-bf57-4096371e298f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057777437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.4057777437
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_override.122960572
Short name T1070
Test name
Test status
Simulation time 18085813 ps
CPU time 0.66 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:21:25 PM PDT 24
Peak memory 202496 kb
Host smart-a2ea6e3a-0a52-4d74-9cff-bd0af26d8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122960572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.122960572
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.131380574
Short name T279
Test name
Test status
Simulation time 7834262016 ps
CPU time 154.28 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 306584 kb
Host smart-10ee5318-fdb1-4eff-8b10-e56b8a9f960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131380574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.131380574
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3731961505
Short name T385
Test name
Test status
Simulation time 2468536647 ps
CPU time 4.42 seconds
Started Mar 21 01:21:27 PM PDT 24
Finished Mar 21 01:21:32 PM PDT 24
Peak memory 203496 kb
Host smart-92276e45-b062-410d-8676-2e287cf39640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731961505 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3731961505
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2600181692
Short name T710
Test name
Test status
Simulation time 10436421609 ps
CPU time 13.15 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:37 PM PDT 24
Peak memory 291804 kb
Host smart-6684e9e4-0156-4ae5-91f4-d494b01d2c59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600181692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2600181692
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.949500426
Short name T482
Test name
Test status
Simulation time 10619354958 ps
CPU time 8.32 seconds
Started Mar 21 01:21:25 PM PDT 24
Finished Mar 21 01:21:33 PM PDT 24
Peak memory 261028 kb
Host smart-f2bd730c-df5f-415c-a3b7-2f077d8fb505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949500426 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.949500426
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3347842741
Short name T159
Test name
Test status
Simulation time 1390110116 ps
CPU time 2.19 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:21:29 PM PDT 24
Peak memory 203420 kb
Host smart-d9fdccc0-14ff-485c-8c71-b6a5099d4a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347842741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3347842741
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2719329396
Short name T106
Test name
Test status
Simulation time 6828791784 ps
CPU time 4.12 seconds
Started Mar 21 01:21:28 PM PDT 24
Finished Mar 21 01:21:32 PM PDT 24
Peak memory 203436 kb
Host smart-4c1e5c33-0478-44ff-83e9-649b1864ddf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719329396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2719329396
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2043500335
Short name T713
Test name
Test status
Simulation time 2670161844 ps
CPU time 24.11 seconds
Started Mar 21 01:21:23 PM PDT 24
Finished Mar 21 01:21:47 PM PDT 24
Peak memory 203408 kb
Host smart-d2d5a308-3440-4b7b-84b6-d811cb0bfdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043500335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2043500335
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3075366032
Short name T116
Test name
Test status
Simulation time 1378589564 ps
CPU time 20.75 seconds
Started Mar 21 01:21:26 PM PDT 24
Finished Mar 21 01:21:47 PM PDT 24
Peak memory 228196 kb
Host smart-4db3e9fa-47af-4045-8c73-e65a1056a2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075366032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3075366032
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.742027776
Short name T856
Test name
Test status
Simulation time 15450270602 ps
CPU time 257.04 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:25:41 PM PDT 24
Peak memory 2004144 kb
Host smart-4b530435-95ff-4298-bf34-c64f93930f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742027776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.742027776
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3389049092
Short name T435
Test name
Test status
Simulation time 1122183025 ps
CPU time 5.93 seconds
Started Mar 21 01:21:21 PM PDT 24
Finished Mar 21 01:21:28 PM PDT 24
Peak memory 215516 kb
Host smart-40183fe3-3d9b-41f2-8bbe-8d706d1a94bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389049092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3389049092
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.4180894422
Short name T25
Test name
Test status
Simulation time 850322956 ps
CPU time 6.27 seconds
Started Mar 21 01:21:31 PM PDT 24
Finished Mar 21 01:21:37 PM PDT 24
Peak memory 203328 kb
Host smart-1a8fda47-982a-4a4b-bd2b-dd7141b3a1ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180894422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.4180894422
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.500942609
Short name T562
Test name
Test status
Simulation time 14148239 ps
CPU time 0.6 seconds
Started Mar 21 01:21:36 PM PDT 24
Finished Mar 21 01:21:38 PM PDT 24
Peak memory 202980 kb
Host smart-9e8c895d-4800-44dc-9a2e-e20f19a039da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500942609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.500942609
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1823880744
Short name T49
Test name
Test status
Simulation time 176324788 ps
CPU time 1.34 seconds
Started Mar 21 01:21:39 PM PDT 24
Finished Mar 21 01:21:41 PM PDT 24
Peak memory 211544 kb
Host smart-e2b08226-67c1-494b-8f68-c6ba3a7bd269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823880744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1823880744
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.611185817
Short name T259
Test name
Test status
Simulation time 145141903 ps
CPU time 3.26 seconds
Started Mar 21 01:21:34 PM PDT 24
Finished Mar 21 01:21:37 PM PDT 24
Peak memory 226900 kb
Host smart-8c1944df-2267-4f6c-9721-9e15f6759f57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611185817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.611185817
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2474325565
Short name T74
Test name
Test status
Simulation time 4367234237 ps
CPU time 64.58 seconds
Started Mar 21 01:21:35 PM PDT 24
Finished Mar 21 01:22:40 PM PDT 24
Peak memory 559804 kb
Host smart-99e203d2-96d7-4d9a-8b56-53ee40e1cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474325565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2474325565
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1639008867
Short name T765
Test name
Test status
Simulation time 1413530331 ps
CPU time 34.25 seconds
Started Mar 21 01:21:31 PM PDT 24
Finished Mar 21 01:22:05 PM PDT 24
Peak memory 490604 kb
Host smart-b2465bdb-fc34-4188-a7ad-910f058f0724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639008867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1639008867
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1599916183
Short name T533
Test name
Test status
Simulation time 139782033 ps
CPU time 1.08 seconds
Started Mar 21 01:21:35 PM PDT 24
Finished Mar 21 01:21:36 PM PDT 24
Peak memory 203308 kb
Host smart-fc1e0757-28ba-4696-ada9-703f2c2faffa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599916183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1599916183
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1094598461
Short name T552
Test name
Test status
Simulation time 284282588 ps
CPU time 4.18 seconds
Started Mar 21 01:21:37 PM PDT 24
Finished Mar 21 01:21:41 PM PDT 24
Peak memory 227356 kb
Host smart-6c307be2-0728-4a44-97d4-32375e3fab28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094598461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1094598461
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2020428747
Short name T606
Test name
Test status
Simulation time 4924485876 ps
CPU time 162.47 seconds
Started Mar 21 01:21:24 PM PDT 24
Finished Mar 21 01:24:07 PM PDT 24
Peak memory 1356212 kb
Host smart-91f06aee-f519-48c8-99bc-a2e49c9eeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020428747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2020428747
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_override.1959282358
Short name T250
Test name
Test status
Simulation time 37798876 ps
CPU time 0.63 seconds
Started Mar 21 01:21:25 PM PDT 24
Finished Mar 21 01:21:26 PM PDT 24
Peak memory 202428 kb
Host smart-b46e4cce-9825-4a15-bd0d-f0aa874867f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959282358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1959282358
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2700398731
Short name T182
Test name
Test status
Simulation time 14086559139 ps
CPU time 188.06 seconds
Started Mar 21 01:21:36 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 306188 kb
Host smart-74955174-d066-42e3-a73a-5f85f899a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700398731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2700398731
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1904879218
Short name T391
Test name
Test status
Simulation time 5609407025 ps
CPU time 23.57 seconds
Started Mar 21 01:21:22 PM PDT 24
Finished Mar 21 01:21:45 PM PDT 24
Peak memory 267496 kb
Host smart-deb661b0-0584-4b2d-862c-b4fdc7245f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904879218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1904879218
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2830326964
Short name T189
Test name
Test status
Simulation time 65184192971 ps
CPU time 1120.99 seconds
Started Mar 21 01:21:36 PM PDT 24
Finished Mar 21 01:40:17 PM PDT 24
Peak memory 1521716 kb
Host smart-5ddbc751-27cd-44ae-8925-bbf1d800abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830326964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2830326964
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3271370295
Short name T1005
Test name
Test status
Simulation time 720346695 ps
CPU time 4.13 seconds
Started Mar 21 01:21:35 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 211560 kb
Host smart-76269039-0409-4719-a604-0d8f60c4cfcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271370295 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3271370295
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3211614681
Short name T726
Test name
Test status
Simulation time 10046006746 ps
CPU time 92.78 seconds
Started Mar 21 01:21:37 PM PDT 24
Finished Mar 21 01:23:10 PM PDT 24
Peak memory 584944 kb
Host smart-5c73e6aa-d561-43ea-96d7-281688db82d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211614681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3211614681
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1683372215
Short name T387
Test name
Test status
Simulation time 10028457739 ps
CPU time 91.04 seconds
Started Mar 21 01:21:34 PM PDT 24
Finished Mar 21 01:23:05 PM PDT 24
Peak memory 690904 kb
Host smart-84f76d02-321e-4761-9f5d-94a434916d36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683372215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1683372215
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1230174765
Short name T646
Test name
Test status
Simulation time 2679446966 ps
CPU time 2.26 seconds
Started Mar 21 01:21:33 PM PDT 24
Finished Mar 21 01:21:35 PM PDT 24
Peak memory 203392 kb
Host smart-5a0447d7-3528-4d3e-a7c2-c30abbda6827
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230174765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1230174765
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2744128999
Short name T687
Test name
Test status
Simulation time 3571743709 ps
CPU time 4.57 seconds
Started Mar 21 01:21:34 PM PDT 24
Finished Mar 21 01:21:39 PM PDT 24
Peak memory 208776 kb
Host smart-3772cd2e-111c-45a4-9590-1948d6d4466d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744128999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2744128999
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2638090310
Short name T761
Test name
Test status
Simulation time 1017282114 ps
CPU time 18.16 seconds
Started Mar 21 01:21:39 PM PDT 24
Finished Mar 21 01:21:59 PM PDT 24
Peak memory 203292 kb
Host smart-9f3136e1-fe2d-4214-8644-c04b8e6bd11b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638090310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2638090310
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3387688740
Short name T115
Test name
Test status
Simulation time 3005454097 ps
CPU time 5 seconds
Started Mar 21 01:21:33 PM PDT 24
Finished Mar 21 01:21:38 PM PDT 24
Peak memory 203468 kb
Host smart-b447c69b-acdc-45c6-8517-348cc6cae359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387688740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3387688740
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3581694015
Short name T345
Test name
Test status
Simulation time 16555773027 ps
CPU time 33.76 seconds
Started Mar 21 01:21:36 PM PDT 24
Finished Mar 21 01:22:10 PM PDT 24
Peak memory 203304 kb
Host smart-bd61a49a-8d5b-42b7-be61-bd9c0e25464b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581694015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3581694015
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1154269071
Short name T536
Test name
Test status
Simulation time 13566347870 ps
CPU time 6.31 seconds
Started Mar 21 01:21:34 PM PDT 24
Finished Mar 21 01:21:40 PM PDT 24
Peak memory 219636 kb
Host smart-39a7fb6d-e18b-4e29-a395-74ccb87f66dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154269071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1154269071
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2813407066
Short name T396
Test name
Test status
Simulation time 16243020 ps
CPU time 0.66 seconds
Started Mar 21 01:17:54 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 203032 kb
Host smart-d64efce4-8741-4c1e-9056-a72d9a166e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813407066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2813407066
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.4178511629
Short name T804
Test name
Test status
Simulation time 150121252 ps
CPU time 1.33 seconds
Started Mar 21 01:17:43 PM PDT 24
Finished Mar 21 01:17:44 PM PDT 24
Peak memory 219592 kb
Host smart-12e5cd9f-96cb-44b0-8126-ae8878bc3fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178511629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.4178511629
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1343671842
Short name T1007
Test name
Test status
Simulation time 1156026484 ps
CPU time 16.25 seconds
Started Mar 21 01:17:41 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 266308 kb
Host smart-ce1e8ecf-f9e8-4b3e-b7e4-cc0581f83200
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343671842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1343671842
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3078832981
Short name T221
Test name
Test status
Simulation time 6157722384 ps
CPU time 74.57 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:18:55 PM PDT 24
Peak memory 616852 kb
Host smart-81714981-20ce-4632-87ff-e97c6ad9fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078832981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3078832981
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.666886463
Short name T60
Test name
Test status
Simulation time 3366555502 ps
CPU time 40.91 seconds
Started Mar 21 01:17:39 PM PDT 24
Finished Mar 21 01:18:20 PM PDT 24
Peak memory 511852 kb
Host smart-654ac453-b313-4564-b58f-3de50121523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666886463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.666886463
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3172377919
Short name T841
Test name
Test status
Simulation time 112359325 ps
CPU time 0.85 seconds
Started Mar 21 01:17:46 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 202616 kb
Host smart-b5a34fd9-15d4-4660-9958-cdf77f48252a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172377919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3172377919
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3977361785
Short name T884
Test name
Test status
Simulation time 665589543 ps
CPU time 3.33 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:44 PM PDT 24
Peak memory 203236 kb
Host smart-6f605ad2-a664-4be6-8748-a92e0b7bc42f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977361785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3977361785
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_override.1927139964
Short name T750
Test name
Test status
Simulation time 18819668 ps
CPU time 0.7 seconds
Started Mar 21 01:17:37 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 202460 kb
Host smart-26295c9a-5510-4b9a-970d-11875ac81bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927139964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1927139964
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.127589518
Short name T745
Test name
Test status
Simulation time 6089940043 ps
CPU time 92.55 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:19:13 PM PDT 24
Peak memory 233320 kb
Host smart-010b22cf-ec0e-4a4b-b29e-ecb984c05ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127589518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.127589518
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3340497406
Short name T411
Test name
Test status
Simulation time 7949183294 ps
CPU time 69.29 seconds
Started Mar 21 01:17:48 PM PDT 24
Finished Mar 21 01:18:57 PM PDT 24
Peak memory 276780 kb
Host smart-d44d841d-1065-4ac5-a54e-b26547da0bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340497406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3340497406
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2874891711
Short name T262
Test name
Test status
Simulation time 4901145666 ps
CPU time 3.55 seconds
Started Mar 21 01:17:41 PM PDT 24
Finished Mar 21 01:17:45 PM PDT 24
Peak memory 203380 kb
Host smart-90b6ce96-aae9-4aae-895c-68ba849cc36f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874891711 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2874891711
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1221219779
Short name T632
Test name
Test status
Simulation time 10138864674 ps
CPU time 80.63 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:19:01 PM PDT 24
Peak memory 630576 kb
Host smart-35effb80-e84a-4314-8a2d-7fc48ce6b00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221219779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1221219779
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.54765673
Short name T389
Test name
Test status
Simulation time 10135900173 ps
CPU time 12.69 seconds
Started Mar 21 01:17:40 PM PDT 24
Finished Mar 21 01:17:53 PM PDT 24
Peak memory 314464 kb
Host smart-f1de253a-bac4-434a-b3db-25c6b0078f58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54765673 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_fifo_reset_tx.54765673
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1479611584
Short name T205
Test name
Test status
Simulation time 656424094 ps
CPU time 3.34 seconds
Started Mar 21 01:17:44 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 203316 kb
Host smart-76977827-6dbc-4f30-a20b-654deca98f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479611584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1479611584
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.745031657
Short name T334
Test name
Test status
Simulation time 2089027932 ps
CPU time 4.95 seconds
Started Mar 21 01:17:41 PM PDT 24
Finished Mar 21 01:17:46 PM PDT 24
Peak memory 206196 kb
Host smart-9a240436-c1dc-4f70-a232-7d1944b0ed58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745031657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.745031657
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.324961151
Short name T349
Test name
Test status
Simulation time 3448161549 ps
CPU time 33.42 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203320 kb
Host smart-96f4d4ba-da94-4960-9440-c8bb2660064e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324961151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.324961151
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.196254956
Short name T558
Test name
Test status
Simulation time 1547071168 ps
CPU time 25.05 seconds
Started Mar 21 01:17:38 PM PDT 24
Finished Mar 21 01:18:03 PM PDT 24
Peak memory 226344 kb
Host smart-60d0540a-8711-44d6-8d99-a274f2b3b559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196254956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.196254956
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1710469457
Short name T282
Test name
Test status
Simulation time 21823518521 ps
CPU time 468.65 seconds
Started Mar 21 01:17:45 PM PDT 24
Finished Mar 21 01:25:33 PM PDT 24
Peak memory 2901136 kb
Host smart-763c9054-1ffc-49a7-94e6-17b80ceeacf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710469457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1710469457
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1602829166
Short name T793
Test name
Test status
Simulation time 4513980188 ps
CPU time 5.86 seconds
Started Mar 21 01:17:42 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 203412 kb
Host smart-1d078c5a-6bc6-4a25-88c4-a97dd8614393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602829166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1602829166
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2628695638
Short name T356
Test name
Test status
Simulation time 16582134 ps
CPU time 0.59 seconds
Started Mar 21 01:18:02 PM PDT 24
Finished Mar 21 01:18:04 PM PDT 24
Peak memory 202016 kb
Host smart-667feb31-84b9-4e63-94dc-69177b8e0280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628695638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2628695638
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2841374174
Short name T1074
Test name
Test status
Simulation time 402959159 ps
CPU time 9.34 seconds
Started Mar 21 01:17:45 PM PDT 24
Finished Mar 21 01:17:54 PM PDT 24
Peak memory 291172 kb
Host smart-d64d7ea6-2597-4006-bbd8-affbdbfb8ac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841374174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2841374174
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1024713903
Short name T846
Test name
Test status
Simulation time 1279484207 ps
CPU time 81.37 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:19:12 PM PDT 24
Peak memory 479104 kb
Host smart-9e039a4f-c23e-4f1f-962f-a02920356c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024713903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1024713903
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2618929289
Short name T928
Test name
Test status
Simulation time 3458790473 ps
CPU time 48.07 seconds
Started Mar 21 01:17:50 PM PDT 24
Finished Mar 21 01:18:38 PM PDT 24
Peak memory 616752 kb
Host smart-b4ba3762-4963-404f-8dca-b41290163034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618929289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2618929289
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3713135951
Short name T695
Test name
Test status
Simulation time 97537110 ps
CPU time 0.91 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:17:50 PM PDT 24
Peak memory 203044 kb
Host smart-73f853bc-21e2-4fa1-8d30-e223bba562e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713135951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3713135951
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2791696013
Short name T998
Test name
Test status
Simulation time 156648471 ps
CPU time 4.61 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:17:54 PM PDT 24
Peak memory 229656 kb
Host smart-0e8bd3ab-c69a-4805-9c64-466c10608acc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791696013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2791696013
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.154909917
Short name T224
Test name
Test status
Simulation time 16326832430 ps
CPU time 121.07 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:19:50 PM PDT 24
Peak memory 1179760 kb
Host smart-bf3f73c8-9786-4a77-8f62-f0b38a8649b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154909917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.154909917
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_override.2873611051
Short name T17
Test name
Test status
Simulation time 15693995 ps
CPU time 0.64 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:17:50 PM PDT 24
Peak memory 202540 kb
Host smart-3c7dc298-c373-4eeb-91f7-5c2381dea96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873611051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2873611051
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3761207782
Short name T36
Test name
Test status
Simulation time 5130497463 ps
CPU time 1300.74 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:39:34 PM PDT 24
Peak memory 668160 kb
Host smart-d41319b0-efaf-4bbd-83cc-60f6980a5def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761207782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3761207782
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1104828351
Short name T247
Test name
Test status
Simulation time 2502028640 ps
CPU time 96.39 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:19:27 PM PDT 24
Peak memory 273080 kb
Host smart-02539844-9c19-4523-bab9-f37e3f7abb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104828351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1104828351
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4087981624
Short name T563
Test name
Test status
Simulation time 1368331798 ps
CPU time 3.01 seconds
Started Mar 21 01:17:45 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 203444 kb
Host smart-463728c7-b90a-4e2f-a801-746465d584c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087981624 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4087981624
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3471607726
Short name T956
Test name
Test status
Simulation time 10229467636 ps
CPU time 13.95 seconds
Started Mar 21 01:17:47 PM PDT 24
Finished Mar 21 01:18:01 PM PDT 24
Peak memory 291908 kb
Host smart-1652b26d-0517-4fac-b27a-42f9754aef45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471607726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3471607726
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3940624914
Short name T1018
Test name
Test status
Simulation time 10243293485 ps
CPU time 15.23 seconds
Started Mar 21 01:18:05 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 312032 kb
Host smart-e0343c87-79ff-40cf-a3f0-c6da2ddb1031
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940624914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3940624914
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.670086282
Short name T587
Test name
Test status
Simulation time 1876711744 ps
CPU time 2.47 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:18:00 PM PDT 24
Peak memory 203356 kb
Host smart-2ebbf3f9-b9a5-4775-a6ef-3c2c9d5070c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670086282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.670086282
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.643572374
Short name T416
Test name
Test status
Simulation time 1188020004 ps
CPU time 5.62 seconds
Started Mar 21 01:17:52 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 215356 kb
Host smart-135882dc-23a7-4b30-93c3-85869f9a7c6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643572374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.643572374
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.4034084511
Short name T392
Test name
Test status
Simulation time 5923001551 ps
CPU time 6.9 seconds
Started Mar 21 01:17:46 PM PDT 24
Finished Mar 21 01:17:54 PM PDT 24
Peak memory 203372 kb
Host smart-bd4b66e8-d85c-4414-a4d8-2b48b33d5ee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034084511 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.4034084511
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2897506237
Short name T175
Test name
Test status
Simulation time 1015512769 ps
CPU time 13.8 seconds
Started Mar 21 01:17:58 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203308 kb
Host smart-d602f3ab-66a6-4901-b046-697498a87c5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897506237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2897506237
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4170383832
Short name T357
Test name
Test status
Simulation time 2435810674 ps
CPU time 62.2 seconds
Started Mar 21 01:17:50 PM PDT 24
Finished Mar 21 01:18:52 PM PDT 24
Peak memory 206084 kb
Host smart-084caba1-5e55-48e6-a544-584157624015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170383832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4170383832
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.4014769527
Short name T434
Test name
Test status
Simulation time 15203019672 ps
CPU time 31.78 seconds
Started Mar 21 01:18:02 PM PDT 24
Finished Mar 21 01:18:35 PM PDT 24
Peak memory 203320 kb
Host smart-d7af6714-0b75-43e1-90ed-1c78133c4cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014769527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.4014769527
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1716077371
Short name T1079
Test name
Test status
Simulation time 6638760675 ps
CPU time 7.06 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:17:58 PM PDT 24
Peak memory 209452 kb
Host smart-ddd2d14f-f86a-47a4-ac53-694894907798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716077371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1716077371
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1192339493
Short name T725
Test name
Test status
Simulation time 33017087 ps
CPU time 0.64 seconds
Started Mar 21 01:18:00 PM PDT 24
Finished Mar 21 01:18:00 PM PDT 24
Peak memory 203104 kb
Host smart-b487bff8-7e19-4258-9f92-65a5d9d90528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192339493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1192339493
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4236453440
Short name T201
Test name
Test status
Simulation time 59845891 ps
CPU time 1.18 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 211576 kb
Host smart-de256105-2d97-405e-b34e-f779920d6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236453440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4236453440
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.630602230
Short name T473
Test name
Test status
Simulation time 293963346 ps
CPU time 6.28 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 263120 kb
Host smart-eafc6ded-1f10-4107-b53a-0f092c96dfd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630602230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.630602230
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3221966173
Short name T638
Test name
Test status
Simulation time 7346785023 ps
CPU time 149.29 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 661764 kb
Host smart-410585b7-8f3b-4d85-8908-85b6ef01c72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221966173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3221966173
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.722393184
Short name T861
Test name
Test status
Simulation time 4287053371 ps
CPU time 62.98 seconds
Started Mar 21 01:17:47 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 716564 kb
Host smart-adf7662b-b279-4b35-aed7-91ba036d8feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722393184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.722393184
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.580274895
Short name T440
Test name
Test status
Simulation time 231940612 ps
CPU time 0.94 seconds
Started Mar 21 01:17:52 PM PDT 24
Finished Mar 21 01:17:53 PM PDT 24
Peak memory 203296 kb
Host smart-4664f12d-6e19-4262-a6ad-bdfef89b6aad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580274895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.580274895
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.567836095
Short name T618
Test name
Test status
Simulation time 131763518 ps
CPU time 2.7 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:17:53 PM PDT 24
Peak memory 203328 kb
Host smart-78888cec-ce54-4cf0-b5ad-64415612d6cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567836095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.567836095
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1037883103
Short name T217
Test name
Test status
Simulation time 11502182388 ps
CPU time 182.5 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 833108 kb
Host smart-ee1ad7be-a0af-47c3-9069-243b49ac2847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037883103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1037883103
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_override.690822879
Short name T1020
Test name
Test status
Simulation time 40337909 ps
CPU time 0.69 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:17:54 PM PDT 24
Peak memory 202356 kb
Host smart-86bf9508-aba9-48c3-a7a9-0739fa498ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690822879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.690822879
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.868391208
Short name T602
Test name
Test status
Simulation time 12408745562 ps
CPU time 342.36 seconds
Started Mar 21 01:17:48 PM PDT 24
Finished Mar 21 01:23:31 PM PDT 24
Peak memory 403764 kb
Host smart-070c392d-6706-4b0d-8a89-98d95fd389b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868391208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.868391208
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2134328454
Short name T73
Test name
Test status
Simulation time 4231881168 ps
CPU time 46.9 seconds
Started Mar 21 01:17:46 PM PDT 24
Finished Mar 21 01:18:34 PM PDT 24
Peak memory 313084 kb
Host smart-f757cc95-fd00-4646-bc9c-462f7a27aa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134328454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2134328454
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.712906690
Short name T108
Test name
Test status
Simulation time 559743900 ps
CPU time 3.32 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:17:53 PM PDT 24
Peak memory 203280 kb
Host smart-f796af64-4579-419f-9aad-ed3150bce2be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712906690 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.712906690
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3180685969
Short name T1058
Test name
Test status
Simulation time 10111035797 ps
CPU time 72.36 seconds
Started Mar 21 01:17:49 PM PDT 24
Finished Mar 21 01:19:02 PM PDT 24
Peak memory 566216 kb
Host smart-d2ed228b-ab6b-4c76-a25c-a3b94b379111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180685969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3180685969
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1226772920
Short name T375
Test name
Test status
Simulation time 10437231636 ps
CPU time 10.08 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 285620 kb
Host smart-496b3778-4d93-4b8a-ace6-2e9eef8122fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226772920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1226772920
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2895494615
Short name T581
Test name
Test status
Simulation time 1606551037 ps
CPU time 2.37 seconds
Started Mar 21 01:17:51 PM PDT 24
Finished Mar 21 01:17:53 PM PDT 24
Peak memory 203728 kb
Host smart-b1dab25b-d637-4446-afff-f628bcb7206d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895494615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2895494615
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1957141037
Short name T930
Test name
Test status
Simulation time 2393896173 ps
CPU time 5.85 seconds
Started Mar 21 01:17:54 PM PDT 24
Finished Mar 21 01:18:00 PM PDT 24
Peak memory 203380 kb
Host smart-93e2cc51-3495-471e-a0d9-fc06204a31d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957141037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1957141037
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3924691183
Short name T111
Test name
Test status
Simulation time 885184068 ps
CPU time 31.25 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:35 PM PDT 24
Peak memory 203312 kb
Host smart-337a3daf-76ae-45ff-97a4-a2c38e73c1a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924691183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3924691183
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.560851294
Short name T834
Test name
Test status
Simulation time 2854617428 ps
CPU time 11.78 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:16 PM PDT 24
Peak memory 205808 kb
Host smart-f329ac52-fcf5-46b1-b7db-df13443958b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560851294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.560851294
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1725727853
Short name T683
Test name
Test status
Simulation time 19137695520 ps
CPU time 39.54 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:43 PM PDT 24
Peak memory 203324 kb
Host smart-d8451cbe-7a20-4fc1-95f2-eed1aed595c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725727853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1725727853
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1703911154
Short name T1024
Test name
Test status
Simulation time 17260999871 ps
CPU time 3156.2 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 02:10:30 PM PDT 24
Peak memory 4121092 kb
Host smart-40617273-0670-4116-96d5-f46da74c6fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703911154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1703911154
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3053707447
Short name T689
Test name
Test status
Simulation time 5201111001 ps
CPU time 6.53 seconds
Started Mar 21 01:17:55 PM PDT 24
Finished Mar 21 01:18:02 PM PDT 24
Peak memory 211628 kb
Host smart-ed669a5e-0936-4473-9b51-b200af832399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053707447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3053707447
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2352868848
Short name T505
Test name
Test status
Simulation time 70726827 ps
CPU time 0.64 seconds
Started Mar 21 01:18:00 PM PDT 24
Finished Mar 21 01:18:03 PM PDT 24
Peak memory 203104 kb
Host smart-d14260d1-0f52-4b3a-88f7-39f3e1bd3bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352868848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2352868848
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3119646987
Short name T555
Test name
Test status
Simulation time 72363487 ps
CPU time 1.82 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:17:55 PM PDT 24
Peak memory 211512 kb
Host smart-ebfbb6d7-e617-4500-9c93-e278c75ad6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119646987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3119646987
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2050933922
Short name T561
Test name
Test status
Simulation time 1080877099 ps
CPU time 6.8 seconds
Started Mar 21 01:17:54 PM PDT 24
Finished Mar 21 01:18:01 PM PDT 24
Peak memory 257084 kb
Host smart-b639f2fd-2e6c-4127-8f03-2d7b027eab37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050933922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2050933922
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.4006895448
Short name T794
Test name
Test status
Simulation time 3478734354 ps
CPU time 50.41 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:50 PM PDT 24
Peak memory 596076 kb
Host smart-582b7f2d-3c17-49a1-8535-ddc3367a07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006895448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.4006895448
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1390432493
Short name T1048
Test name
Test status
Simulation time 6341631768 ps
CPU time 81.82 seconds
Started Mar 21 01:17:52 PM PDT 24
Finished Mar 21 01:19:14 PM PDT 24
Peak memory 789152 kb
Host smart-bcbebce3-ad7b-49e6-8c71-f745331c6352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390432493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1390432493
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3217272442
Short name T623
Test name
Test status
Simulation time 976770517 ps
CPU time 0.9 seconds
Started Mar 21 01:17:58 PM PDT 24
Finished Mar 21 01:17:59 PM PDT 24
Peak memory 203108 kb
Host smart-3708ed7a-f239-49e3-90fb-bf96deee4327
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217272442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3217272442
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3841171683
Short name T390
Test name
Test status
Simulation time 494199435 ps
CPU time 4.53 seconds
Started Mar 21 01:17:57 PM PDT 24
Finished Mar 21 01:18:02 PM PDT 24
Peak memory 234696 kb
Host smart-6d6248fa-f283-4429-bf1e-dc597c7c43ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841171683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3841171683
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_override.4018066748
Short name T1085
Test name
Test status
Simulation time 21777810 ps
CPU time 0.7 seconds
Started Mar 21 01:18:01 PM PDT 24
Finished Mar 21 01:18:04 PM PDT 24
Peak memory 202532 kb
Host smart-fd498618-7d89-41cc-bfd7-12c43d3d3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018066748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4018066748
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.155993679
Short name T543
Test name
Test status
Simulation time 2732120065 ps
CPU time 66.07 seconds
Started Mar 21 01:17:58 PM PDT 24
Finished Mar 21 01:19:05 PM PDT 24
Peak memory 219712 kb
Host smart-b92cf5e7-a8dd-464c-8a31-53a01cc38453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155993679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.155993679
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.888221487
Short name T335
Test name
Test status
Simulation time 4380346448 ps
CPU time 109.89 seconds
Started Mar 21 01:17:56 PM PDT 24
Finished Mar 21 01:19:46 PM PDT 24
Peak memory 405300 kb
Host smart-8968d598-09f0-4496-9cb4-20bb02ad03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888221487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.888221487
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.4043764873
Short name T228
Test name
Test status
Simulation time 27711219694 ps
CPU time 1338.91 seconds
Started Mar 21 01:18:14 PM PDT 24
Finished Mar 21 01:40:33 PM PDT 24
Peak memory 1285640 kb
Host smart-be85e570-5c63-450b-876d-ddd524177b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043764873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.4043764873
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3088514185
Short name T288
Test name
Test status
Simulation time 16361882545 ps
CPU time 4.08 seconds
Started Mar 21 01:18:06 PM PDT 24
Finished Mar 21 01:18:11 PM PDT 24
Peak memory 211612 kb
Host smart-4b7a4bdd-ef29-45b4-a54a-2df1c7dd1246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088514185 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3088514185
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1525996594
Short name T773
Test name
Test status
Simulation time 10073177874 ps
CPU time 14.76 seconds
Started Mar 21 01:18:03 PM PDT 24
Finished Mar 21 01:18:18 PM PDT 24
Peak memory 298192 kb
Host smart-30a1fa5a-a52b-4183-9e9e-6860b12ad799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525996594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1525996594
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2439405643
Short name T443
Test name
Test status
Simulation time 10121076307 ps
CPU time 102.44 seconds
Started Mar 21 01:18:05 PM PDT 24
Finished Mar 21 01:19:48 PM PDT 24
Peak memory 753992 kb
Host smart-0b8399cc-3d1f-4722-ad67-31c1f121fdb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439405643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2439405643
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2147233991
Short name T707
Test name
Test status
Simulation time 884814937 ps
CPU time 2.69 seconds
Started Mar 21 01:17:56 PM PDT 24
Finished Mar 21 01:17:59 PM PDT 24
Peak memory 203472 kb
Host smart-c0845b44-05df-4a3d-b7d8-c4423aa0bf45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147233991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2147233991
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.8120112
Short name T1076
Test name
Test status
Simulation time 980321732 ps
CPU time 4.93 seconds
Started Mar 21 01:17:54 PM PDT 24
Finished Mar 21 01:17:59 PM PDT 24
Peak memory 204660 kb
Host smart-e2428350-9645-4888-bd9b-936c1461261e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8120112 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_intr_smoke.8120112
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1626043034
Short name T875
Test name
Test status
Simulation time 2979638823 ps
CPU time 8.62 seconds
Started Mar 21 01:18:07 PM PDT 24
Finished Mar 21 01:18:16 PM PDT 24
Peak memory 203372 kb
Host smart-2e0fc86e-d476-424f-984b-2203d38a0d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626043034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1626043034
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1243118782
Short name T488
Test name
Test status
Simulation time 763266480 ps
CPU time 34.26 seconds
Started Mar 21 01:17:53 PM PDT 24
Finished Mar 21 01:18:28 PM PDT 24
Peak memory 203332 kb
Host smart-c1ebc7cf-f8db-4561-bc46-4f619d412f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243118782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1243118782
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1467552199
Short name T373
Test name
Test status
Simulation time 24660658743 ps
CPU time 6.89 seconds
Started Mar 21 01:18:00 PM PDT 24
Finished Mar 21 01:18:08 PM PDT 24
Peak memory 203408 kb
Host smart-e0f7b2ff-1482-488f-93b5-dfe22795ae4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467552199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1467552199
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1466563357
Short name T502
Test name
Test status
Simulation time 43764583503 ps
CPU time 219.28 seconds
Started Mar 21 01:17:54 PM PDT 24
Finished Mar 21 01:21:33 PM PDT 24
Peak memory 1888068 kb
Host smart-4e3523a2-fa4a-49f9-a5c1-d98cb078f763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466563357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1466563357
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3341577989
Short name T772
Test name
Test status
Simulation time 2755619668 ps
CPU time 6.94 seconds
Started Mar 21 01:18:10 PM PDT 24
Finished Mar 21 01:18:17 PM PDT 24
Peak memory 219648 kb
Host smart-031516c1-99d7-4960-ae64-83d03d38895a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341577989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3341577989
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2511448751
Short name T369
Test name
Test status
Simulation time 38429736 ps
CPU time 0.61 seconds
Started Mar 21 01:18:00 PM PDT 24
Finished Mar 21 01:18:00 PM PDT 24
Peak memory 202088 kb
Host smart-9fea10f3-5958-4de3-b983-e64c9910e379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511448751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2511448751
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.4051556123
Short name T1042
Test name
Test status
Simulation time 40775963 ps
CPU time 1.16 seconds
Started Mar 21 01:17:56 PM PDT 24
Finished Mar 21 01:17:57 PM PDT 24
Peak memory 203348 kb
Host smart-2512402e-bbd4-4cd7-b131-9395ebba11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051556123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.4051556123
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3886155009
Short name T585
Test name
Test status
Simulation time 307631747 ps
CPU time 14.92 seconds
Started Mar 21 01:17:57 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 246064 kb
Host smart-63c8a0e8-5165-4b2b-852a-4d26d6840cdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886155009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3886155009
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3502052167
Short name T1054
Test name
Test status
Simulation time 5221140992 ps
CPU time 47.66 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:47 PM PDT 24
Peak memory 567852 kb
Host smart-83179576-c7be-436a-b0a8-9d59b887605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502052167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3502052167
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.4030280518
Short name T722
Test name
Test status
Simulation time 1391881906 ps
CPU time 0.89 seconds
Started Mar 21 01:17:55 PM PDT 24
Finished Mar 21 01:17:56 PM PDT 24
Peak memory 203016 kb
Host smart-3236ccc7-ad60-47c9-beb0-852a440585e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030280518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.4030280518
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2100207621
Short name T674
Test name
Test status
Simulation time 433227519 ps
CPU time 4.4 seconds
Started Mar 21 01:18:08 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 226244 kb
Host smart-5f37c376-1234-4b87-9d12-c6f2f0458893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100207621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2100207621
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2256604185
Short name T490
Test name
Test status
Simulation time 10585372022 ps
CPU time 69.24 seconds
Started Mar 21 01:18:09 PM PDT 24
Finished Mar 21 01:19:19 PM PDT 24
Peak memory 835644 kb
Host smart-d8c5338c-ec75-4912-9e51-467db3a1075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256604185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2256604185
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.4185674649
Short name T210
Test name
Test status
Simulation time 2225166386 ps
CPU time 33.57 seconds
Started Mar 21 01:17:57 PM PDT 24
Finished Mar 21 01:18:31 PM PDT 24
Peak memory 311128 kb
Host smart-0272780f-3a6f-4441-a66d-5b5c481b75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185674649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4185674649
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.211717826
Short name T972
Test name
Test status
Simulation time 792651336 ps
CPU time 3.93 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:03 PM PDT 24
Peak memory 203312 kb
Host smart-fc2e226c-0e5d-42ef-91fb-4efd930198da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211717826 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.211717826
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1561180784
Short name T368
Test name
Test status
Simulation time 10476039931 ps
CPU time 12.07 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 279864 kb
Host smart-eec83361-095a-444d-b066-56336c026f3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561180784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1561180784
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1564717555
Short name T374
Test name
Test status
Simulation time 10310451714 ps
CPU time 19.98 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:20 PM PDT 24
Peak memory 395840 kb
Host smart-8f113a05-5223-4cb5-a104-eda09b398f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564717555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1564717555
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.563281667
Short name T816
Test name
Test status
Simulation time 613477734 ps
CPU time 2.18 seconds
Started Mar 21 01:18:13 PM PDT 24
Finished Mar 21 01:18:15 PM PDT 24
Peak memory 203320 kb
Host smart-8975cb93-07bb-4841-9aaf-0a88afe0df63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563281667 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.563281667
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.4067699790
Short name T651
Test name
Test status
Simulation time 1364663538 ps
CPU time 7.71 seconds
Started Mar 21 01:17:57 PM PDT 24
Finished Mar 21 01:18:05 PM PDT 24
Peak memory 219368 kb
Host smart-41182f9d-aa36-445b-956a-ebfd4b285b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067699790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.4067699790
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.4288749072
Short name T746
Test name
Test status
Simulation time 6685719631 ps
CPU time 5.18 seconds
Started Mar 21 01:18:16 PM PDT 24
Finished Mar 21 01:18:21 PM PDT 24
Peak memory 203328 kb
Host smart-101e947a-b16b-4679-bf2c-3c414069cf6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288749072 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.4288749072
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.133283603
Short name T825
Test name
Test status
Simulation time 904677920 ps
CPU time 16.37 seconds
Started Mar 21 01:17:56 PM PDT 24
Finished Mar 21 01:18:13 PM PDT 24
Peak memory 203316 kb
Host smart-64db039f-f633-4473-9a83-87fffaea72be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133283603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.133283603
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.145560826
Short name T656
Test name
Test status
Simulation time 6676295300 ps
CPU time 28.13 seconds
Started Mar 21 01:18:13 PM PDT 24
Finished Mar 21 01:18:41 PM PDT 24
Peak memory 231488 kb
Host smart-883004a3-b316-43ab-adbe-0c74b7d1c150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145560826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.145560826
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1664070571
Short name T383
Test name
Test status
Simulation time 5222341607 ps
CPU time 7.03 seconds
Started Mar 21 01:17:59 PM PDT 24
Finished Mar 21 01:18:06 PM PDT 24
Peak memory 203372 kb
Host smart-634d5589-658e-497d-b531-8d72e41fccac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664070571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1664070571
Directory /workspace/9.i2c_target_timeout/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%