Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.59	92.59	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	92.59	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	4	23	85.19

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	4	23	85.19	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

97950

1

T3

134

T6

87

T15

9

ack

6558

1

T1

12

T3

10

T6

1

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	390	1			T3	2		T47	1		T70	1
high	21832	1			T1	1		T3	32		T6	18
med	39297	1			T1	2		T3	50		T6	30
sml	42577	1			T1	9		T3	58		T6	40
all_zero	412	1			T3	2		T69	1		T70	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52231

1

T1

7

T3

73

T6

41

auto[1]

52277

1

T1

5

T3

71

T6

47

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70967

1

T1

12

T3

93

T6

58

auto[1]

33541

1

T3

51

T6

30

T15

5

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101211

1

T1

6

T3

144

T6

88

auto[1]

3297

1

T1

6

T14

7

T15

1

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100078

1

T1

6

T3

134

T6

87

auto[1]

4430

1

T1

6

T3

10

T6

1

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100457

1

T1

6

T3

134

T6

87

auto[1]

4051

1

T1

6

T3

10

T6

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52231

1

T1

7

T3

73

T6

41

auto[1]

52277

1

T1

5

T3

71

T6

47

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70967

1

T1

12

T3

93

T6

58

auto[1]

33541

1

T3

51

T6

30

T15

5

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101211

1

T1

6

T3

144

T6

88

auto[1]

3297

1

T1

6

T14

7

T15

1

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100078

1

T1

6

T3

134

T6

87

auto[1]

4430

1

T1

6

T3

10

T6

1

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100457

1

T1

6

T3

134

T6

87

auto[1]

4051

1

T1

6

T3

10

T6

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	4	23	85.19	2
Automatically Generated Cross Bins	15	2	13	86.67	2
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T205

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T206

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

131

1

T78

1

T79

1

T207

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

55

1

T207

1

T208

1

T197

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

45

1

T19

1

T57

1

T87

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

249

1

T19

2

T78

4

T79

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

111

1

T47

1

T86

2

T207

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

134

1

T19

1

T20

1

T86

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

231

1

T19

1

T78

2

T86

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

125

1

T57

1

T85

1

T86

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

101

1

T47

1

T78

2

T86

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T81

1

T74

1

T209

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T210

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	31494	1			T3	37		T6	27		T15	3
write_address_byte	4430	1			T1	6		T3	10		T6	1
read_with_ack	1004	1			T47	5		T28	8		T19	5
read_with_nack	2293	1			T1	6		T14	7		T15	1
stop_byte	4051	1			T1	6		T3	10		T6	1
write_address_byte_nak	1954	1			T47	4		T19	6		T16	1
data_byte_nack	97950	1			T3	134		T6	87		T15	9
stop_byte_nack	2559	1			T3	10		T6	1		T15	1
nakok_byte_nack	48986	1			T3	66		T6	47		T15	3
nakok_addr_byte_nack	995	1			T47	1		T19	3		T16	1