Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26421804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6775298

1

T1

8406

T2

77

T3

1044

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30327786	1			T1	17497		T2	243		T3	2004
values[0x0]	1435907	1			T1	61		T2	9		T3	103
values[0x1]	1433409	1			T1	55		T2	8		T3	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19179280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14017822

1

T1

10349

T2

123

T3

1312

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	109919	1			T1	62		T2	1		T3	2
valid_sources[0x01]	111879	1			T1	61		T2	1		T3	9
valid_sources[0x02]	104237	1			T1	58		T3	12		T4	88
valid_sources[0x03]	114763	1			T1	64		T3	21		T4	80
valid_sources[0x04]	103504	1			T1	67		T3	11		T4	54
valid_sources[0x05]	105573	1			T1	77		T3	7		T4	71
valid_sources[0x06]	112986	1			T1	65		T3	13		T4	76
valid_sources[0x07]	110463	1			T1	49		T3	4		T4	74
valid_sources[0x08]	117685	1			T1	74		T3	14		T4	63
valid_sources[0x09]	107809	1			T1	83		T2	4		T3	8
valid_sources[0x0a]	112445	1			T1	50		T2	1		T4	77
valid_sources[0x0b]	114277	1			T1	73		T2	2		T3	1
valid_sources[0x0c]	112082	1			T1	67		T2	1		T3	2
valid_sources[0x0d]	115882	1			T1	76		T2	1		T3	3
valid_sources[0x0e]	108570	1			T1	76		T3	1		T4	78
valid_sources[0x0f]	278879	1			T1	65		T3	11		T4	76
valid_sources[0x10]	105105	1			T1	68		T3	4		T4	78
valid_sources[0x11]	115702	1			T1	81		T3	7		T4	83
valid_sources[0x12]	576538	1			T1	48		T2	1		T3	5
valid_sources[0x13]	119088	1			T1	66		T3	5		T4	103
valid_sources[0x14]	127225	1			T1	75		T2	3		T3	10
valid_sources[0x15]	116707	1			T1	52		T3	4		T4	80
valid_sources[0x16]	107309	1			T1	78		T2	4		T3	19
valid_sources[0x17]	143724	1			T1	61		T2	1		T3	1
valid_sources[0x18]	138728	1			T1	59		T3	6		T4	55
valid_sources[0x19]	110134	1			T1	70		T4	73		T9	1
valid_sources[0x1a]	105072	1			T1	75		T3	1		T4	77
valid_sources[0x1b]	99767	1			T1	55		T2	1		T3	8
valid_sources[0x1c]	116708	1			T1	77		T2	2		T3	6
valid_sources[0x1d]	104503	1			T1	59		T2	1		T3	10
valid_sources[0x1e]	111958	1			T1	70		T2	1		T3	1
valid_sources[0x1f]	399513	1			T1	74		T3	6		T4	78
valid_sources[0x20]	105138	1			T1	57		T2	1		T3	8
valid_sources[0x21]	101907	1			T1	77		T2	1		T4	50
valid_sources[0x22]	116728	1			T1	62		T2	5		T3	12
valid_sources[0x23]	111935	1			T1	71		T3	7		T4	104
valid_sources[0x24]	118791	1			T1	93		T3	8		T4	95
valid_sources[0x25]	111804	1			T1	88		T3	14		T4	63
valid_sources[0x26]	103604	1			T1	75		T2	4		T3	6
valid_sources[0x27]	122401	1			T1	56		T3	21		T4	69
valid_sources[0x28]	121713	1			T1	76		T3	23		T4	54
valid_sources[0x29]	101876	1			T1	68		T2	1		T3	3
valid_sources[0x2a]	122602	1			T1	63		T3	11		T4	53
valid_sources[0x2b]	115970	1			T1	77		T2	1		T3	1
valid_sources[0x2c]	129155	1			T1	88		T2	1		T3	11
valid_sources[0x2d]	109674	1			T1	87		T2	1		T3	2
valid_sources[0x2e]	113637	1			T1	68		T2	3		T3	27
valid_sources[0x2f]	220627	1			T1	62		T4	73		T7	2
valid_sources[0x30]	115929	1			T1	82		T3	1		T4	63
valid_sources[0x31]	153381	1			T1	68		T3	6		T4	85
valid_sources[0x32]	124894	1			T1	41		T3	7		T4	73
valid_sources[0x33]	103117	1			T1	62		T2	9		T3	6
valid_sources[0x34]	128021	1			T1	65		T3	7		T4	55
valid_sources[0x35]	111552	1			T1	63		T2	1		T3	5
valid_sources[0x36]	102067	1			T1	61		T2	1		T3	4
valid_sources[0x37]	142781	1			T1	80		T2	2		T3	18
valid_sources[0x38]	402287	1			T1	51		T2	1		T3	13
valid_sources[0x39]	136762	1			T1	57		T3	1		T4	57
valid_sources[0x3a]	109700	1			T1	75		T2	1		T3	12
valid_sources[0x3b]	118049	1			T1	59		T2	1		T3	1
valid_sources[0x3c]	108867	1			T1	57		T2	4		T3	26
valid_sources[0x3d]	100185	1			T1	85		T2	1		T3	10
valid_sources[0x3e]	118283	1			T1	59		T2	1		T3	32
valid_sources[0x3f]	110092	1			T1	59		T2	1		T3	2
valid_sources[0x40]	109197	1			T1	64		T3	12		T4	77
valid_sources[0x41]	109756	1			T1	86		T2	2		T3	7
valid_sources[0x42]	108751	1			T1	53		T3	4		T4	89
valid_sources[0x43]	117845	1			T1	57		T2	1		T3	6
valid_sources[0x44]	106142	1			T1	69		T3	13		T4	60
valid_sources[0x45]	105601	1			T1	61		T3	1		T4	71
valid_sources[0x46]	130857	1			T1	43		T3	17		T4	60
valid_sources[0x47]	116031	1			T1	82		T2	3		T3	5
valid_sources[0x48]	109270	1			T1	79		T3	1		T4	79
valid_sources[0x49]	109666	1			T1	59		T3	6		T4	61
valid_sources[0x4a]	113976	1			T1	78		T2	1		T3	20
valid_sources[0x4b]	267234	1			T1	52		T2	2		T3	5
valid_sources[0x4c]	123225	1			T1	75		T3	10		T4	59
valid_sources[0x4d]	106331	1			T1	79		T3	7		T4	64
valid_sources[0x4e]	126310	1			T1	52		T3	1		T4	78
valid_sources[0x4f]	112879	1			T1	86		T2	3		T3	11
valid_sources[0x50]	133382	1			T1	83		T3	12		T4	67
valid_sources[0x51]	191904	1			T1	71		T3	17		T4	77
valid_sources[0x52]	104337	1			T1	74		T2	2		T3	7
valid_sources[0x53]	111378	1			T1	67		T2	1		T3	6
valid_sources[0x54]	114879	1			T1	69		T2	2		T3	20
valid_sources[0x55]	106507	1			T1	66		T2	1		T3	5
valid_sources[0x56]	112745	1			T1	64		T3	7		T4	67
valid_sources[0x57]	112751	1			T1	49		T3	15		T4	86
valid_sources[0x58]	349577	1			T1	80		T3	1		T4	52
valid_sources[0x59]	107320	1			T1	72		T2	1		T3	4
valid_sources[0x5a]	119044	1			T1	64		T3	11		T4	65
valid_sources[0x5b]	107209	1			T1	54		T3	27		T4	85
valid_sources[0x5c]	134011	1			T1	60		T2	1		T3	15
valid_sources[0x5d]	282725	1			T1	68		T3	5		T4	77
valid_sources[0x5e]	128390	1			T1	49		T2	2		T3	7
valid_sources[0x5f]	148598	1			T1	82		T2	1		T3	3
valid_sources[0x60]	110161	1			T1	53		T4	86		T7	1
valid_sources[0x61]	165383	1			T1	84		T3	1		T4	76
valid_sources[0x62]	132972	1			T1	58		T3	14		T4	65
valid_sources[0x63]	106281	1			T1	87		T3	8		T4	60
valid_sources[0x64]	110822	1			T1	76		T2	1		T3	2
valid_sources[0x65]	113785	1			T1	51		T3	3		T4	71
valid_sources[0x66]	116958	1			T1	81		T2	2		T3	7
valid_sources[0x67]	106974	1			T1	65		T3	8		T4	71
valid_sources[0x68]	106687	1			T1	93		T2	1		T3	12
valid_sources[0x69]	104823	1			T1	104		T3	6		T4	64
valid_sources[0x6a]	115440	1			T1	70		T3	3		T4	73
valid_sources[0x6b]	112853	1			T1	54		T2	3		T3	16
valid_sources[0x6c]	112254	1			T1	56		T2	4		T3	3
valid_sources[0x6d]	130286	1			T1	80		T2	1		T3	7
valid_sources[0x6e]	113891	1			T1	62		T3	7		T4	64
valid_sources[0x6f]	226521	1			T1	73		T2	3		T3	12
valid_sources[0x70]	114907	1			T1	63		T2	1		T3	11
valid_sources[0x71]	194060	1			T1	73		T2	4		T3	11
valid_sources[0x72]	113539	1			T1	66		T2	2		T3	24
valid_sources[0x73]	109912	1			T1	66		T3	4		T4	52
valid_sources[0x74]	120115	1			T1	82		T2	2		T4	57
valid_sources[0x75]	127199	1			T1	70		T2	1		T3	17
valid_sources[0x76]	110504	1			T1	70		T3	16		T4	51
valid_sources[0x77]	114596	1			T1	58		T2	2		T3	5
valid_sources[0x78]	105523	1			T1	61		T3	4		T4	62
valid_sources[0x79]	109902	1			T1	65		T3	6		T4	76
valid_sources[0x7a]	119800	1			T1	65		T3	18		T4	57
valid_sources[0x7b]	109238	1			T1	67		T2	2		T4	81
valid_sources[0x7c]	107748	1			T1	60		T2	1		T4	64
valid_sources[0x7d]	109018	1			T1	82		T2	3		T3	5
valid_sources[0x7e]	199395	1			T1	88		T2	1		T3	6
valid_sources[0x7f]	108540	1			T1	75		T2	3		T3	6
valid_sources[0x80]	117071	1			T1	71		T3	2		T4	68

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5655234

1

T1

8313

T2

63

T3

927

values[0x0]

all_enables

biggest_size

716294

1

T1

48

T2

8

T3

66

values[0x1]

all_enables

biggest_size

403770

1

T1

45

T2

6

T3

51