Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

109293

1

T2

1

T7

86

T11

640

ack

6916

1

T2

3

T7

1

T11

20

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	394	1			T11	2		T12	2		T16	4
high	24421	1			T2	1		T7	27		T11	139
med	43755	1			T7	32		T11	244		T12	397
sml	47174	1			T2	3		T7	28		T11	274
all_zero	465	1			T11	1		T12	5		T16	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58370

1

T2

1

T7

51

T11

332

auto[1]

57839

1

T2

3

T7

36

T11

328

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78892

1

T2

2

T7

57

T11

450

auto[1]

37317

1

T2

2

T7

30

T11

210

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112750

1

T2

1

T7

87

T11

651

auto[1]

3459

1

T2

3

T11

9

T12

16

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111480

1

T2

3

T7

86

T11

641

auto[1]

4729

1

T2

1

T7

1

T11

19

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111925

1

T2

3

T7

86

T11

642

auto[1]

4284

1

T2

1

T7

1

T11

18

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58370

1

T2

1

T7

51

T11

332

auto[1]

57839

1

T2

3

T7

36

T11

328

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78892

1

T2

2

T7

57

T11

450

auto[1]

37317

1

T2

2

T7

30

T11

210

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112750

1

T2

1

T7

87

T11

651

auto[1]

3459

1

T2

3

T11

9

T12

16

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111480

1

T2

3

T7

86

T11

641

auto[1]

4729

1

T2

1

T7

1

T11

19

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111925

1

T2

3

T7

86

T11

642

auto[1]

4284

1

T2

1

T7

1

T11

18

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T220

2

T234

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T235

1

T236

1

T237

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T238

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

142

1

T12

4

T90

2

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

72

1

T11

1

T16

1

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

59

1

T11

1

T12

1

T36

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

233

1

T11

1

T12

3

T90

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

105

1

T11

2

T16

1

T36

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

143

1

T11

1

T12

4

T90

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

228

1

T34

1

T73

1

T99

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

154

1

T11

1

T12

4

T90

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

119

1

T11

1

T12

3

T90

5

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T239

1

T240

1

T220

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T241

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T12

1

T242

1

T243

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	35425	1			T7	31		T11	208		T12	356
write_address_byte	4729	1			T2	1		T7	1		T11	19
read_with_ack	1018	1			T2	2		T33	19		T16	2
read_with_nack	2441	1			T2	1		T11	9		T12	16
stop_byte	4284	1			T2	1		T7	1		T11	18
write_address_byte_nak	2118	1			T11	16		T12	30		T16	8
data_byte_nack	109293	1			T2	1		T7	86		T11	640
stop_byte_nack	2709	1			T7	1		T11	15		T12	29
nakok_byte_nack	54413	1			T2	1		T7	36		T11	322
nakok_addr_byte_nack	1001	1			T11	6		T12	18		T16	3