Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29021441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7471439

1

T2

6399

T3

220

T6

66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33455185	1			T1	1		T2	13978		T3	17978
values[0x0]	1517440	1			T2	2346		T3	316		T6	40
values[0x1]	1520255	1			T1	2		T2	2315		T3	304

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21071610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15421270

1

T2

9436

T3

7157

T6

101

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	131865	1			T2	80		T3	65		T6	1
valid_sources[0x01]	132548	1			T2	70		T3	93		T18	1
valid_sources[0x02]	152308	1			T2	78		T3	76		T18	3
valid_sources[0x03]	129141	1			T2	62		T3	52		T11	136
valid_sources[0x04]	124739	1			T2	80		T3	79		T18	5
valid_sources[0x05]	129620	1			T1	1		T2	77		T3	85
valid_sources[0x06]	120560	1			T2	66		T3	65		T18	2
valid_sources[0x07]	127152	1			T2	56		T3	53		T18	7
valid_sources[0x08]	124125	1			T2	62		T3	70		T6	13
valid_sources[0x09]	144562	1			T2	62		T3	74		T18	2
valid_sources[0x0a]	119722	1			T2	56		T3	68		T11	145
valid_sources[0x0b]	137911	1			T2	79		T3	64		T18	4
valid_sources[0x0c]	127665	1			T2	58		T3	84		T11	137
valid_sources[0x0d]	124392	1			T2	65		T3	68		T6	1
valid_sources[0x0e]	123000	1			T2	68		T3	86		T6	1
valid_sources[0x0f]	125804	1			T2	84		T3	70		T11	141
valid_sources[0x10]	126011	1			T2	83		T3	67		T18	2
valid_sources[0x11]	125058	1			T2	81		T3	57		T18	3
valid_sources[0x12]	128058	1			T2	85		T3	80		T11	122
valid_sources[0x13]	128372	1			T2	69		T3	81		T18	1
valid_sources[0x14]	128290	1			T2	80		T3	75		T11	100
valid_sources[0x15]	132622	1			T2	72		T3	60		T18	4
valid_sources[0x16]	138460	1			T2	82		T3	68		T18	1
valid_sources[0x17]	132292	1			T2	65		T3	74		T6	25
valid_sources[0x18]	127964	1			T2	91		T3	68		T18	4
valid_sources[0x19]	352525	1			T2	76		T3	68		T11	139
valid_sources[0x1a]	126094	1			T2	66		T3	81		T18	1
valid_sources[0x1b]	190720	1			T2	63		T3	70		T18	5
valid_sources[0x1c]	135791	1			T2	51		T3	80		T18	3
valid_sources[0x1d]	122431	1			T2	77		T3	78		T18	1
valid_sources[0x1e]	138913	1			T2	78		T3	65		T18	1
valid_sources[0x1f]	130397	1			T2	64		T3	66		T18	1
valid_sources[0x20]	141500	1			T2	66		T3	64		T18	1
valid_sources[0x21]	129075	1			T2	47		T3	81		T18	1
valid_sources[0x22]	125080	1			T2	70		T3	77		T18	2
valid_sources[0x23]	133356	1			T2	76		T3	85		T6	1
valid_sources[0x24]	130108	1			T2	71		T3	77		T18	2
valid_sources[0x25]	208494	1			T2	83		T3	66		T18	2
valid_sources[0x26]	202997	1			T2	62		T3	70		T6	1
valid_sources[0x27]	140459	1			T2	77		T3	79		T18	1
valid_sources[0x28]	138252	1			T2	75		T3	76		T11	145
valid_sources[0x29]	127062	1			T2	83		T3	83		T18	5
valid_sources[0x2a]	126856	1			T2	67		T3	64		T18	1
valid_sources[0x2b]	121855	1			T2	53		T3	79		T18	2
valid_sources[0x2c]	124572	1			T2	69		T3	71		T18	2
valid_sources[0x2d]	127166	1			T2	67		T3	72		T11	105
valid_sources[0x2e]	130839	1			T2	59		T3	59		T18	3
valid_sources[0x2f]	126494	1			T2	80		T3	75		T11	113
valid_sources[0x30]	145590	1			T2	70		T3	78		T11	112
valid_sources[0x31]	130189	1			T2	79		T3	80		T11	101
valid_sources[0x32]	143630	1			T2	70		T3	63		T11	155
valid_sources[0x33]	223768	1			T2	74		T3	59		T11	144
valid_sources[0x34]	121918	1			T2	85		T3	79		T11	137
valid_sources[0x35]	131535	1			T2	58		T3	84		T18	3
valid_sources[0x36]	129715	1			T2	75		T3	71		T11	129
valid_sources[0x37]	122466	1			T2	86		T3	70		T18	1
valid_sources[0x38]	134065	1			T2	84		T3	72		T11	104
valid_sources[0x39]	126424	1			T2	74		T3	83		T11	95
valid_sources[0x3a]	137167	1			T1	1		T2	80		T3	72
valid_sources[0x3b]	127386	1			T2	79		T3	72		T18	1
valid_sources[0x3c]	152583	1			T2	69		T3	72		T18	1
valid_sources[0x3d]	125825	1			T2	68		T3	67		T11	158
valid_sources[0x3e]	130941	1			T2	66		T3	80		T18	1
valid_sources[0x3f]	134286	1			T2	63		T3	60		T18	2
valid_sources[0x40]	368682	1			T2	79		T3	68		T11	110
valid_sources[0x41]	134605	1			T2	85		T3	67		T18	2
valid_sources[0x42]	166488	1			T2	76		T3	67		T18	3
valid_sources[0x43]	124219	1			T2	74		T3	69		T18	2
valid_sources[0x44]	131032	1			T2	82		T3	93		T18	1
valid_sources[0x45]	124232	1			T2	79		T3	64		T18	4
valid_sources[0x46]	129245	1			T2	65		T3	72		T18	2
valid_sources[0x47]	127348	1			T2	64		T3	92		T11	137
valid_sources[0x48]	133114	1			T2	76		T3	73		T18	3
valid_sources[0x49]	129232	1			T2	88		T3	77		T11	95
valid_sources[0x4a]	128141	1			T2	71		T3	74		T18	2
valid_sources[0x4b]	142763	1			T2	58		T3	75		T18	1
valid_sources[0x4c]	148304	1			T2	82		T3	76		T11	142
valid_sources[0x4d]	137745	1			T2	86		T3	64		T18	2
valid_sources[0x4e]	127840	1			T2	82		T3	66		T18	1
valid_sources[0x4f]	131750	1			T2	74		T3	58		T11	140
valid_sources[0x50]	128890	1			T2	94		T3	65		T18	1
valid_sources[0x51]	161618	1			T2	80		T3	61		T11	114
valid_sources[0x52]	141121	1			T2	73		T3	75		T18	1
valid_sources[0x53]	137404	1			T2	66		T3	69		T18	2
valid_sources[0x54]	129523	1			T2	87		T3	53		T18	3
valid_sources[0x55]	141921	1			T2	96		T3	73		T11	119
valid_sources[0x56]	128934	1			T2	75		T3	72		T18	1
valid_sources[0x57]	138709	1			T2	87		T3	66		T11	129
valid_sources[0x58]	298424	1			T2	81		T3	72		T18	2
valid_sources[0x59]	129013	1			T2	77		T3	62		T18	3
valid_sources[0x5a]	125774	1			T2	72		T3	76		T11	113
valid_sources[0x5b]	128262	1			T2	70		T3	64		T18	1
valid_sources[0x5c]	127716	1			T2	81		T3	80		T18	3
valid_sources[0x5d]	127169	1			T2	75		T3	66		T6	26
valid_sources[0x5e]	195158	1			T2	70		T3	67		T18	1
valid_sources[0x5f]	132212	1			T2	64		T3	73		T11	116
valid_sources[0x60]	132253	1			T2	65		T3	80		T18	4
valid_sources[0x61]	133108	1			T2	89		T3	75		T18	1
valid_sources[0x62]	123513	1			T2	90		T3	67		T11	117
valid_sources[0x63]	131723	1			T2	74		T3	71		T11	134
valid_sources[0x64]	130010	1			T2	81		T3	82		T18	1
valid_sources[0x65]	123834	1			T2	76		T3	82		T18	1
valid_sources[0x66]	124570	1			T2	75		T3	91		T18	5
valid_sources[0x67]	137258	1			T2	59		T3	73		T11	109
valid_sources[0x68]	133975	1			T2	68		T3	78		T18	1
valid_sources[0x69]	122827	1			T2	78		T3	90		T18	2
valid_sources[0x6a]	128953	1			T2	64		T3	69		T18	2
valid_sources[0x6b]	125238	1			T2	58		T3	60		T11	139
valid_sources[0x6c]	131132	1			T2	54		T3	61		T11	143
valid_sources[0x6d]	125838	1			T2	76		T3	69		T18	1
valid_sources[0x6e]	136532	1			T2	51		T3	72		T18	1
valid_sources[0x6f]	120260	1			T2	73		T3	65		T11	121
valid_sources[0x70]	126125	1			T2	65		T3	84		T11	146
valid_sources[0x71]	136179	1			T2	64		T3	76		T18	2
valid_sources[0x72]	135603	1			T2	76		T3	90		T6	1
valid_sources[0x73]	119737	1			T2	74		T3	69		T18	2
valid_sources[0x74]	134186	1			T2	71		T3	75		T18	4
valid_sources[0x75]	133037	1			T2	81		T3	74		T11	117
valid_sources[0x76]	141376	1			T2	71		T3	67		T18	2
valid_sources[0x77]	174062	1			T2	60		T3	79		T11	132
valid_sources[0x78]	120385	1			T2	69		T3	69		T18	1
valid_sources[0x79]	145791	1			T2	85		T3	78		T18	2
valid_sources[0x7a]	124501	1			T2	76		T3	57		T11	148
valid_sources[0x7b]	137903	1			T2	75		T3	54		T6	13
valid_sources[0x7c]	120479	1			T2	74		T3	66		T18	1
valid_sources[0x7d]	121789	1			T2	77		T3	81		T11	134
valid_sources[0x7e]	121900	1			T2	55		T3	83		T18	2
valid_sources[0x7f]	121921	1			T2	75		T3	77		T6	12
valid_sources[0x80]	132192	1			T2	81		T3	90		T11	125

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6280833

1

T2

4593

T3

52

T6

4

values[0x0]

all_enables

biggest_size

760780

1

T2

1181

T3

106

T6

30

values[0x1]

all_enables

biggest_size

429826

1

T2

625

T3

62

T6

32