Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215649222	7580	0	0
ctrl_rd_A	215649222	1265	0	0
host_fifo_config_rd_A	215649222	4089	0	0
host_timeout_ctrl_rd_A	215649222	859	0	0
intr_enable_rd_A	215649222	3893	0	0
ovrd_rd_A	215649222	2158	0	0
target_fifo_config_rd_A	215649222	1346	0	0
target_id_rd_A	215649222	1504	0	0
target_timeout_ctrl_rd_A	215649222	1147	0	0
timeout_ctrl_rd_A	215649222	1186	0	0
timing0_rd_A	215649222	1168	0	0
timing1_rd_A	215649222	1082	0	0
timing2_rd_A	215649222	1101	0	0
timing3_rd_A	215649222	1063	0	0
timing4_rd_A	215649222	1114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	7580	0	0
T111	2143	147	0	0
T112	10803	5	0	0
T113	1877	155	0	0
T129	2394	29	0	0
T130	7619	4	0	0
T131	2207	345	0	0
T133	2594	172	0	0
T134	1783	28	0	0
T150	3420	19	0	0
T151	1416	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1265	0	0
T83	1455	4	0	0
T142	7733	16	0	0
T143	11412	88	0	0
T150	3420	18	0	0
T155	1494	3	0	0
T156	1267	6	0	0
T157	1976	4	0	0
T167	5037	9	0	0
T172	1721	2	0	0
T173	1998	7	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	4089	0	0
T4	26433	0	0	0
T5	92969	0	0	0
T12	396593	186	0	0
T21	75477	0	0	0
T33	146859	0	0	0
T37	8296	0	0	0
T38	14364	0	0	0
T52	123183	0	0	0
T55	11482	0	0	0
T87	14466	0	0	0
T174	0	185	0	0
T175	0	241	0	0
T176	0	102	0	0
T177	0	176	0	0
T178	0	199	0	0
T179	0	185	0	0
T180	0	252	0	0
T181	0	223	0	0
T182	0	198	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	859	0	0
T142	7733	7	0	0
T143	11412	36	0	0
T150	3420	14	0	0
T156	1267	4	0	0
T157	1976	5	0	0
T167	5037	18	0	0
T172	1721	3	0	0
T183	1666	10	0	0
T184	12771	77	0	0
T185	9738	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	3893	0	0
T66	160824	0	0	0
T86	478904	34	0	0
T142	0	7	0	0
T150	0	15	0	0
T167	0	45	0	0
T186	0	38	0	0
T187	0	9	0	0
T188	0	16	0	0
T189	0	14	0	0
T190	0	11	0	0
T191	0	1	0	0
T192	372115	0	0	0
T193	6177	0	0	0
T194	134495	0	0	0
T195	234636	0	0	0
T196	136941	0	0	0
T197	32284	0	0	0
T198	262127	0	0	0
T199	1122	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	2158	0	0
T20	1563	31	0	0
T22	58502	0	0	0
T25	103317	0	0	0
T27	3240	0	0	0
T56	1021	0	0	0
T59	65540	0	0	0
T92	113877	0	0	0
T93	447045	0	0	0
T105	265564	0	0	0
T106	18474	0	0	0
T200	0	29	0	0
T201	0	26	0	0
T202	0	37	0	0
T203	0	68	0	0
T204	0	28	0	0
T205	0	39	0	0
T206	0	76	0	0
T207	0	56	0	0
T208	0	46	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1346	0	0
T142	7733	4	0	0
T143	11412	77	0	0
T150	3420	6	0	0
T155	1494	10	0	0
T157	1976	5	0	0
T167	5037	28	0	0
T172	1721	3	0	0
T173	1998	2	0	0
T184	12771	146	0	0
T185	9738	19	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1504	0	0
T83	1455	11	0	0
T136	6596	101	0	0
T142	7733	22	0	0
T143	11412	102	0	0
T150	3420	25	0	0
T155	1494	10	0	0
T156	1267	15	0	0
T157	1976	2	0	0
T167	5037	14	0	0
T184	12771	204	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1147	0	0
T136	6596	56	0	0
T143	11412	74	0	0
T150	3420	10	0	0
T155	1494	4	0	0
T156	1267	3	0	0
T157	1976	9	0	0
T167	5037	29	0	0
T172	1721	1	0	0
T183	1666	2	0	0
T184	12771	108	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1186	0	0
T83	1455	1	0	0
T142	7733	13	0	0
T150	3420	27	0	0
T155	1494	2	0	0
T156	1267	6	0	0
T157	1976	7	0	0
T167	5037	53	0	0
T172	1721	9	0	0
T173	1998	13	0	0
T183	1666	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1168	0	0
T83	1455	8	0	0
T143	11412	58	0	0
T150	3420	18	0	0
T155	1494	7	0	0
T156	1267	4	0	0
T157	1976	4	0	0
T167	5037	21	0	0
T172	1721	4	0	0
T184	12771	140	0	0
T185	9738	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1082	0	0
T83	1455	10	0	0
T142	7733	10	0	0
T143	11412	54	0	0
T150	3420	12	0	0
T156	1267	2	0	0
T157	1976	3	0	0
T167	5037	29	0	0
T172	1721	8	0	0
T173	1998	14	0	0
T183	1666	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1101	0	0
T83	1455	13	0	0
T142	7733	4	0	0
T150	3420	3	0	0
T155	1494	1	0	0
T156	1267	4	0	0
T157	1976	10	0	0
T167	5037	35	0	0
T172	1721	1	0	0
T173	1998	3	0	0
T183	1666	15	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1063	0	0
T83	1455	6	0	0
T142	7733	2	0	0
T143	11412	71	0	0
T150	3420	12	0	0
T155	1494	12	0	0
T156	1267	8	0	0
T157	1976	3	0	0
T172	1721	3	0	0
T173	1998	6	0	0
T183	1666	11	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215649222	1114	0	0
T83	1455	4	0	0
T143	11412	72	0	0
T150	3420	14	0	0
T155	1494	3	0	0
T156	1267	5	0	0
T167	5037	21	0	0
T172	1721	2	0	0
T183	1666	11	0	0
T184	12771	124	0	0
T185	9738	3	0	0