Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.59	92.59	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	92.59	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	4	23	85.19

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	4	23	85.19	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

109209

1

T2

704

T6

2577

T23

93

ack

9433

1

T2

22

T6

58

T10

19

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	424	1			T2	3		T6	10		T72	1
high	24550	1			T2	136		T6	525		T10	2
med	43928	1			T2	271		T6	1043		T10	3
sml	49311	1			T2	314		T6	1046		T10	14
all_zero	429	1			T2	2		T6	11		T28	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59616

1

T2

370

T6

1324

T10

12

auto[1]

59026

1

T2

356

T6

1311

T10

7

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80967

1

T2

485

T6

1772

T10

19

auto[1]

37675

1

T2

241

T6

863

T23

27

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113393

1

T2

716

T6

2605

T10

10

auto[1]

5249

1

T2

10

T6

30

T10

9

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112721

1

T2

705

T6

2582

T10

9

auto[1]

5921

1

T2

21

T6

53

T10

10

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113385

1

T2

706

T6

2595

T10

10

auto[1]

5257

1

T2

20

T6

40

T10

9

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59616

1

T2

370

T6

1324

T10

12

auto[1]

59026

1

T2

356

T6

1311

T10

7

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80967

1

T2

485

T6

1772

T10

19

auto[1]

37675

1

T2

241

T6

863

T23

27

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113393

1

T2

716

T6

2605

T10

10

auto[1]

5249

1

T2

10

T6

30

T10

9

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112721

1

T2

705

T6

2582

T10

9

auto[1]

5921

1

T2

21

T6

53

T10

10

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113385

1

T2

706

T6

2595

T10

10

auto[1]

5257

1

T2

20

T6

40

T10

9

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	4	23	85.19	2
Automatically Generated Cross Bins	15	2	13	86.67	2
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T225

1

T226

1

T227

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

112

1

T6

5

T24

1

T80

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

70

1

T2

1

T6

2

T80

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

80

1

T2

1

T28

1

T73

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

227

1

T2

1

T6

9

T28

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

136

1

T2

1

T6

6

T23

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

113

1

T2

2

T6

3

T28

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

251

1

T2

2

T6

3

T24

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

128

1

T6

1

T73

3

T80

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

112

1

T2

3

T6

2

T80

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T152

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T80

1

T228

1

T229

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T230

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	35291	1			T2	242		T6	822		T23	20
write_address_byte	5921	1			T2	21		T6	53		T10	10
read_with_ack	1904	1			T6	7		T51	8		T24	3
read_with_nack	3345	1			T2	10		T6	23		T10	9
stop_byte	5257	1			T2	20		T6	40		T10	9
write_address_byte_nak	2352	1			T2	18		T6	43		T23	8
data_byte_nack	109209	1			T2	704		T6	2577		T23	93
stop_byte_nack	2891	1			T2	17		T6	34		T23	6
nakok_byte_nack	54313	1			T2	345		T6	1280		T23	56
nakok_addr_byte_nack	1208	1			T2	6		T6	22		T23	5