Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_rd_wr_cg	85.71	1	100	1	64	64

---

Group Instance : i2c_rd_wr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance i2c_rd_wr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	24	4	20	83.33

Variables for Group Instance i2c_rd_wr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
address_match	2	0	2	100.00	100	1	1	2
cp_address_match	4	0	4	100.00	100	1	1	0
cp_read_byte	5	1	4	80.00	100	1	1	0
cp_write_byte	5	1	4	80.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_rd_wr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_address_match_x_ip_mode	4	0	4	100.00	100	1	1	0
cross_write_byte_x_ip_mode	10	2	8	80.00	100	1	1	0
cross_read_byte_x_ip_mode	10	2	8	80.00	100	1	1	0

Summary for Variable address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for address_match

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12161872

1

T1

4971

T5

10198

T8

14140

auto[1]

11303343

1

T1

119

T2

37512

T3

10

---

Summary for Variable cp_address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_address_match

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_addr_no_match	6795901	1			T5	4448		T8	7530		T16	28226
read_addr_match	8205987	1			T2	19877		T4	1765		T5	145
write_addr_no_match	5183949	1			T1	4947		T5	5726		T8	6596
write_addr_match	2999386	1			T1	117		T2	17615		T5	175

---

Summary for Variable cp_read_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_read_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	3052937	1			T2	4333		T4	440		T5	1049
med	5824706	1			T2	8444		T4	597		T5	1810
low	5980991	1			T2	6918		T4	697		T5	1719
all_zero	143254	1			T2	182		T4	31		T5	15

---

Summary for Variable cp_write_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_write_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	1669990	1			T1	917		T2	3981		T5	1281
med	3187765	1			T1	2369		T2	7111		T5	2114
low	3244085	1			T1	1732		T2	6392		T5	2469
all_zero	81495	1			T1	46		T2	131		T5	37

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

12825617

1

T1

5090

T5

10520

T8

15120

host

10639598

1

T2

37512

T3

10

T4

1786

---

Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins

address_match

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

device

12161740

1

T1

4971

T5

10198

T8

14140

auto[0]

host

132

1

T201

2

T141

1

T96

4

auto[1]

device

663877

1

T1

119

T5

322

T8

980

auto[1]

host

10639466

1

T2

37512

T3

10

T4

1786

---

Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1102891	1			T1	917		T5	1281		T8	1514
high	host	567099	1			T2	3981		T6	9868		T23	172
med	device	2115360	1			T1	2369		T5	2114		T8	2742
med	host	1072405	1			T2	7111		T6	19954		T23	820
low	device	2177651	1			T1	1732		T5	2469		T8	2684
low	host	1066434	1			T2	6392		T6	33841		T38	12
all_zero	device	50988	1			T1	46		T5	37		T8	92
all_zero	host	30507	1			T2	131		T6	401		T38	7

---

Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1102891	1			T1	917		T5	1281		T8	1514
high	host	567099	1			T2	3981		T6	9868		T23	172
med	device	2115360	1			T1	2369		T5	2114		T8	2742
med	host	1072405	1			T2	7111		T6	19954		T23	820
low	device	2177651	1			T1	1732		T5	2469		T8	2684
low	host	1066434	1			T2	6392		T6	33841		T38	12
all_zero	device	50988	1			T1	46		T5	37		T8	92
all_zero	host	30507	1			T2	131		T6	401		T38	7