Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29294491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7005130

1

T1

97

T2

28782

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35598281	1			T1	506		T2	116644		T3	91
values[0x0]	350858	1			T1	9		T2	429		T3	39
values[0x1]	350482	1			T1	8		T2	447		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20953293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15346328

1

T1

224

T2

54669

T3

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	137058	1			T2	398		T4	10		T5	36
valid_sources[0x01]	141863	1			T1	1		T2	435		T4	24
valid_sources[0x02]	119250	1			T1	1		T2	410		T4	26
valid_sources[0x03]	136987	1			T1	4		T2	513		T4	21
valid_sources[0x04]	122853	1			T1	1		T2	444		T3	2
valid_sources[0x05]	136389	1			T1	1		T2	415		T4	12
valid_sources[0x06]	129069	1			T1	1		T2	417		T3	1
valid_sources[0x07]	144711	1			T1	1		T2	406		T4	12
valid_sources[0x08]	172791	1			T1	2		T2	366		T4	16
valid_sources[0x09]	133804	1			T1	1		T2	425		T3	3
valid_sources[0x0a]	152738	1			T1	6		T2	424		T4	12
valid_sources[0x0b]	140786	1			T1	1		T2	431		T4	7
valid_sources[0x0c]	132898	1			T1	4		T2	456		T4	8
valid_sources[0x0d]	143651	1			T1	5		T2	478		T4	19
valid_sources[0x0e]	185107	1			T1	1		T2	428		T3	2
valid_sources[0x0f]	140097	1			T1	1		T2	499		T4	23
valid_sources[0x10]	130242	1			T1	5		T2	454		T3	8
valid_sources[0x11]	138590	1			T2	427		T4	24		T5	39
valid_sources[0x12]	127795	1			T1	4		T2	452		T4	20
valid_sources[0x13]	130213	1			T1	1		T2	415		T4	24
valid_sources[0x14]	137703	1			T1	2		T2	458		T3	5
valid_sources[0x15]	135579	1			T1	1		T2	503		T4	31
valid_sources[0x16]	138315	1			T1	3		T2	391		T4	17
valid_sources[0x17]	128445	1			T1	3		T2	438		T3	4
valid_sources[0x18]	216216	1			T2	464		T4	15		T5	45
valid_sources[0x19]	130214	1			T1	2		T2	425		T4	26
valid_sources[0x1a]	140984	1			T1	1		T2	539		T4	29
valid_sources[0x1b]	130317	1			T1	2		T2	542		T4	14
valid_sources[0x1c]	129063	1			T1	1		T2	438		T4	36
valid_sources[0x1d]	153289	1			T1	1		T2	495		T3	1
valid_sources[0x1e]	130044	1			T2	460		T4	22		T5	54
valid_sources[0x1f]	142499	1			T2	499		T3	3		T4	14
valid_sources[0x20]	178273	1			T1	3		T2	535		T4	30
valid_sources[0x21]	125653	1			T2	391		T4	11		T5	39
valid_sources[0x22]	131627	1			T2	515		T4	31		T5	48
valid_sources[0x23]	123620	1			T1	2		T2	453		T3	1
valid_sources[0x24]	120257	1			T2	430		T3	2		T4	33
valid_sources[0x25]	144520	1			T1	5		T2	484		T4	21
valid_sources[0x26]	135134	1			T1	3		T2	473		T4	17
valid_sources[0x27]	119793	1			T1	2		T2	403		T4	14
valid_sources[0x28]	126217	1			T1	1		T2	422		T4	16
valid_sources[0x29]	121743	1			T1	4		T2	426		T4	13
valid_sources[0x2a]	188524	1			T1	2		T2	570		T3	3
valid_sources[0x2b]	136863	1			T1	1		T2	394		T3	3
valid_sources[0x2c]	135314	1			T2	515		T4	27		T5	44
valid_sources[0x2d]	133608	1			T1	1		T2	471		T4	17
valid_sources[0x2e]	211298	1			T1	4		T2	486		T4	18
valid_sources[0x2f]	123088	1			T2	573		T4	29		T5	31
valid_sources[0x30]	129531	1			T1	5		T2	612		T4	10
valid_sources[0x31]	133965	1			T1	1		T2	435		T4	15
valid_sources[0x32]	125006	1			T1	1		T2	416		T3	1
valid_sources[0x33]	125408	1			T1	6		T2	449		T3	3
valid_sources[0x34]	123428	1			T1	1		T2	526		T3	2
valid_sources[0x35]	127884	1			T1	2		T2	509		T4	16
valid_sources[0x36]	136656	1			T2	457		T4	7		T5	52
valid_sources[0x37]	127295	1			T1	1		T2	481		T4	23
valid_sources[0x38]	137559	1			T1	3		T2	482		T4	18
valid_sources[0x39]	122191	1			T2	506		T3	3		T4	12
valid_sources[0x3a]	131484	1			T1	1		T2	401		T3	1
valid_sources[0x3b]	145709	1			T1	4		T2	532		T4	10
valid_sources[0x3c]	124887	1			T1	3		T2	388		T3	2
valid_sources[0x3d]	129514	1			T1	1		T2	460		T3	1
valid_sources[0x3e]	213763	1			T2	451		T4	15		T5	35
valid_sources[0x3f]	126431	1			T2	446		T3	2		T4	9
valid_sources[0x40]	138939	1			T1	3		T2	503		T4	25
valid_sources[0x41]	135306	1			T2	460		T4	27		T5	61
valid_sources[0x42]	117548	1			T1	2		T2	486		T4	31
valid_sources[0x43]	131505	1			T1	2		T2	495		T4	35
valid_sources[0x44]	473054	1			T2	470		T3	3		T4	25
valid_sources[0x45]	130011	1			T2	544		T4	18		T5	57
valid_sources[0x46]	272441	1			T2	468		T4	10		T5	45
valid_sources[0x47]	125521	1			T1	1		T2	425		T3	7
valid_sources[0x48]	126735	1			T1	7		T2	423		T4	15
valid_sources[0x49]	354478	1			T2	391		T4	28		T5	43
valid_sources[0x4a]	129825	1			T2	442		T3	5		T4	21
valid_sources[0x4b]	126416	1			T1	1		T2	535		T3	3
valid_sources[0x4c]	128813	1			T1	2		T2	390		T3	4
valid_sources[0x4d]	122377	1			T1	1		T2	444		T4	26
valid_sources[0x4e]	133395	1			T1	1		T2	486		T4	21
valid_sources[0x4f]	121808	1			T1	3		T2	456		T3	2
valid_sources[0x50]	149016	1			T1	2		T2	545		T4	31
valid_sources[0x51]	128881	1			T2	488		T3	1		T4	29
valid_sources[0x52]	121383	1			T1	1		T2	439		T4	23
valid_sources[0x53]	124035	1			T1	2		T2	461		T4	12
valid_sources[0x54]	126845	1			T1	1		T2	433		T4	15
valid_sources[0x55]	116637	1			T1	5		T2	462		T3	4
valid_sources[0x56]	133766	1			T2	492		T4	33		T5	39
valid_sources[0x57]	120274	1			T1	2		T2	485		T4	30
valid_sources[0x58]	126267	1			T2	493		T4	8		T5	45
valid_sources[0x59]	135342	1			T1	3		T2	481		T4	10
valid_sources[0x5a]	132662	1			T1	4		T2	616		T4	17
valid_sources[0x5b]	133534	1			T1	1		T2	367		T4	25
valid_sources[0x5c]	135494	1			T1	2		T2	472		T3	2
valid_sources[0x5d]	151197	1			T1	3		T2	430		T3	2
valid_sources[0x5e]	131718	1			T1	2		T2	438		T4	21
valid_sources[0x5f]	139985	1			T1	1		T2	428		T4	8
valid_sources[0x60]	131364	1			T1	2		T2	472		T4	22
valid_sources[0x61]	126312	1			T1	1		T2	436		T3	2
valid_sources[0x62]	272823	1			T1	1		T2	488		T4	10
valid_sources[0x63]	166584	1			T1	1		T2	433		T4	23
valid_sources[0x64]	117942	1			T1	1		T2	479		T4	28
valid_sources[0x65]	133256	1			T1	6		T2	437		T3	2
valid_sources[0x66]	136243	1			T1	1		T2	461		T4	20
valid_sources[0x67]	118140	1			T2	425		T4	14		T5	42
valid_sources[0x68]	122878	1			T1	3		T2	444		T4	12
valid_sources[0x69]	131704	1			T1	2		T2	431		T4	27
valid_sources[0x6a]	129627	1			T2	371		T4	9		T5	45
valid_sources[0x6b]	289794	1			T1	1		T2	476		T3	3
valid_sources[0x6c]	187444	1			T2	526		T4	22		T5	42
valid_sources[0x6d]	129772	1			T1	4		T2	448		T4	14
valid_sources[0x6e]	139371	1			T1	2		T2	533		T4	15
valid_sources[0x6f]	127601	1			T1	2		T2	479		T3	2
valid_sources[0x70]	131356	1			T2	445		T4	26		T5	45
valid_sources[0x71]	122516	1			T2	499		T3	1		T4	18
valid_sources[0x72]	126224	1			T2	436		T4	21		T5	41
valid_sources[0x73]	138561	1			T1	3		T2	459		T4	18
valid_sources[0x74]	130987	1			T1	1		T2	370		T4	13
valid_sources[0x75]	132210	1			T1	3		T2	386		T3	2
valid_sources[0x76]	133948	1			T1	3		T2	392		T4	19
valid_sources[0x77]	133279	1			T1	2		T2	411		T4	16
valid_sources[0x78]	134587	1			T1	3		T2	499		T4	26
valid_sources[0x79]	136843	1			T1	3		T2	455		T4	4
valid_sources[0x7a]	121175	1			T1	7		T2	366		T4	17
valid_sources[0x7b]	126697	1			T1	2		T2	493		T4	19
valid_sources[0x7c]	119358	1			T2	431		T4	17		T5	41
valid_sources[0x7d]	120970	1			T1	1		T2	358		T3	1
valid_sources[0x7e]	128106	1			T1	6		T2	459		T4	17
valid_sources[0x7f]	257225	1			T1	1		T2	427		T3	1
valid_sources[0x80]	133044	1			T1	1		T2	362		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6707166

1

T1

83

T2

28368

T3

1

values[0x0]

all_enables

biggest_size

176895

1

T1

6

T2

231

T3

20

values[0x1]

all_enables

biggest_size

121069

1

T1

8

T2

183

T3

12