Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_target_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	2231	1			T2	1		T6	5		T10	7
b2b_read_same_addr	207	1			T6	6		T23	1		T28	3
write_after_read_different_addr	2209	1			T2	5		T6	10		T10	4
write_after_read_same_addr	34	1			T6	1		T15	1		T28	1
read_after_write_different_addr	2235	1			T2	4		T6	11		T10	5
read_after_write_same_addr	35	1			T80	2		T236	1		T237	1
b2b_write_different_addr	2127	1			T2	11		T6	20		T10	2
b2b_write_same_addr	208	1			T6	4		T23	1		T24	1

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	10	1			T66	1		T61	2		T238	1
b2b_read_same_addr	5	1			T239	1		T67	1		T240	1
write_after_read_different_addr	17059	1			T5	10		T32	22		T17	29
write_after_read_same_addr	108	1			T241	7		T239	15		T242	19
read_after_write_different_addr	17051	1			T5	10		T32	22		T17	29
read_after_write_same_addr	107	1			T241	6		T239	15		T242	19
b2b_write_different_addr	30080	1			T5	20		T8	76		T16	284
b2b_write_same_addr	245643	1			T1	195		T5	250		T8	319